S32K14X系列MCU硬件手册.pdf(共2023页)

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【实例简介】
汽车电子级芯片，s32K系列单片机参考手册
【实例截图】
【核心代码】
Contents
Section number Title Page
Chapter 1
About This Manual
1 Audience....................................................................................................................................................................... 49
2 Organization..................................................................................................................................................................49
3 Module descriptions......................................................................................................................................................49
3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 50
3.2 Example: chip-specific information that refers to a different chapter........................................................... 51
4 Register descriptions.....................................................................................................................................................52
5 Conventions.................................................................................................................................................................. 53
5.1 Notes, Cautions, and Warnings......................................................................................................................53
5.2 Numbering systems........................................................................................................................................53
5.3 Typographic notation..................................................................................................................................... 54
5.4 Special terms.................................................................................................................................................. 54
Chapter 2
Introduction
1 Overview.......................................................................................................................................................................57
2 S32K1xx Series introduction........................................................................................................................................ 57
2.1 S32K14x.........................................................................................................................................................57
2.2 S32K11x ........................................................................................................................................................59
3 Feature summary...........................................................................................................................................................60
4 Block diagram...............................................................................................................................................................63
5 Feature comparison.......................................................................................................................................................64
5.1 Differences between S32K14x and S32K11x................................................................................................66
6 Applications.................................................................................................................................................................. 67
7 Module functional categories........................................................................................................................................68
7.1 Arm Cortex-M4F Core Modules....................................................................................................................69
7.2 Arm Cortex-M0  Core Modules....................................................................................................................70
7.3 System modules............................................................................................................................................. 70
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7.4 Memories and memory interfaces..................................................................................................................71
7.5 Power Management........................................................................................................................................72
7.6 Clocking......................................................................................................................................................... 72
7.7 Analog modules............................................................................................................................................. 73
7.8 Timer modules............................................................................................................................................... 73
7.9 Communication interfaces............................................................................................................................. 74
7.10 Debug modules.............................................................................................................................................. 75
Chapter 3
Memory Map
1 Introduction...................................................................................................................................................................77
2 SRAM memory map.....................................................................................................................................................77
2.1 S32K14x: SRAM memory map ....................................................................................................................77
2.2 S32K11x: SRAM memory map ....................................................................................................................77
3 Flash memory map........................................................................................................................................................78
4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................78
4.1 Read-after-write sequence and required serialization of memory operations................................................79
5 Private Peripheral Bus (PPB) memory map..................................................................................................................80
6 Aliased bit-band regions for CM4 core........................................................................................................................ 81
Chapter 4
Signal Multiplexing and Pin Assignment
1 Introduction...................................................................................................................................................................83
2 Functional description...................................................................................................................................................83
3 Pad description..............................................................................................................................................................84
4 Default pad state........................................................................................................................................................... 85
5 Signal Multiplexing sheet............................................................................................................................................. 86
5.1 IO Signal Table ............................................................................................................................................. 86
5.2 Input muxing table......................................................................................................................................... 88
6 Pinout diagrams............................................................................................................................................................ 89
Chapter 5
Security Overview
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1 Introduction...................................................................................................................................................................91
2 Device security..............................................................................................................................................................91
2.1 Flash memory security................................................................................................................................... 91
2.2 Cryptographic Services Engine (CSEc) security features..............................................................................92
2.3 Device Boot modes........................................................................................................................................ 93
3 Security use case examples...........................................................................................................................................93
3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 93
3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 94
3.3 Secure communication...................................................................................................................................95
3.4 Component protection....................................................................................................................................96
3.5 Message-authentication example................................................................................................................... 97
4 Steps required before failure analysis...........................................................................................................................98
5 Security programming flow example (Secure Boot).................................................................................................... 99
Chapter 6
Safety Overview
1 Introduction...................................................................................................................................................................101
2 S32K1xx safety concept............................................................................................................................................... 102
2.1 Cortex-M4/M0  Structural Core Self Test (SCST).......................................................................................103
2.2 ECC on RAM and flash memory...................................................................................................................104
2.3 Power supply monitoring............................................................................................................................... 104
2.4 Clock monitoring........................................................................................................................................... 105
2.5 Temporal protection.......................................................................................................................................105
2.6 Operational interference protection............................................................................................................... 105
2.7 CRC................................................................................................................................................................107
2.8 Diversity of system resources........................................................................................................................ 107
Chapter 7
CM4 Overview
1 Arm Cortex-M4F core configuration............................................................................................................................109
1.1 Buses, interconnects, and interfaces.............................................................................................................. 110
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1.2 System Tick Timer.........................................................................................................................................110
1.3 Debug facilities.............................................................................................................................................. 110
1.4 Caches............................................................................................................................................................ 111
1.5 Core privilege levels...................................................................................................................................... 111
2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 112
2.1 Interrupt priority levels.................................................................................................................................. 112
2.2 Non-maskable interrupt..................................................................................................................................113
2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 113
3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................114
3.1 Wake-up sources............................................................................................................................................ 114
4 FPU configuration.........................................................................................................................................................115
5 JTAG controller configuration......................................................................................................................................116
Chapter 8
CM0  Overview
1 Arm Cortex-M0  core introduction..............................................................................................................................117
1.1 Buses, interconnects, and interfaces.............................................................................................................. 118
1.2 System tick timer........................................................................................................................................... 118
1.3 Debug facilities.............................................................................................................................................. 118
1.4 Core privilege levels...................................................................................................................................... 118
2 Nested vectored interrupt controller (NVIC) ...............................................................................................................119
2.1 Interrupt priority levels.................................................................................................................................. 119
2.2 Non-maskable interrupt..................................................................................................................................119
2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 119
3 AWIC introduction....................................................................................................................................................... 120
3.1 Wake-up sources............................................................................................................................................ 120
Chapter 9
Micro Trace Buffer (MTB)
1 Introduction...................................................................................................................................................................123
1.1 Overview........................................................................................................................................................123
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1.2 Features.......................................................................................................................................................... 125
1.3 Modes of operation........................................................................................................................................ 126
2 Memory map and register definition.............................................................................................................................126
2.1 MTB_DWT Memory Map.............................................................................................................................127
Chapter 10
Miscellaneous Control Module (MCM)
1 Chip-specific MCM information.................................................................................................................................. 137
2 Introduction...................................................................................................................................................................138
2.1 Features.......................................................................................................................................................... 138
3 Memory map/register descriptions............................................................................................................................... 138
3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................139
3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 140
3.3 Core Platform Control Register (MCM_CPCR)............................................................................................141
3.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 144
3.5 Process ID Register (MCM_PID).................................................................................................................. 147
3.6 Compute Operation Control Register (MCM_CPO)..................................................................................... 148
3.7 Local Memory Descriptor Register (MCM_LMDRn)...................................................................................149
3.8 Local Memory Descriptor Register2 (MCM_LMDR2).................................................................................152
3.9 LMEM Parity and ECC Control Register (MCM_LMPECR).......................................................................156
3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)...................................................................... 157
3.11 LMEM Fault Address Register (MCM_LMFAR).........................................................................................158
3.12 LMEM Fault Attribute Register (MCM_LMFATR)..................................................................................... 159
3.13 LMEM Fault Data High Register (MCM_LMFDHR).................................................................................. 160
3.14 LMEM Fault Data Low Register (MCM_LMFDLR)....................................................................................160
4 Functional description...................................................................................................................................................161
4.1 Interrupts........................................................................................................................................................ 161
Chapter 11
System Integration Module (SIM)
1 Chip-specific SIM information.....................................................................................................................................163
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1.1 SIM register bitfield implementation.............................................................................................................163
2 Introduction...................................................................................................................................................................163
2.1 Features.......................................................................................................................................................... 163
3 Memory map and register definition.............................................................................................................................164
3.1 SIM register descriptions............................................................................................................................... 164
Chapter 12
Port Control and Interrupts (PORT)
1 Chip-specific PORT information..................................................................................................................................191
1.1 Number of PCRs............................................................................................................................................ 191
1.2 Finding address for PORTx_PCRn ...............................................................................................................192
1.3 I/O configuration sequence ........................................................................................................................... 192
1.4 Digital input filter configuration sequence ................................................................................................... 193
2 Introduction...................................................................................................................................................................194
3 Overview.......................................................................................................................................................................194
3.1 Features.......................................................................................................................................................... 194
3.2 Modes of operation........................................................................................................................................ 195
4 External signal description............................................................................................................................................195
5 Detailed signal description............................................................................................................................................196
6 Memory map and register definition.............................................................................................................................196
6.1 Pin Control Register n (PORT_PCRn).......................................................................................................... 198
6.2 Global Pin Control Low Register (PORT_GPCLR)......................................................................................201
6.3 Global Pin Control High Register (PORT_GPCHR).....................................................................................201
6.4 Global Interrupt Control Low Register (PORT_GICLR).............................................................................. 202
6.5 Global Interrupt Control High Register (PORT_GICHR).............................................................................202
6.6 Interrupt Status Flag Register (PORT_ISFR)................................................................................................ 203
6.7 Digital Filter Enable Register (PORT_DFER).............................................................................................. 204
6.8 Digital Filter Clock Register (PORT_DFCR)................................................................................................204
6.9 Digital Filter Width Register (PORT_DFWR).............................................................................................. 205
7 Functional description...................................................................................................................................................205
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7.1 Pin control...................................................................................................................................................... 205
7.2 Global pin control.......................................................................................................................................... 206
7.3 Global interrupt control..................................................................................................................................207
7.4 External interrupts..........................................................................................................................................207
7.5 Digital filter....................................................................................................................................................208
Chapter 13
General-Purpose Input/Output (GPIO)
1 Chip-specific GPIO information...................................................................................................................................209
1.1 Instantiation information................................................................................................................................209
1.2 GPIO ports memory map............................................................................................................................... 209
1.3 GPIO register reset values .............................................................................................................................210
2 Introduction...................................................................................................................................................................210
2.1 Features.......................................................................................................................................................... 211
2.2 Modes of operation........................................................................................................................................ 211
2.3 GPIO signal descriptions............................................................................................................................... 211
3 Memory map and register definition.............................................................................................................................212
3.1 GPIO register descriptions............................................................................................................................. 212
4 Functional description...................................................................................................................................................220
4.1 General-purpose input....................................................................................................................................220
4.2 General-purpose output..................................................................................................................................220
Chapter 14
Crossbar Switch Lite (AXBS-Lite)
1 Chip-specific AXBS-Lite information..........................................................................................................................223
1.1 Crossbar Switch master assignments............................................................................................................. 223
1.2 Crossbar Switch slave assignments................................................................................................................223
2 Introduction...................................................................................................................................................................224
2.1 Features.......................................................................................................................................................... 224
3 Functional Description..................................................................................................................................................225
3.1 General operation...........................................................................................................................................225
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3.2 Arbitration......................................................................................................................................................225
4 Initialization/application information........................................................................................................................... 227
Chapter 15
Memory Protection Unit (MPU)
1 Chip-specific MPU information................................................................................................................................... 229
1.1 MPU Slave Port Assignments........................................................................................................................229
1.2 MPU Logical Bus Master Assignments.........................................................................................................230
1.3 Current PID.................................................................................................................................................... 230
1.4 Region descriptors and slave port configuration............................................................................................230
2 Introduction...................................................................................................................................................................231
3 Overview.......................................................................................................................................................................231
3.1 Block diagram................................................................................................................................................ 231
3.2 Features.......................................................................................................................................................... 232
4 MPU register descriptions.............................................................................................................................................233
4.1 MPU Memory map........................................................................................................................................ 233
4.2 Control/Error Status Register (CESR)........................................................................................................... 236
4.3 Error Address Register, slave port n (EAR0 - EAR4)................................................................................... 238
4.4 Error Detail Register, slave port n (EDR0 - EDR4)...................................................................................... 239
4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WORD0)...........................................................241
4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)...........................................................................................242
4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)...........................................................................................243
4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)...........................................................................................246
4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)...........................................................247
4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)...........................................................248
4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)...........................................................251
4.12 Region Descriptor Alternate Access Control 0 (RGDAAC0)....................................................................... 253
4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)............................................... 256
5 Functional description...................................................................................................................................................259
5.1 Access evaluation macro................................................................................................................................259
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5.2 Putting it all together and error terminations................................................................................................. 261
5.3 Power management........................................................................................................................................ 261
6 Initialization information.............................................................................................................................................. 262
7 Application information................................................................................................................................................262
Chapter 16
Peripheral Bridge (AIPS-Lite)
1 Chip-specific AIPS information................................................................................................................................... 265
1.1 Instantiation information................................................................................................................................265
1.2 Memory maps................................................................................................................................................ 265
2 Introduction...................................................................................................................................................................266
2.1 Features.......................................................................................................................................................... 267
2.2 General operation...........................................................................................................................................267
3 Memory map/register definition................................................................................................................................... 267
3.1 AIPS register descriptions..............................................................................................................................267
4 Functional description...................................................................................................................................................311
4.1 Access support............................................................................................................................................... 311
Chapter 17
Direct Memory Access Multiplexer (DMAMUX)
1 Chip-specific DMAMUX information......................................................................................................................... 313
1.1 Number of channels ...................................................................................................................................... 313
1.2 DMA transfers via TRGMUX trigger............................................................................................................313
2 Introduction...................................................................................................................................................................314
2.1 Overview........................................................................................................................................................314
2.2 Features.......................................................................................................................................................... 314
2.3 Modes of operation........................................................................................................................................ 315
3 Memory map/register definition................................................................................................................................... 315
3.1 DMAMUX register descriptions....................................................................................................................315
4 Functional description...................................................................................................................................................317
4.1 DMA channels with periodic triggering capability........................................................................................317
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4.2 DMA channels with no triggering capability.................................................................................................320
4.3 Always-enabled DMA sources...................................................................................................................... 320
5 Initialization/application information........................................................................................................................... 321
5.1 Reset...............................................................................................................................................................321
5.2 Enabling and configuring sources..................................................................................................................321
Chapter 18
Enhanced Direct Memory Access (eDMA)
1 Chip-specific eDMA information ................................................................................................................................325
1.1 Seamless eDMA transfer .............................................................................................................................. 325
1.2 Number of channels ...................................................................................................................................... 326
2 Introduction...................................................................................................................................................................326
2.1 eDMA system block diagram........................................................................................................................ 326
2.2 Block parts..................................................................................................................................................... 327
2.3 Features.......................................................................................................................................................... 328
3 Modes of operation....................................................................................................................................................... 329
4 Memory map/register definition................................................................................................................................... 330
4.1 TCD memory................................................................................................................................................. 330
4.2 TCD initialization.......................................................................................................................................... 330
4.3 TCD structure.................................................................................................................................................330
4.4 Reserved memory and bit fields.....................................................................................................................331
4.5 DMA register descriptions............................................................................................................................. 331
5 Functional description...................................................................................................................................................380
5.1 eDMA basic data flow................................................................................................................................... 380
5.2 Fault reporting and handling.......................................................................................................................... 383
5.3 Channel preemption....................................................................................................................................... 386
6 Initialization/application information........................................................................................................................... 386
6.1 eDMA initialization....................................................................................................................................... 386
6.2 Programming errors....................................................................................................................................... 388
6.3 Arbitration mode considerations....................................................................................................................389
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6.4 Performing DMA transfers............................................................................................................................ 389
6.5 Monitoring transfer descriptor status............................................................................................................. 393
6.6 Channel Linking.............................................................................................................................................395
6.7 Dynamic programming.................................................................................................................................. 396
6.8 Suspend/resume a DMA channel with active hardware service requests......................................................400
Chapter 19
Trigger MUX Control (TRGMUX)
1 Chip-specific TRGMUX information...........................................................................................................................403
1.1 Module interconnectivity............................................................................................................................... 403
1.2 TRGMUX register information..................................................................................................................... 407
2 Introduction...................................................................................................................................................................407
3 Features.........................................................................................................................................................................407
4 Memory map and register definition.............................................................................................................................408
4.1 TRGMUX register descriptions..................................................................................................................... 408
Chapter 20
External Watchdog Monitor (EWM)
1 Chip-specific EWM information ................................................................................................................................. 447
1.1 EWM_OUT signal configuration...................................................................................................................447
1.2 EWM Memory Map access............................................................................................................................447
1.3 EWM low-power modes................................................................................................................................ 447
2 Introduction...................................................................................................................................................................447
2.1 Features.......................................................................................................................................................... 448
2.2 Modes of Operation....................................................................................................................................... 448
2.3 Block Diagram............................................................................................................................................... 449
3 EWM Signal Descriptions............................................................................................................................................ 450
4 Memory Map/Register Definition.................................................................................................................................451
4.1 EWM register descriptions.............................................................................................................................451
5 Functional Description..................................................................................................................................................456
5.1 The EWM_OUT_b Signal............................................................................................................................. 456
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5.2 EWM_OUT_b pin state in low power modes................................................................................................457
5.3 The EWM_in Signal...................................................................................................................................... 457
5.4 EWM Counter................................................................................................................................................ 458
5.5 EWM Compare Registers.............................................................................................................................. 458
5.6 EWM Refresh Mechanism.............................................................................................................................458
5.7 EWM Interrupt...............................................................................................................................................459
5.8 Counter clock prescaler..................................................................................................................................459
Chapter 21
Error Injection Module (EIM)
1 Chip-specific EIM information.....................................................................................................................................461
1.1 EIM channel assignments.............................................................................................................................. 461
2 Introduction...................................................................................................................................................................461
2.1 Overview........................................................................................................................................................461
2.2 Features.......................................................................................................................................................... 463
3 EIM register descriptions..............................................................................................................................................463
3.1 EIM Memory map..........................................................................................................................................464
3.2 Error Injection Module Configuration Register (EIMCR)............................................................................ 464
3.3 Error Injection Channel Enable register (EICHEN)...................................................................................... 465
3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)............................468
3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)............................470
4 Functional description...................................................................................................................................................471
4.1 Error injection scenarios................................................................................................................................ 471
Chapter 22
Error Reporting Module (ERM)
1 Chip-specific ERM information................................................................................................................................... 473
1.1 Sources of memory error events.................................................................................................................... 473
2 Introduction...................................................................................................................................................................473
2.1 Overview........................................................................................................................................................473
2.2 Features.......................................................................................................................................................... 474
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3 ERM register descriptions.............................................................................................................................................474
3.1 ERM Memory map........................................................................................................................................ 474
3.2 ERM Configuration Register 0 (CR0)........................................................................................................... 475
3.3 ERM Status Register 0 (SR0)........................................................................................................................ 477
3.4 ERM Memory n Error Address Register (EAR0 - EAR1)............................................................................ 479
4 Functional description...................................................................................................................................................480
4.1 Single-bit correction events........................................................................................................................... 480
4.2 Non-correctable error events..........................................................................................................................481
5 Initialization.................................................................................................................................................................. 482
Chapter 23
Watchdog timer (WDOG)
1 Chip-specific WDOG information................................................................................................................................483
1.1 WDOG clocks................................................................................................................................................ 483
1.2 WDOG low-power modes............................................................................................................................. 483
1.3 Default watchdog timeout .............................................................................................................................484
2 Introduction...................................................................................................................................................................484
2.1 Features.......................................................................................................................................................... 484
2.2 Block diagram................................................................................................................................................ 485
3 Memory map and register definition.............................................................................................................................486
3.1 WDOG register descriptions..........................................................................................................................486
4 Functional description...................................................................................................................................................492
4.1 Clock source...................................................................................................................................................492
4.2 Watchdog refresh mechanism........................................................................................................................493
4.3 Configuring the Watchdog.............................................................................................................................495
4.4 Using interrupts to delay resets......................................................................................................................496
4.5 Backup reset...................................................................................................................................................496
4.6 Functionality in debug and low-power modes...............................................................................................497
4.7 Fast testing of the watchdog...........................................................................................................................497
5 Application Information................................................................................................................................................499
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5.1 Disable Watchdog.......................................................................................................................................... 499
5.2 Disable Watchdog after Reset........................................................................................................................499
5.3 Configure Watchdog...................................................................................................................................... 500
5.4 Refreshing the Watchdog...............................................................................................................................500
Chapter 24
Cyclic Redundancy Check (CRC)
1 Chip-specific CRC information.................................................................................................................................... 501
2 Introduction...................................................................................................................................................................501
2.1 Features.......................................................................................................................................................... 501
2.2 Block diagram................................................................................................................................................ 502
2.3 Modes of operation........................................................................................................................................ 502
3 Memory map and register descriptions.........................................................................................................................502
3.1 CRC register descriptions.............................................................................................................................. 502
4 Functional description...................................................................................................................................................507
4.1 CRC initialization/reinitialization.................................................................................................................. 507
4.2 CRC calculations............................................................................................................................................507
4.3 Transpose feature........................................................................................................................................... 508
4.4 CRC result complement................................................................................................................................. 510
Chapter 25
Reset and Boot
1 Introduction...................................................................................................................................................................511
2 Reset..............................................................................................................................................................................511
2.1 Power-on reset (POR).................................................................................................................................... 512
2.2 System reset sources...................................................................................................................................... 512
2.3 MCU Resets................................................................................................................................................... 516
2.4 Reset pin ........................................................................................................................................................516
2.5 Debug resets...................................................................................................................................................517
3 Boot...............................................................................................................................................................................518
3.1 Boot sources...................................................................................................................................................518
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3.2 FOPT boot options......................................................................................................................................... 518
3.3 Boot sequence................................................................................................................................................ 519
Chapter 26
Reset Control Module (RCM)
1 Chip-specific RCM information................................................................................................................................... 521
1.1 RCM register information .............................................................................................................................521
2 Reset pin filter operation in STOP1/2 modes .............................................................................................................. 522
3 Introduction...................................................................................................................................................................522
4 Reset memory map and register descriptions............................................................................................................... 522
4.1 Version ID Register (RCM_VERID).............................................................................................................523
4.2 Parameter Register (RCM_PARAM)............................................................................................................ 524
4.3 System Reset Status Register (RCM_SRS)................................................................................................... 526
4.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 529
4.5 Sticky System Reset Status Register (RCM_SSRS)......................................................................................531
4.6 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 533
Chapter 27
Clock Distribution
1 Introduction...................................................................................................................................................................537
2 High level clocking diagram.........................................................................................................................................537
3 Clock definitions...........................................................................................................................................................538
4 Internal clocking requirements..................................................................................................................................... 540
4.1 Clock divider values after reset......................................................................................................................544
4.2 HSRUN mode clocking................................................................................................................................. 544
4.3 VLPR mode clocking.....................................................................................................................................544
4.4 VLPR/VLPS mode entry............................................................................................................................... 544
5 Clock Gating................................................................................................................................................................. 545
6 Module clocks...............................................................................................................................................................545
Chapter 28
System Clock Generator (SCG)
1 Chip-specific SCG information.................................................................................................................................... 557
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1.1 Supported frequency ranges...........................................................................................................................557
1.2 Oscillator and SPLL guidelines..................................................................................................................... 557
1.3 System clock switching .................................................................................................................................558
1.4 System clock and clock monitor requirement ...............................................................................................558
2 Introduction...................................................................................................................................................................559
2.1 Features.......................................................................................................................................................... 559
3 Memory Map/Register Definition.................................................................................................................................560
3.1 Version ID Register (SCG_VERID)..............................................................................................................561
3.2 Parameter Register (SCG_PARAM)............................................................................................................. 562
3.3 Clock Status Register (SCG_CSR)................................................................................................................ 563
3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................565
3.5 VLPR Clock Control Register (SCG_VCCR)............................................................................................... 567
3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................569
3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................571
3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................573
3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 575
3.10 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 576
3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................578
3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 579
3.13 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................580
3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 581
3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................583
3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 584
3.17 System PLL Control Status Register (SCG_SPLLCSR)............................................................................... 585
3.18 System PLL Divide Register (SCG_SPLLDIV)............................................................................................587
3.19 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 588
4 Functional description...................................................................................................................................................590
4.1 SCG Clock Mode Transitions........................................................................................................................ 590
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Peripheral Clock Controller (PCC)
1 Chip-specific PCC information.....................................................................................................................................593
1.1 PCC register information............................................................................................................................... 593
2 Introduction...................................................................................................................................................................596
3 Features.........................................................................................................................................................................596
4 Functional description...................................................................................................................................................597
5 Memory map and register definition.............................................................................................................................598
6 PCC register descriptions..............................................................................................................................................598
6.1 PCC Memory map......................................................................................................................................... 598
6.2 PCC FTFC Register (PCC_FTFC)................................................................................................................ 599
6.3 PCC DMAMUX Register (PCC_DMAMUX).............................................................................................. 601
6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)................................................................................................ 602
6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)................................................................................................ 604
6.6 PCC FTM3 Register (PCC_FTM3)............................................................................................................... 605
6.7 PCC ADC1 Register (PCC_ADC1)...............................................................................................................607
6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)................................................................................................ 608
6.9 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................610
6.10 PCC LPSPI1 Register (PCC_LPSPI1)...........................................................................................................612
6.11 PCC LPSPI2 Register (PCC_LPSPI2)...........................................................................................................613
6.12 PCC PDB1 Register (PCC_PDB1)................................................................................................................ 615
6.13 PCC CRC Register (PCC_CRC)....................................................................................................................617
6.14 PCC PDB0 Register (PCC_PDB0)................................................................................................................ 618
6.15 PCC LPIT Register (PCC_LPIT)...................................................................................................................620
6.16 PCC FTM0 Register (PCC_FTM0)............................................................................................................... 621
6.17 PCC FTM1 Register (PCC_FTM1)............................................................................................................... 623
6.18 PCC FTM2 Register (PCC_FTM2)............................................................................................................... 624
6.19 PCC ADC0 Register (PCC_ADC0)...............................................................................................................626
6.20 PCC RTC Register (PCC_RTC).................................................................................................................... 628
6.21 PCC LPTMR0 Register (PCC_LPTMR0).....................................................................................................629
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6.22 PCC PORTA Register (PCC_PORTA)......................................................................................................... 631
6.23 PCC PORTB Register (PCC_PORTB)..........................................................................................................633
6.24 PCC PORTC Register (PCC_PORTC)..........................................................................................................634
6.25 PCC PORTD Register (PCC_PORTD)......................................................................................................... 636
6.26 PCC PORTE Register (PCC_PORTE).......................................................................................................... 637
6.27 PCC SAI0 Register (PCC_SAI0)...................................................................................................................639
6.28 PCC SAI1 Register (PCC_SAI1)...................................................................................................................640
6.29 PCC FlexIO Register (PCC_FlexIO).............................................................................................................642
6.30 PCC EWM Register (PCC_EWM)................................................................................................................ 643
6.31 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 645
6.32 PCC LPI2C1 Register (PCC_LPI2C1).......................................................................................................... 646
6.33 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 648
6.34 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 649
6.35 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 651
6.36 PCC FTM4 Register (PCC_FTM4)............................................................................................................... 653
6.37 PCC FTM5 Register (PCC_FTM5)............................................................................................................... 654
6.38 PCC FTM6 Register (PCC_FTM6)............................................................................................................... 656
6.39 PCC FTM7 Register (PCC_FTM7)............................................................................................................... 658
6.40 PCC CMP0 Register (PCC_CMP0)...............................................................................................................659
6.41 PCC QSPI Register (PCC_QSPI).................................................................................................................. 661
6.42 PCC ENET Register (PCC_ENET)............................................................................................................... 663
Chapter 30
Clock Monitoring Unit (CMU)
1 CMU chip-specific information....................................................................................................................................665
2 Introduction...................................................................................................................................................................666
2.1 Basic operation...............................................................................................................................................667
2.2 Features.......................................................................................................................................................... 668
3 CMU_FC register descriptions..................................................................................................................................... 668
3.1 CMU_FC Memory map................................................................................................................................. 668
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3.2 Global Configuration Register (GCR)........................................................................................................... 669
3.3 Reference Count Configuration Register (RCCR).........................................................................................670
3.4 High Threshold Configuration Register (HTCR).......................................................................................... 671
3.5 Low Threshold Configuration Register (LTCR)........................................................................................... 672
3.6 Status Register (SR)....................................................................................................................................... 673
3.7 Interrupt Enable Register (IER)..................................................................................................................... 674
4 Functional description...................................................................................................................................................677
4.1 Monitored clock lost...................................................................................................................................... 677
5 Programming guidelines............................................................................................................................................... 677
5.1 Programming HFREF and LFREF................................................................................................................ 677
5.2 Programming RCCR[REF_CNT].................................................................................................................. 678
5.3 CMU_FC programming sequence................................................................................................................. 679
Chapter 31
Memories and Memory Interfaces
1 Introduction...................................................................................................................................................................681
2 Flash Memory Controller and flash memory modules................................................................................................. 681
3 SRAM configuration.....................................................................................................................................................682
3.1 SRAM sizes....................................................................................................................................................682
3.2 SRAM accessibility........................................................................................................................................683
3.3 SRAM arbitration and priority control...........................................................................................................684
3.4 SRAM retention: power modes and resets.....................................................................................................684
3.5 SRAM access: Behavior of device when in accessing a memory with multi-bit ECC error.........................685
Chapter 32
PRAM Controller (PRAMC)
1 PRAMC chip-specific information ..............................................................................................................................687
2 Introduction...................................................................................................................................................................687
3 Memory map and register definition.............................................................................................................................688
4 Functional description...................................................................................................................................................688
4.1 Error Correcting Code (ECC)........................................................................................................................ 688
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4.2 Read/Write introduction.................................................................................................................................689
4.3 Reads..............................................................................................................................................................689
4.4 Writes............................................................................................................................................................. 690
4.5 Late write hits.................................................................................................................................................691
5 Initialization / application information......................................................................................................................... 692
Chapter 33
Local Memory Controller (LMEM)
1 Chip-specific LMEM information ............................................................................................................................... 693
1.1 LMEM region description..............................................................................................................................693
1.2 LMEM SRAM sizes.......................................................................................................................................693
2 Introduction...................................................................................................................................................................693
2.1 Block Diagram............................................................................................................................................... 694
2.2 Cache features................................................................................................................................................ 695
3 Memory Map/Register Definition.................................................................................................................................697
3.1 LMEM register descriptions.......................................................................................................................... 697
4 Functional Description..................................................................................................................................................706
4.1 LMEM Function............................................................................................................................................ 706
4.2 SRAM Function............................................................................................................................................. 707
4.3 Cache Function.............................................................................................................................................. 709
4.4 Cache Control................................................................................................................................................ 710
Chapter 34
Miscellaneous System Control Module (MSCM)
1 Chip-specific MSCM information................................................................................................................................ 715
1.1 Chip-specific TMLSZ/TMUSZ information................................................................................................. 715
1.2 Chip-specific register information................................................................................................................. 715
2 Overview.......................................................................................................................................................................716
3 Chip Configuration and Boot........................................................................................................................................716
4 MSCM Memory Map/Register Definition....................................................................................................................717
4.1 CPU Configuration Memory Map and Registers...........................................................................................717
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4.2 MSCM register descriptions.......................................................................................................................... 717
Chapter 35
Flash Memory Controller (FMC)
1 Chip-specific FMC information....................................................................................................................................749
1.1 FMC masters.................................................................................................................................................. 749
1.2 Program flash and Data flash port width....................................................................................................... 750
2 Introduction...................................................................................................................................................................750
2.1 Overview........................................................................................................................................................750
2.2 Features.......................................................................................................................................................... 750
3 Modes of operation....................................................................................................................................................... 751
4 External signal description............................................................................................................................................751
5 Functional description...................................................................................................................................................751
5.1 Default configuration..................................................................................................................................... 751
5.2 Speculative reads............................................................................................................................................752
6 Initialization and application information.....................................................................................................................753
Chapter 36
Flash Memory Module (FTFC)
1 Chip-specific FTFC information...................................................................................................................................755
1.1 Flash memory types....................................................................................................................................... 755
1.2 Flash memory sizes........................................................................................................................................756
1.3 Flash memory map.........................................................................................................................................775
1.4 Flash memory security................................................................................................................................... 776
1.5 Power mode restrictions on flash memory programming..............................................................................776
1.6 Flash memory modes..................................................................................................................................... 776
1.7 Erase all contents of flash memory................................................................................................................ 776
1.8 Customize MCU operations via FTFC_FOPT register..................................................................................777
1.9 Simultaneous operations on PFLASH read partitions .................................................................................. 777
2 Introduction...................................................................................................................................................................777
2.1 Features.......................................................................................................................................................... 778
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2.2 Block diagram................................................................................................................................................ 780
2.3 Glossary......................................................................................................................................................... 781
3 External signal description............................................................................................................................................783
4 Memory map and registers............................................................................................................................................784
4.1 Flash configuration field description............................................................................................................. 784
4.2 Program flash 0 IFR map............................................................................................................................... 784
4.3 Data flash 0 IFR map..................................................................................................................................... 785
4.4 Register descriptions...................................................................................................................................... 786
5 Functional description...................................................................................................................................................804
5.1 Flash protection..............................................................................................................................................804
5.2 FlexNVM description.................................................................................................................................... 806
5.3 Interrupts........................................................................................................................................................ 809
5.4 Flash operation in low-power modes............................................................................................................. 810
5.5 Functional modes of operation.......................................................................................................................810
5.6 Flash memory reads and ignored writes........................................................................................................ 810
5.7 Read while write (RWW).............................................................................................................................. 811
5.8 Flash program and erase................................................................................................................................ 811
5.9 FTFC command operations............................................................................................................................811
5.10 Margin read commands..................................................................................................................................818
5.11 Flash command descriptions..........................................................................................................................819
5.12 Security.......................................................................................................................................................... 845
5.13 Cryptographic Services Engine (CSEc).........................................................................................................847
5.14 Reset sequence............................................................................................................................................... 885
Chapter 37
Quad Serial Peripheral Interface (QuadSPI)
1 Chip-specific QuadSPI information..............................................................................................................................887
1.1 Overview........................................................................................................................................................887
1.2 Memory size requirement ............................................................................................................................. 887
1.3 QuadSPI register reset values........................................................................................................................ 887
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1.4 Use case..........................................................................................................................................................888
1.5 Supported read modes....................................................................................................................................888
1.6 External memory options............................................................................................................................... 889
1.7 Recommended software configuration.......................................................................................................... 889
1.8 Recommended programming sequence......................................................................................................... 890
1.9 Clock ratio between QuadSPI clocks ............................................................................................................890
1.10 QuadSPI_MCR[SCLKCFG] implementation ...............................................................................................890
1.11 QuadSPI_SOCCR[SOCCFG] implementation .............................................................................................891
2 Introduction...................................................................................................................................................................893
2.1 Features.......................................................................................................................................................... 893
2.2 Block Diagram............................................................................................................................................... 894
2.3 QuadSPI Modes of Operation........................................................................................................................ 895
2.4 Acronyms and Abbreviations.........................................................................................................................896
2.5 Glossary for QuadSPI module....................................................................................................................... 896
3 External Signal Description.......................................................................................................................................... 898
3.1 Driving External Signals................................................................................................................................899
4 Memory Map and Register Definition..........................................................................................................................901
4.1 Register Write Access....................................................................................................................................901
4.2 Peripheral Bus Register Descriptions............................................................................................................ 902
4.3 Serial Flash Address Assignment.................................................................................................................. 945
5 Flash memory mapped AMBA bus.............................................................................................................................. 946
5.1 AHB Bus Access Considerations...................................................................................................................947
5.2 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A.....................................................947
5.3 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B..................................................... 948
5.4 AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31).......................................................................... 949
6 Interrupt Signals............................................................................................................................................................951
7 Functional Description..................................................................................................................................................952
7.1 Serial Flash Access Schemes......................................................................................................................... 952
7.2 Normal Mode................................................................................................................................................. 952
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7.3 HyperRAM Support.......................................................................................................................................971
8 Initialization/Application Information..........................................................................................................................972
8.1 Power Up and Reset.......................................................................................................................................972
8.2 Available Status/Flag Information................................................................................................................. 972
8.3 Flash Device Selection...................................................................................................................................975
8.4 DMA Usage................................................................................................................................................... 975
9 Byte Ordering - Endianness..........................................................................................................................................979
9.1 Programming Flash Data............................................................................................................................... 980
9.2 Reading Flash Data into the RX Buffer......................................................................................................... 980
9.3 Reading Flash Data into the AHB Buffer...................................................................................................... 981
10 Driving Flash Control Signals in Single and Dual Mode............................................................................................. 982
11 Serial Flash Devices......................................................................................................................................................982
11.1 Example Sequences........................................................................................................................................982
12 Sampling of Serial Flash Input Data.............................................................................................................................988
12.1 Basic Description........................................................................................................................................... 988
12.2 Supported read modes....................................................................................................................................989
12.3 Data Strobe (DQS) sampling method............................................................................................................ 992
13 Data Input Hold Requirement of Flash.........................................................................................................................995
Chapter 38
Power Management
1 Introduction...................................................................................................................................................................997
2 Power modes description.............................................................................................................................................. 997
3 Entering and exiting power modes............................................................................................................................... 999
4 Clocking modes............................................................................................................................................................ 999
4.1 Clock gating................................................................................................................................................... 999
4.2 Stop mode options..........................................................................................................................................999
4.3 DMA wake-up................................................................................................................................................1000
4.4 Compute Operation (CPO).............................................................................................................................1001
4.5 Peripheral Doze..............................................................................................................................................1002
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5 Power mode transitions.................................................................................................................................................1003
6 Shutdown sequencing for power modes....................................................................................................................... 1004
7 Power mode restrictions on flash memory programming.............................................................................................1004
8 Module operation in available power modes................................................................................................................1005
9 QuadSPI, Ethernet, and SAI operation ........................................................................................................................ 1009
Chapter 39
System Mode Controller (SMC)
1 Introduction...................................................................................................................................................................1011
2 Modes of operation....................................................................................................................................................... 1011
3 Memory map and register descriptions.........................................................................................................................1013
3.1 SMC Version ID Register (SMC_VERID)....................................................................................................1014
3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 1015
3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................1016
3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................1017
3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................1019
3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 1021
4 Functional description...................................................................................................................................................1021
4.1 Power mode transitions..................................................................................................................................1022
4.2 Power mode entry/exit sequencing................................................................................................................ 1023
4.3 Run modes......................................................................................................................................................1026
4.4 Stop modes.....................................................................................................................................................1028
4.5 Debug in low power modes........................................................................................................................... 1029
Chapter 40
Power Management Controller (PMC)
1 Chip-specific PMC information....................................................................................................................................1031
1.1 Modes supported............................................................................................................................................ 1031
2 Introduction...................................................................................................................................................................1031
3 Features.........................................................................................................................................................................1031
4 Modes of Operation...................................................................................................................................................... 1032
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4.1 Full Performance Mode (FPM)......................................................................................................................1032
4.2 Low Power Mode (LPM)...............................................................................................................................1032
5 Low Voltage Detect (LVD) System............................................................................................................................. 1032
5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 1033
5.2 LVD Interrupt Operation............................................................................................................................... 1033
5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 1033
6 Memory Map and Register Definition..........................................................................................................................1033
6.1 PMC register descriptions..............................................................................................................................1033
Chapter 41
ADC Configuration
1 Instantiation information...............................................................................................................................................1041
1.1 Number of ADC channels..............................................................................................................................1041
1.2 ADC Connections/Channel Assignment........................................................................................................1042
2 Register implementation............................................................................................................................................... 1043
3 DMA Support on ADC................................................................................................................................................. 1043
4 ADC Hardware Interleaved Channels.......................................................................................................................... 1044
5 ADC internal supply monitoring.................................................................................................................................. 1045
6 ADC Reference Options............................................................................................................................................... 1045
7 ADC Trigger Sources................................................................................................................................................... 1045
7.1 PDB triggering scheme.................................................................................................................................. 1047
7.2 TRGMUX trigger scheme..............................................................................................................................1048
8 Trigger Selection...........................................................................................................................................................1049
9 Trigger Latching and Arbitration..................................................................................................................................1050
10 ADC triggering configurations .................................................................................................................................... 1052
11 ADC low-power modes................................................................................................................................................ 1059
12 ADC Trigger Concept – Use Case................................................................................................................................1059
13 ADC calibration scheme...............................................................................................................................................1061
14 S32K11X to S32K14X difference ............................................................................................................................... 1062
Chapter 42
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Analog-to-Digital Converter (ADC)
1 Chip-specific ADC information....................................................................................................................................1063
2 Introduction...................................................................................................................................................................1063
2.1 Features.......................................................................................................................................................... 1063
2.2 Block diagram................................................................................................................................................ 1064
3 ADC signal descriptions............................................................................................................................................... 1065
3.1 Analog Power (VDDA)................................................................................................................................. 1065
3.2 Analog Ground (VSSA).................................................................................................................................1065
3.3 Voltage Reference Select............................................................................................................................... 1065
3.4 Analog Channel Inputs (ADx)....................................................................................................................... 1066
4 ADC register descriptions.............................................................................................................................................1066
4.1 ADC Memory map.........................................................................................................................................1066
4.2 ADC Status and Control Register 1 (SC1A - aSC1P)................................................................................... 1068
4.3 ADC Configuration Register 1 (CFG1)......................................................................................................... 1071
4.4 ADC Configuration Register 2 (CFG2)......................................................................................................... 1073
4.5 ADC Data Result Registers (RA - aRP)........................................................................................................ 1074
4.6 Compare Value Registers (CV1 - CV2)........................................................................................................ 1076
4.7 Status and Control Register 2 (SC2).............................................................................................................. 1077
4.8 Status and Control Register 3 (SC3).............................................................................................................. 1080
4.9 BASE Offset Register (BASE_OFS).............................................................................................................1081
4.10 ADC Offset Correction Register (OFS).........................................................................................................1082
4.11 USER Offset Correction Register (USR_OFS)............................................................................................. 1083
4.12 ADC X Offset Correction Register (XOFS).................................................................................................. 1084
4.13 ADC Y Offset Correction Register (YOFS).................................................................................................. 1085
4.14 ADC Gain Register (G)..................................................................................................................................1086
4.15 ADC User Gain Register (UG)...................................................................................................................... 1088
4.16 ADC General Calibration Value Register S (CLPS)..................................................................................... 1089
4.17 ADC Plus-Side General Calibration Value Register 3 (CLP3)..................................................................... 1090
4.18 ADC Plus-Side General Calibration Value Register 2 (CLP2)..................................................................... 1091
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4.19 ADC Plus-Side General Calibration Value Register 1 (CLP1)..................................................................... 1091
4.20 ADC Plus-Side General Calibration Value Register 0 (CLP0)..................................................................... 1092
4.21 ADC Plus-Side General Calibration Value Register X (CLPX)....................................................................1093
4.22 ADC Plus-Side General Calibration Value Register 9 (CLP9)..................................................................... 1094
4.23 ADC General Calibration Offset Value Register S (CLPS_OFS).................................................................1095
4.24 ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS)................................................. 1096
4.25 ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS)................................................. 1097
4.26 ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS)................................................. 1098
4.27 ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS)................................................. 1099
4.28 ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)............................................... 1100
4.29 ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS)................................................. 1101
4.30 ADC Status and Control Register 1 (SC1AA - SC1Z).................................................................................. 1102
4.31 ADC Data Result Registers (RAA - RZ)....................................................................................................... 1105
5 Functional description...................................................................................................................................................1107
5.1 Clock select and divide control......................................................................................................................1107
5.2 Voltage reference selection............................................................................................................................1108
5.3 Hardware trigger and channel selects............................................................................................................ 1108
5.4 Conversion control.........................................................................................................................................1109
5.5 Automatic compare function..........................................................................................................................1113
5.6 Calibration function....................................................................................................................................... 1114
5.7 User-defined offset function.......................................................................................................................... 1115
5.8 MCU Normal Stop mode operation............................................................................................................... 1116
Chapter 43
Comparator (CMP)
1 Chip-specific CMP information....................................................................................................................................1117
1.1 Instantiation information................................................................................................................................1117
1.2 CMP input connections..................................................................................................................................1117
1.3 CMP external references................................................................................................................................1119
1.4 External window/sample input.......................................................................................................................1119
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1.5 CMP trigger mode..........................................................................................................................................1119
1.6 Programming recommendation......................................................................................................................1120
1.7 S32K11X to S32K14X difference ................................................................................................................ 1120
2 Introduction...................................................................................................................................................................1121
3 Features.........................................................................................................................................................................1121
3.1 CMP features..................................................................................................................................................1121
3.2 8-bit DAC key features.................................................................................................................................. 1122
3.3 ANMUX key features.................................................................................................................................... 1122
4 CMP, DAC, and ANMUX diagram..............................................................................................................................1123
5 CMP block diagram...................................................................................................................................................... 1124
6 CMP pin descriptions....................................................................................................................................................1126
6.1 External pins.................................................................................................................................................. 1126
7 CMP functional modes................................................................................................................................................. 1127
7.1 Disabled mode (# 1).......................................................................................................................................1128
7.2 Continuous mode (#s 2A & 2B).................................................................................................................... 1129
7.3 Sampled, Non-Filtered mode (#s 3A & 3B).................................................................................................. 1129
7.4 Sampled, Filtered mode (#s 4A & 4B).......................................................................................................... 1131
7.5 Windowed mode (#s 5A & 5B)..................................................................................................................... 1133
7.6 Windowed/Resampled mode (# 6).................................................................................................................1135
7.7 Windowed/Filtered mode (#7)....................................................................................................................... 1136
8 Memory map/register definitions..................................................................................................................................1137
8.1 CMP Control Register 0 (CMP_C0)..............................................................................................................1137
8.2 CMP Control Register 1 (CMP_C1)..............................................................................................................1141
8.3 CMP Control Register 2 (CMP_C2)..............................................................................................................1144
9 CMP functional description.......................................................................................................................................... 1146
9.1 Initialization................................................................................................................................................... 1146
9.2 Low-pass filter............................................................................................................................................... 1147
10 Interrupts.......................................................................................................................................................................1149
11 DMA support................................................................................................................................................................ 1149
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12 DAC functional description.......................................................................................................................................... 1150
12.1 Digital-to-analog converter block diagram.................................................................................................... 1150
12.2 DAC resets..................................................................................................................................................... 1150
12.3 DAC clocks.................................................................................................................................................... 1151
12.4 DAC interrupts...............................................................................................................................................1151
13 Trigger mode.................................................................................................................................................................1151
Chapter 44
Programmable delay block (PDB)
1 Chip-specific PDB information.................................................................................................................................... 1155
1.1 Instantiation Information................................................................................................................................1155
1.2 PDB trigger interconnections with ADC and TRGMUX.............................................................................. 1156
1.3 Back-to-back acknowledgement connections................................................................................................1156
1.4 Pulse-Out Enable Register Implementation...................................................................................................1163
1.5 S32K11X to S32K14X difference ................................................................................................................ 1163
2 Introduction...................................................................................................................................................................1163
2.1 Features.......................................................................................................................................................... 1163
2.2 Implementation.............................................................................................................................................. 1164
2.3 Back-to-back acknowledgment connections..................................................................................................1165
2.4 Block diagram................................................................................................................................................ 1165
2.5 Modes of operation........................................................................................................................................ 1166
3 Memory map and register definition.............................................................................................................................1167
3.1 Status and Control register (PDB_SC)...........................................................................................................1169
3.2 Modulus register (PDB_MOD)......................................................................................................................1172
3.3 Counter register (PDB_CNT)........................................................................................................................ 1173
3.4 Interrupt Delay register (PDB_IDLY)........................................................................................................... 1173
3.5 Channel n Control register 1 (PDB_CHnC1)................................................................................................ 1174
3.6 Channel n Status register (PDB_CHnS)........................................................................................................ 1175
3.7 Channel n Delay 0 register (PDB_CHnDLY0)..............................................................................................1175
3.8 Channel n Delay 1 register (PDB_CHnDLY1)..............................................................................................1176
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3.9 Channel n Delay 2 register (PDB_CHnDLY2)..............................................................................................1177
3.10 Channel n Delay 3 register (PDB_CHnDLY3)..............................................................................................1177
3.11 Channel n Delay 4 register (PDB_CHnDLY4)..............................................................................................1178
3.12 Channel n Delay 5 register (PDB_CHnDLY5)..............................................................................................1179
3.13 Channel n Delay 6 register (PDB_CHnDLY6)..............................................................................................1179
3.14 Channel n Delay 7 register (PDB_CHnDLY7)..............................................................................................1180
3.15 Pulse-Out n Enable register (PDB_POEN)....................................................................................................1180
3.16 Pulse-Out n Delay register (PDB_POnDLY)................................................................................................ 1181
4 Functional description...................................................................................................................................................1181
4.1 PDB pre-trigger and trigger outputs...............................................................................................................1181
4.2 PDB trigger input source selection................................................................................................................ 1184
4.3 Pulse-Out's..................................................................................................................................................... 1184
4.4 Updating the delay registers...........................................................................................................................1185
4.5 Interrupts........................................................................................................................................................ 1187
4.6 DMA.............................................................................................................................................................. 1187
5 Application information................................................................................................................................................1187
5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................... 1187
Chapter 45
FlexTimer Module (FTM)
1 Chip-specific FTM information....................................................................................................................................1189
1.1 Instantiation Information................................................................................................................................1189
1.2 FTM Interrupts...............................................................................................................................................1190
1.3 FTM Fault Detection Inputs...........................................................................................................................1190
1.4 FTM Hardware Triggers and Synchronization.............................................................................................. 1192
1.5 FTM Input Capture Options...........................................................................................................................1194
1.6 FTM Hall sensor support............................................................................................................................... 1195
1.7 FTM Modulation Implementation................................................................................................................. 1195
1.8 FTM Global Time Base................................................................................................................................. 1196
1.9 FTM BDM and debug halt mode...................................................................................................................1197
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1.10 S32K11X to S32K14X difference ................................................................................................................ 1197
2 Introduction...................................................................................................................................................................1199
2.1 Features.......................................................................................................................................................... 1199
2.2 Modes of operation........................................................................................................................................ 1200
2.3 Block Diagram............................................................................................................................................... 1201
3 FTM signal descriptions............................................................................................................................................... 1203
4 Memory map and register definition.............................................................................................................................1203
4.1 Memory map.................................................................................................................................................. 1203
4.2 Register descriptions...................................................................................................................................... 1204
4.3 FTM register descriptions.............................................................................................................................. 1204
5 Functional Description..................................................................................................................................................1261
5.1 Clock source...................................................................................................................................................1261
5.2 Prescaler......................................................................................................................................................... 1261
5.3 Counter...........................................................................................................................................................1262
5.4 Channel Modes.............................................................................................................................................. 1268
5.5 Input Capture Mode....................................................................................................................................... 1270
5.6 Output Compare mode................................................................................................................................... 1275
5.7 Edge-Aligned PWM (EPWM) mode............................................................................................................. 1276
5.8 Center-Aligned PWM (CPWM) mode.......................................................................................................... 1278
5.9 Combine mode............................................................................................................................................... 1280
5.10 Modified Combine PWM Mode.................................................................................................................... 1288
5.11 Complementary Mode....................................................................................................................................1291
5.12 Registers updated from write buffers.............................................................................................................1293
5.13 PWM synchronization....................................................................................................................................1294
5.14 Inverting......................................................................................................................................................... 1310
5.15 Software Output Control Mode......................................................................................................................1311
5.16 Deadtime insertion......................................................................................................................................... 1313
5.17 Output mask................................................................................................................................................... 1317
5.18 Fault Control.................................................................................................................................................. 1318
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5.19 Polarity Control..............................................................................................................................................1322
5.20 Initialization................................................................................................................................................... 1323
5.21 Features Priority.............................................................................................................................................1323
5.22 External Trigger............................................................................................................................................. 1324
5.23 Initialization Trigger...................................................................................................................................... 1325
5.24 Capture Test Mode.........................................................................................................................................1327
5.25 DMA.............................................................................................................................................................. 1328
5.26 Dual Edge Capture Mode...............................................................................................................................1329
5.27 Quadrature Decoder Mode.............................................................................................................................1337
5.28 Debug mode................................................................................................................................................... 1343
5.29 Reload Points................................................................................................................................................. 1344
5.30 Global Load....................................................................................................................................................1347
5.31 Global time base (GTB).................................................................................................................................1348
5.32 Channel trigger output................................................................................................................................... 1349
5.33 External Control of Channels Output.............................................................................................................1350
5.34 Dithering........................................................................................................................................................ 1350
6 Reset Overview.............................................................................................................................................................1361
7 FTM Interrupts..............................................................................................................................................................1363
7.1 Timer Overflow Interrupt...............................................................................................................................1363
7.2 Reload Point Interrupt....................................................................................................................................1363
7.3 Channel (n) Interrupt......................................................................................................................................1363
7.4 Fault Interrupt................................................................................................................................................ 1363
8 Initialization Procedure.................................................................................................................................................1364
Chapter 46
Low Power Interrupt Timer (LPIT)
1 Chip-specific LPIT information....................................................................................................................................1367
1.1 Instantiation Information................................................................................................................................1367
1.2 LPIT/DMA Periodic Trigger Assignments ...................................................................................................1367
1.3 LPIT input triggers ........................................................................................................................................1368
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1.4 LPIT/ADC Trigger.........................................................................................................................................1368
1.5 S32K11X to S32K14X difference ................................................................................................................ 1369
2 Introduction...................................................................................................................................................................1370
2.1 Overview........................................................................................................................................................1370
2.2 Block Diagram............................................................................................................................................... 1371
3 Modes of operation....................................................................................................................................................... 1372
4 Memory Map and Registers..........................................................................................................................................1373
4.1 LPIT register descriptions..............................................................................................................................1373
5 Functional description...................................................................................................................................................1389
5.1 LPIT programming model............................................................................................................................. 1389
5.2 Initialization................................................................................................................................................... 1391
5.3 Timer Modes.................................................................................................................................................. 1392
5.4 Trigger Control for Timers............................................................................................................................ 1392
5.5 Channel Chaining...........................................................................................................................................1393
5.6 Detailed timing...............................................................................................................................................1394
Chapter 47
Low Power Timer (LPTMR)
1 Chip-specific LPTMR information...............................................................................................................................1407
1.1 Instantiation Information................................................................................................................................1407
1.2 LPTMR pulse counter input options..............................................................................................................1407
1.3 S32K11X to S32K14X difference ................................................................................................................ 1408
2 Introduction...................................................................................................................................................................1408
2.1 Features.......................................................................................................................................................... 1408
2.2 Modes of operation........................................................................................................................................ 1408
3 LPTMR signal descriptions.......................................................................................................................................... 1409
3.1 Detailed signal descriptions........................................................................................................................... 1409
4 Memory map and register definition.............................................................................................................................1410
4.1 LPTMR register descriptions......................................................................................................................... 1410
5 Functional description...................................................................................................................................................1415
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5.1 LPTMR power and reset................................................................................................................................ 1415
5.2 LPTMR clocking............................................................................................................................................1416
5.3 LPTMR prescaler/glitch filter........................................................................................................................1416
5.4 LPTMR counter............................................................................................................................................. 1417
5.5 LPTMR compare............................................................................................................................................1418
5.6 LPTMR interrupt............................................................................................................................................1418
5.7 LPTMR hardware trigger...............................................................................................................................1419
Chapter 48
Real Time Clock (RTC)
1 Chip-specific RTC information.................................................................................................................................... 1421
1.1 RTC instantiation........................................................................................................................................... 1421
1.2 RTC interrupts ...............................................................................................................................................1421
1.3 Software recommendation............................................................................................................................. 1421
1.4 Multiple trigger ............................................................................................................................................. 1421
1.5 S32K11X to S32K14X difference ................................................................................................................ 1422
2 Introduction...................................................................................................................................................................1422
2.1 Features.......................................................................................................................................................... 1422
2.2 Modes of operation........................................................................................................................................ 1422
2.3 RTC signal descriptions................................................................................................................................. 1422
3 Register definition.........................................................................................................................................................1423
3.1 RTC register descriptions...............................................................................................................................1423
4 Functional description...................................................................................................................................................1434
4.1 Power, clocking, and reset............................................................................................................................. 1434
4.2 Time counter.................................................................................................................................................. 1435
4.3 Compensation.................................................................................................................................................1435
4.4 Time alarm..................................................................................................................................................... 1436
4.5 Update mode.................................................................................................................................................. 1437
4.6 Register lock.................................................................................................................................................. 1437
4.7 Interrupt..........................................................................................................................................................1437
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Chapter 49
Low Power Serial Peripheral Interface (LPSPI)
1 Chip-specific LPSPI information..................................................................................................................................1439
1.1 Instantiation Information................................................................................................................................1439
2 Introduction...................................................................................................................................................................1440
2.1 Features.......................................................................................................................................................... 1442
2.2 Block Diagram............................................................................................................................................... 1442
2.3 Modes of operation........................................................................................................................................ 1443
2.4 Signal Descriptions........................................................................................................................................ 1443
2.5 Wiring options................................................................................................................................................1444
3 Memory Map and Registers..........................................................................................................................................1446
3.1 LPSPI register descriptions............................................................................................................................1446
4 Functional description...................................................................................................................................................1469
4.1 Clocking and resets........................................................................................................................................ 1469
4.2 Master Mode.................................................................................................................................................. 1470
4.3 Slave Mode.................................................................................................................................................... 1476
4.4 Interrupts and DMA Requests........................................................................................................................1478
4.5 Peripheral Triggers.........................................................................................................................................1479
Chapter 50
Low Power Inter-Integrated Circuit (LPI2C)
1 Chip-specific LPI2C information................................................................................................................................. 1481
1.1 Instantiation information................................................................................................................................1481
2 Introduction...................................................................................................................................................................1482
2.1 Features.......................................................................................................................................................... 1483
2.2 Block Diagram............................................................................................................................................... 1485
2.3 Modes of operation........................................................................................................................................ 1485
2.4 Signal Descriptions........................................................................................................................................ 1485
2.5 Wiring options................................................................................................................................................1486
3 Memory Map and Registers..........................................................................................................................................1487
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3.1 LPI2C register descriptions............................................................................................................................1488
4 Functional description...................................................................................................................................................1526
4.1 Clocking and Resets.......................................................................................................................................1526
4.2 Master Mode.................................................................................................................................................. 1527
4.3 Slave Mode.................................................................................................................................................... 1533
4.4 Interrupts and DMA Requests........................................................................................................................1535
4.5 Peripheral Triggers.........................................................................................................................................1537
Chapter 51
Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
1 Chip-specific LPUART information.............................................................................................................................1539
1.1 Instantiation Information................................................................................................................................1539
2 Introduction...................................................................................................................................................................1540
2.1 Features.......................................................................................................................................................... 1540
2.2 Modes of operation........................................................................................................................................ 1541
2.3 Signal Descriptions........................................................................................................................................ 1541
2.4 Block diagram................................................................................................................................................ 1541
3 Register definition.........................................................................................................................................................1543
3.1 LPUART register descriptions.......................................................................................................................1543
4 Functional description...................................................................................................................................................1569
4.1 Clocking and Resets.......................................................................................................................................1569
4.2 Baud rate generation...................................................................................................................................... 1569
4.3 Transmitter functional description................................................................................................................. 1570
4.4 Receiver functional description..................................................................................................................... 1574
4.5 Additional LPUART functions...................................................................................................................... 1580
4.6 Infrared interface............................................................................................................................................1582
4.7 Interrupts and status flags.............................................................................................................................. 1583
4.8 Peripheral Triggers.........................................................................................................................................1584
Chapter 52
Flexible I/O (FlexIO)
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1 Chip-specific FlexIO information.................................................................................................................................1587
1.1 FlexIO Configuration.....................................................................................................................................1587
2 Introduction...................................................................................................................................................................1587
2.1 Overview........................................................................................................................................................1587
2.2 Features.......................................................................................................................................................... 1588
2.3 Block Diagram............................................................................................................................................... 1588
2.4 Modes of operation........................................................................................................................................ 1589
2.5 FlexIO Signal Descriptions............................................................................................................................1589
3 Memory Map and Registers..........................................................................................................................................1590
3.1 FLEXIO register descriptions........................................................................................................................ 1590
4 Functional description...................................................................................................................................................1614
4.1 Clocking and Resets.......................................................................................................................................1614
4.2 Shifter operation.............................................................................................................................................1615
4.3 Timer Operation.............................................................................................................................................1617
4.4 Pin operation.................................................................................................................................................. 1621
4.5 Interrupts and DMA Requests........................................................................................................................1622
4.6 Peripheral Triggers.........................................................................................................................................1622
5 Application Information................................................................................................................................................1623
5.1 UART Transmit............................................................................................................................................. 1623
5.2 UART Receive...............................................................................................................................................1624
5.3 SPI Master......................................................................................................................................................1626
5.4 SPI Slave........................................................................................................................................................ 1628
5.5 I2C Master......................................................................................................................................................1629
5.6 I2S Master...................................................................................................................................................... 1631
5.7 I2S Slave........................................................................................................................................................ 1633
Chapter 53
FlexCAN
1 Chip-specific FlexCAN information.............................................................................................................................1635
1.1 Instantiation information................................................................................................................................1635
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1.2 Reset value of MDIS bit.................................................................................................................................1636
1.3 FlexCAN external time tick .......................................................................................................................... 1636
1.4 FlexCAN Interrupts........................................................................................................................................1636
1.5 FlexCAN Operation in Low Power Modes....................................................................................................1637
1.6 FlexCAN oscillator clock...............................................................................................................................1637
1.7 Supported baud rate ...................................................................................................................................... 1637
1.8 Requirements for entering FlexCAN modes: Freeze, Disable, Stop............................................................. 1637
2 Introduction...................................................................................................................................................................1639
2.1 Overview........................................................................................................................................................1640
2.2 FlexCAN module features............................................................................................................................. 1641
2.3 Modes of operation........................................................................................................................................ 1642
3 FlexCAN signal descriptions........................................................................................................................................ 1644
3.1 CAN Rx .........................................................................................................................................................1644
3.2 CAN Tx .........................................................................................................................................................1645
4 Memory map/register definition................................................................................................................................... 1645
4.1 FlexCAN memory mapping...........................................................................................................................1645
4.2 CAN register descriptions..............................................................................................................................1646
4.3 Message buffer structure................................................................................................................................1717
4.4 FlexCAN memory partition for CAN FD...................................................................................................... 1724
4.5 FlexCAN message buffer memory map.........................................................................................................1725
4.6 Rx FIFO structure.......................................................................................................................................... 1727
5 Functional description...................................................................................................................................................1730
5.1 Transmit process............................................................................................................................................ 1730
5.2 Arbitration process.........................................................................................................................................1732
5.3 Receive process..............................................................................................................................................1735
5.4 Matching process........................................................................................................................................... 1738
5.5 Receive process under Pretended Networking mode.....................................................................................1742
5.6 Move process................................................................................................................................................. 1747
5.7 Data coherence...............................................................................................................................................1749
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5.8 Rx FIFO......................................................................................................................................................... 1752
5.9 CAN protocol related features....................................................................................................................... 1755
5.10 Clock domains and restrictions...................................................................................................................... 1776
5.11 Modes of operation details.............................................................................................................................1780
5.12 Interrupts........................................................................................................................................................ 1784
5.13 Bus interface.................................................................................................................................................. 1785
6 Initialization/application information........................................................................................................................... 1786
6.1 FlexCAN initialization sequence................................................................................................................... 1786
Chapter 54
Synchronous Audio Interface (SAI)
1 Chip-specific SAI information .....................................................................................................................................1789
1.1 SAI configuration...........................................................................................................................................1789
1.2 Chip-specific register information................................................................................................................. 1790
2 Introduction...................................................................................................................................................................1791
2.1 Features.......................................................................................................................................................... 1791
2.2 Block diagram................................................................................................................................................ 1791
2.3 Modes of operation........................................................................................................................................ 1792
3 External signals.............................................................................................................................................................1793
4 Memory map and register definition.............................................................................................................................1793
4.1 I2S register descriptions.................................................................................................................................1793
5 Functional description...................................................................................................................................................1826
5.1 SAI clocking.................................................................................................................................................. 1826
5.2 SAI resets....................................................................................................................................................... 1828
5.3 Synchronous modes....................................................................................................................................... 1829
5.4 Frame sync configuration...............................................................................................................................1830
5.5 Data FIFO...................................................................................................................................................... 1830
5.6 Word mask register........................................................................................................................................ 1834
5.7 Interrupts and DMA requests.........................................................................................................................1835
Chapter 55
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Ethernet MAC (ENET)
1 Chip-specific ENET information..................................................................................................................................1839
1.1 Software guideline during ENET operation...................................................................................................1839
2 Introduction...................................................................................................................................................................1839
3 Overview.......................................................................................................................................................................1840
3.1 Features.......................................................................................................................................................... 1840
3.2 Block diagram................................................................................................................................................ 1843
4 External signal description............................................................................................................................................1843
5 Memory map/register definition................................................................................................................................... 1845
5.1 Interrupt Event Register (ENET_EIR)...........................................................................................................1850
5.2 Interrupt Mask Register (ENET_EIMR)........................................................................................................1853
5.3 Receive Descriptor Active Register (ENET_RDAR)....................................................................................1856
5.4 Transmit Descriptor Active Register (ENET_TDAR)...................................................................................1857
5.5 Ethernet Control Register (ENET_ECR).......................................................................................................1858
5.6 MII Management Frame Register (ENET_MMFR)...................................................................................... 1860
5.7 MII Speed Control Register (ENET_MSCR)................................................................................................ 1860
5.8 MIB Control Register (ENET_MIBC).......................................................................................................... 1863
5.9 Receive Control Register (ENET_RCR)....................................................................................................... 1864
5.10 Transmit Control Register (ENET_TCR)...................................................................................................... 1867
5.11 Physical Address Lower Register (ENET_PALR)........................................................................................ 1869
5.12 Physical Address Upper Register (ENET_PAUR)........................................................................................ 1869
5.13 Opcode/Pause Duration Register (ENET_OPD)........................................................................................... 1870
5.14 Descriptor Individual Upper Address Register (ENET_IAUR).................................................................... 1870
5.15 Descriptor Individual Lower Address Register (ENET_IALR).................................................................... 1871
5.16 Descriptor Group Upper Address Register (ENET_GAUR).........................................................................1871
5.17 Descriptor Group Lower Address Register (ENET_GALR).........................................................................1872
5.18 Transmit FIFO Watermark Register (ENET_TFWR)................................................................................... 1872
5.19 Receive Descriptor Ring Start Register (ENET_RDSR)...............................................................................1873
5.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR).................................................................. 1874
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5.21 Maximum Receive Buffer Size Register (ENET_MRBR)............................................................................ 1875
5.22 Receive FIFO Section Full Threshold (ENET_RSFL).................................................................................. 1876
5.23 Receive FIFO Section Empty Threshold (ENET_RSEM)............................................................................ 1876
5.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)............................................................................ 1877
5.25 Receive FIFO Almost Full Threshold (ENET_RAFL)..................................................................................1877
5.26 Transmit FIFO Section Empty Threshold (ENET_TSEM)........................................................................... 1878
5.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM)...........................................................................1878
5.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)................................................................................ 1879
5.29 Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................... 1879
5.30 Frame Truncation Length (ENET_FTRL).....................................................................................................1880
5.31 Transmit Accelerator Function Configuration (ENET_TACC).................................................................... 1880
5.32 Receive Accelerator Function Configuration (ENET_RACC)......................................................................1881
5.33 Reserved Statistic Register (ENET_RMON_T_DROP)................................................................................1882
5.34 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS)............................................................ 1883
5.35 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)........................................................1883
5.36 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)........................................................1884
5.37 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN)............................ 1884
5.38 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)............1884
5.39 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)..........1885
5.40 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG).....................1885
5.41 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)........ 1886
5.42 Tx Collision Count Statistic Register (ENET_RMON_T_COL).................................................................. 1886
5.43 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................... 1886
5.44 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127)............................................ 1887
5.45 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)........................................ 1887
5.46 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)........................................ 1888
5.47 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................... 1888
5.48 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047)................................ 1889
5.49 Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048).......................... 1889
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5.50 Tx Octets Statistic Register (ENET_RMON_T_OCTETS).......................................................................... 1889
5.51 Reserved Statistic Register (ENET_IEEE_T_DROP)...................................................................................1890
5.52 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK)................................................ 1890
5.53 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................... 1891
5.54 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).........................1891
5.55 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)....................................1891
5.56 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL).................................. 1892
5.57 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL).....................1892
5.58 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR)....................1893
5.59 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)....................... 1893
5.60 Reserved Statistic Register (ENET_IEEE_T_SQE)...................................................................................... 1893
5.61 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC)...............................1894
5.62 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK)...........1894
5.63 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS)............................................................ 1895
5.64 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)....................................................... 1895
5.65 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)....................................................... 1895
5.66 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)............................1896
5.67 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENET_RMON_R_UNDERSIZE)................................................................................................................1896
5.68 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE)...1897
5.69 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................... 1897
5.70 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)....... 1897
5.71 Reserved Statistic Register (ENET_RMON_R_RESVD_0).........................................................................1898
5.72 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64)...................................................................1898
5.73 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)........................................... 1899
5.74 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)....................................... 1899
5.75 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)....................................... 1899
5.76 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................... 1900
5.77 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................... 1900
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5.78 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)........................... 1901
5.79 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)..........................................................................1901
5.80 Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP)................................................. 1901
5.81 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................... 1902
5.82 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC).............................................. 1902
5.83 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN)................................ 1903
5.84 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)..........................................1903
5.85 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC)...................................1903
5.86 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK).........1904
5.87 Adjustable Timer Control Register (ENET_ATCR)..................................................................................... 1904
5.88 Timer Value Register (ENET_ATVR).......................................................................................................... 1906
5.89 Timer Offset Register (ENET_ATOFF)........................................................................................................ 1907
5.90 Timer Period Register (ENET_ATPER)........................................................................................................1907
5.91 Timer Correction Register (ENET_ATCOR)................................................................................................ 1908
5.92 Time-Stamping Clock Period Register (ENET_ATINC).............................................................................. 1908
5.93 Timestamp of Last Transmitted Frame (ENET_ATSTMP).......................................................................... 1909
5.94 Timer Global Status Register (ENET_TGSR)...............................................................................................1909
5.95 Timer Control Status Register (ENET_TCSRn)............................................................................................1910
5.96 Timer Compare Capture Register (ENET_TCCRn)......................................................................................1911
6 Functional description...................................................................................................................................................1912
6.1 Ethernet MAC frame formats........................................................................................................................ 1912
6.2 IP and higher layers frame format..................................................................................................................1915
6.3 IEEE 1588 message formats.......................................................................................................................... 1919
6.4 MAC receive.................................................................................................................................................. 1923
6.5 MAC transmit................................................................................................................................................ 1929
6.6 Full-duplex flow control operation................................................................................................................ 1933
6.7 Magic packet detection.................................................................................................................................. 1935
6.8 IP accelerator functions..................................................................................................................................1936
6.9 Resets and stop controls.................................................................................................................................1940
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6.10 IEEE 1588 functions...................................................................................................................................... 1943
6.11 FIFO thresholds..............................................................................................................................................1947
6.12 Loopback options...........................................................................................................................................1950
6.13 Legacy buffer descriptors...............................................................................................................................1951
6.14 Enhanced buffer descriptors...........................................................................................................................1952
6.15 Client FIFO application interface.................................................................................................................. 1958
6.16 FIFO protection..............................................................................................................................................1961
6.17 Reference clock..............................................................................................................................................1963
6.18 PHY management interface........................................................................................................................... 1964
6.19 Ethernet interfaces..........................................................................................................................................1967
Chapter 56
Debug
1 Introduction...................................................................................................................................................................1973
2 CM4 and CM0  ROM table......................................................................................................................................... 1976
3 Debug port.................................................................................................................................................................... 1977
3.1 JTAG-to-SWD change sequence................................................................................................................... 1978
4 Debug port pin descriptions..........................................................................................................................................1979
5 System TAP connection................................................................................................................................................1979
5.1 IR codes..........................................................................................................................................................1979
6 MDM-AP status and control registers.......................................................................................................................... 1980
6.1 MDM-AP Control Register............................................................................................................................1981
6.2 MDM-AP Status Register.............................................................................................................................. 1982
7 Debug resets..................................................................................................................................................................1983
8 AHB-AP........................................................................................................................................................................1984
9 ITM............................................................................................................................................................................... 1984
10 Core trace connectivity................................................................................................................................................. 1985
11 TPIU..............................................................................................................................................................................1985
12 DWT............................................................................................................................................................................. 1986
13 MTB .............................................................................................................................................................................1986
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14 Debug in low-power modes..........................................................................................................................................1987
14.1 Debug module state in low-power modes......................................................................................................1987
15 Debug and security....................................................................................................................................................... 1988
Chapter 57
JTAG Controller (JTAGC)
1 Chip-specific JTAGC information................................................................................................................................1989
2 Introduction...................................................................................................................................................................1989
2.1 Block diagram................................................................................................................................................ 1989
2.2 Features.......................................................................................................................................................... 1990
2.3 Modes of operation........................................................................................................................................ 1990
3 External signal description............................................................................................................................................1992
3.1 Test clock input (TCK).................................................................................................................................. 1992
3.2 Test data input (TDI)......................................................................................................................................1992
3.3 Test data output (TDO).................................................................................................................................. 1992
3.4 Test mode select (TMS).................................................................................................................................1993
4 Register description...................................................................................................................................................... 1993
4.1 Instruction register......................................................................................................................................... 1993
4.2 Bypass register............................................................................................................................................... 1993
4.3 Device identification register......................................................................................................................... 1994
4.4 Boundary scan register...................................................................................................................................1994
5 Functional description...................................................................................................................................................1995
5.1 JTAGC reset configuration............................................................................................................................ 1995
5.2 IEEE 1149.1-2001 (JTAG) TAP....................................................................................................................1995
5.3 TAP controller state machine.........................................................................................................................1995
5.4 JTAGC block instructions..............................................................................................................................1998
5.5 Boundary scan................................................................................................................................................2001
6 Initialization/application information........................................................................................................................... 2001
标签： S32k 硬件手册
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S32K14X系列MCU硬件手册.pdf(共2023页)

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