Debug Interface Architecture Specification

【实例截图】

【核心代码】

Contents
ARM Debug Interface Architecture Specification
ADIv5.0 to ADIv5.2
Preface
About this book ............................................................................................................ x
Using this book ........................................................................................................... xi
Conventions ............................................................................................................... xii
Additional reading ..................................................................................................... xiv
Feedback ................................................................................................................... xv
Chapter 1 Introduction
1.1 About the ARM Debug Interface version 5 (ADIv5) ............................................... 1-18
1.2 The function of the ARM Debug Interface .............................................................. 1-20
1.3 The subdivisions of an ARM Debug Interface v5 implementation ......................... 1-22
1.4 The external interface, the Debug Port (DP) .......................................................... 1-23
1.5 The resource interface, the Access Ports (APs) .................................................... 1-24
1.6 Design choices and implementation examples ...................................................... 1-28
Chapter 2 The Debug Port (DP)
2.1 Common Debug Port features ............................................................................... 2-34
2.2 DP architecture versions ........................................................................................ 2-40
2.3 DP register descriptions ......................................................................................... 2-45
2.4 System and debug power and debug reset control ............................................... 2-62
Chapter 3 The JTAG Debug Port (JTAG-DP)
3.1 The Debug TAP State Machine introduction .......................................................... 3-70
3.2 The scan chain interface ........................................................................................ 3-71
3.3 IR scan chain and IR instructions .......................................................................... 3-74
3.4 DR scan chain and DR registers ............................................................................ 3-78
Contents
vi Copyright © 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved. ARM IHI 0031C
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Chapter 4 The Serial Wire Debug Port (SW-DP)
4.1 Introduction to the Serial Wire Debug Port ............................................................. 4-88
4.2 Introduction to the ARM Serial Wire Debug (SWD) protocol .................................. 4-89
4.3 Serial Wire Debug protocol operation .................................................................... 4-93
4.4 Serial Wire Debug interface ................................................................................. 4-104
Chapter 5 The Serial Wire/JTAG Debug Port (SWJ-DP)
5.1 Serial Wire/JTAG Debug Port (SWJ-DP) ............................................................. 5-108
5.2 SWD and JTAG select mechanism ...................................................................... 5-110
5.3 Dormant operation ................................................................................................ 5-113
5.4 Restriction on switching ........................................................................................ 5-120
Chapter 6 The Access Port (AP)
6.1 Overview of Access Ports (APs) .......................................................................... 6-122
6.2 Selecting and accessing an AP ............................................................................ 6-123
6.3 The Programmers’ Model for Access Port (AP) registers ..................................... 6-124
Chapter 7 The Memory Access Port (MEM-AP)
7.1 About the function of a Memory Access Port (MEM-AP) ..................................... 7-128
7.2 MEM-AP functions ................................................................................................ 7-132
7.3 Implementing a MEM-AP ..................................................................................... 7-142
7.4 MEM-AP examples of pushed-verify and pushed-compare ................................. 7-144
7.5 MEM-AP register summary .................................................................................. 7-146
7.6 MEM-AP register descriptions .............................................................................. 7-147
Chapter 8 The JTAG Access Port (JTAG-AP)
8.1 Overview of the JTAG Access Port (JTAG-AP) ................................................... 8-162
8.2 Operation of the JTAG-AP ................................................................................... 8-166
8.3 The JTAG Engine Byte Command Protocol ......................................................... 8-169
8.4 JTAG-AP register summary ................................................................................. 8-176
8.5 JTAG-AP register descriptions ............................................................................. 8-177
Chapter 9 Component and Peripheral ID Registers
9.1 Component and Peripheral ID registers ............................................................... 9-186
9.2 The Component ID Registers ............................................................................... 9-187
9.3 The Peripheral ID Registers ................................................................................. 9-191
Chapter 10 ROM Tables
10.1 ROM Table overview .......................................................................................... 10-200
10.2 ROM Table entries ............................................................................................. 10-202
10.3 The MEMTYPE register ..................................................................................... 10-205
10.4 Component and Peripheral ID Registers ............................................................ 10-206
10.5 ROM Table hierarchies ...................................................................................... 10-207
Appendix A Standard Memory Access Port Definitions
A.1 Introduction .......................................................................................................... A-212
A.2 AMBA AXI3 and AXI4 .......................................................................................... A-213
A.3 AMBA AXI4 with ACE-Lite ................................................................................... A-215
A.4 AMBA AHB .......................................................................................................... A-217
A.5 AMBA APB2 and APB3 ....................................................................................... A-218
Appendix B Cross-over with the ARM Architecture
B.1 Introduction .......................................................................................................... B-220
B.2 ARMv6-M architecture ......................................................................................... B-221
B.3 ARMv7-M architecture profile .............................................................................. B-222
B.4 ARMv7-A without Large Physical Address Extension and ARMv7-R architecture profiles
 B-223
Contents
ARM IHI 0031C Copyright © 2006, 2009, 2012, 2013 ARM Limited or its affiliates. All rights reserved. vii
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B.5 ARMv7-A with Large Physical Address Extension and ARMv8-A architecture profiles .
B-224
B.6 Summary of the required ADIv5 implementations ............................................... B-225
Appendix C Pseudocode Definition
C.1 About ARM pseudocode ...................................................................................... C-228
C.2 Data types ............................................................................................................ C-229
C.3 Expressions ......................................................................................................... C-233
C.4 Operators and built-in functions ........................................................................... C-235
C.5 Statements and program structure ...................................................................... C-240
Glossary