Verilog实现对sdram的操作（sdram_if.v）

always @(posedge CLK or posedge RST)
begin
if (RST)
begin
sdr_state <= S_IDLE;
//priority_judge0 <= 1'b1;
//priority_judge1 <= 1'b0;
init_complete <= 0;
ref_ack_flag <= 0;
end
else
begin
case ( sdr_state )
S_IDLE :
begin
if (init_wait_200)
sdr_state <= S_INIT_PRE;
else
sdr_state <= S_IDLE;
end
//  initialization precharge
S_INIT_PRE :
begin
sdr_state <= S_INIT_PRE_NOP;
end
S_INIT_PRE_NOP :
begin
if (time_is_tRP)
sdr_state <= S_INIT_REF;
else
sdr_state <= S_INIT_PRE_NOP;
end
//  initialization autorefresh 8 times
S_INIT_REF :
begin
sdr_state <= S_INIT_REF_NOP;
end
S_INIT_REF_NOP :
begin
if (time_is_tRC & ref_8_times)
sdr_state <= S_MRS;
else if (time_is_tRC)
sdr_state <= S_INIT_REF;
else
sdr_state <= S_INIT_REF_NOP;
end
//  initialization mode register set
S_MRS :
begin
sdr_state <= S_MRS_NOP;
end
S_MRS_NOP :
begin
if (time_is_tMRD)
begin
sdr_state     <= S_IDLE_REF;
init_complete <= 1;
end
else
sdr_state <= S_MRS_NOP;
end
//  normal autorefresh
S_IDLE_REF :
begin
sdr_state <= S_IDLE_REF_NOP;
ref_ack_flag<=0;
end
S_IDLE_REF_NOP :
begin

if( time_is_tRC && refresh_time )
begin           //-----------change------------
sdr_state <= S_IDLE_REF;
ref_ack_flag <= 1;
end
else if (time_is_tRC & RD_RQ_i_latch)
begin
sdr_state <= S_RD_ACT;
//priority_judge0 <= ~ priority_judge0;
end
else if (time_is_tRC & WR_RQ_i_latch )
begin
sdr_state <= S_WR_ACT;
//priority_judge0 <= ~ priority_judge0;
end


 
else if (time_is_tRC)
sdr_state <= S_IDLE_REF;
else
begin
sdr_state <= S_IDLE_REF_NOP;
//priority_judge0 <= ~ priority_judge0;
end
end
//  write active
S_WR_ACT :
begin
sdr_state <= S_WR_ACT_NOP;
end
//  read active
S_RD_ACT :
begin
sdr_state <= S_RD_ACT_NOP;
end
S_WR_ACT_NOP :
begin
if (time_is_tRCD)
sdr_state <= S_WR_COL;
else
sdr_state <= S_WR_ACT_NOP;
end
S_RD_ACT_NOP :
begin
if (time_is_tRCD)
sdr_state <= S_RD_COL;
else
sdr_state <= S_RD_ACT_NOP;
end
//  write column address
S_WR_COL :
begin
if (wr_cnt_is_LEN | page_end)
sdr_state <= S_WR_END;
else
sdr_state <= S_WR_COL;
end
//  read column address
S_RD_COL :
begin
if (rd_cnt_is_LEN | page_end)
sdr_state <= S_PRE;
else
sdr_state <= S_RD_COL;
end
S_WR_END :
begin
sdr_state <= S_PRE;
end
//  page_end or w/r end precharge
S_PRE :
begin
sdr_state <= S_PRE_NOP;
end
S_PRE_NOP :
begin
if (time_is_tRP & (rd_cnt_is_LEN_latch|wr_cnt_is_LEN_latch))
// sdr_state <= S_IDLE_REF;
sdr_state <= S_IDLE_REF_NOP;
else if(WR_RQ_i_latch )
begin
sdr_state <= S_WR_ACT;
//priority_judge1 <= ~ priority_judge1;
end
else if(RD_RQ_i_latch )
begin
sdr_state <= S_RD_ACT;
//priority_judge1 <= ~ priority_judge1;
end
else
begin
//priority_judge1 <= ~ priority_judge1;
sdr_state <= S_PRE_NOP;
end
end
default :
sdr_state <= S_IDLE;
endcase
end
end