xilinx DPD document

【实例简介】
xilinx DPD document pre-distortion negates the non-linear effects of a power amplifier generated when transmitting a wide-band signal.
XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL Table of contents ￡ⅫLNX DPD-QMC Performance Dual tx Path performance 86 FPGA Resource Utilization, Timing Performance, and Power Consumption Timing Performance 87 Power Consumption 87 Using the Hardware Design Files 90 Software Tools Requirements IP Core ZIP File Descriptions Interface Description 91 Port Descriptie 91 Interfaces 93 Clock Interface Data path Interface 95 SRx Interfac 6 Host Interface 97 Dual Antenna Interface ting dpd netlist 98 Instantiation Example sing dpd_build. bat Script Constraints 101 Running simulation in System generator Hardware in the loop in System generator 103 Instantiating in a User Design stantiating dpd 1 (dpd_2tx_cw) Modifying various Project Files Using the Supplied Software 106 Control shell Interface 107 Triggering a Control Mode Supplied control Modes Status Indicators 113 ECF Parameters and Status Monitoring 116 ECF Parameters 116 Estimation Parameter tests 116 ECF Monitoring 117 DCL Parameters and Status Monitoring 118 DCL Parameters 118 119 Coefficient Management 120 System Integration ..122 Sample rate Required Signal Levels and Properti 122 RF Performance 123 Placement in the Signal C 123 Operations Guide nitial Setup and Debug Amplifier Characterization Establishing DPD Parameters 125 Capture Mode Estimation Parameters DCL Parameters Control and monit References 127 127 AppendⅸA:Ab Appendix B: Using executable Control mod Loading New EC Parameters Command 129 UPDATE_ECF_PARAMETERS(175 Loading New QMC Parameters Command 13 SET_ QMC_ PARAMS(26 131 Loading New DCL Parameters Command SET_DCL_PARAMETERS(12 mIning p Parameter Run dcL Controller c RUN_ DCL 14 133 DCL C d routines 135 Run DCL Controller with QMc Command APP1128(v1.0) March18,2009 Www.xuinX.com XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL Table of contents ￡ⅫLNX RUN_ DCL_WITH_QMC 271 135 Run DCL Controller with Accelerated Startup QMC Command 136 RUN DCL WITH ACCEL QMC 231 Exit dcL Controller command 36 EX什T_DcL{18}.. 136 Capture New Set of Samples in the Capture RAM Command 136 CAPTURE NEW SAMPLES 20 36 un a Single Iteration of the DPD Update Algorithm Command 137 COMPUTE_NEW_COEFFICIENTS(2 Run a Single Iteration of the QMC Update Algorithm Command 138 QMC_SINGLE_STEP(22) 138 Reset the coefficients command RESET_COEFFICIENTS 3 139 Reset the Qmc Coefficients command 139 RESET_QMC121) 139 Enable External RX Path Select Control Command 139 ENABLE EXT RXSEL28 Enable Internal rX Path Select Control command ENABLE INT RXSEL291 40 Set Meter Length Command .140 SET METER LENGTH6 Read the Power meters command READ_POWER_METERS(13 着1 141 Read the Capture Power Meter Command ..,.,.142 READ- CAPTURE_ POWER__METERS 161 142 Read Capture RAM Contents Command 142 GET_CAPTURE_RAM_PAGE(4) 142 Read the Histogram Command 143 GET_HISTOGRAM_PAGE5 Read the capture histogram command GET_CAPTURE_HISTOGRAM_PAGE[15] Turn QMC OFF Command 144 QMC_OFF1251 Turn QMC ON Command 14 QMC_ON{24}....... Turn dPd off command 145 DPD_OFF[7 Turn dPd on o command ..145 DPD_ON_0(8 Turn dpdon 1 command 145 DPD_ON_119 145 Turn DPD oN 2 Command 145 DPD_ON_2(10] 145 Set Capture Parameters command 146 SET_ CAPTURE_PARAMS(11 146 Read dPD Parameters command READ_CONFIGURATION 1S 46 Restore Default Configuration Command .......148 RESTORE DEFAULTS(19 A48 Command/Monitoring E) Example 1 -dumping the Full 4K Samples 148 Example 2-Dumping the Full Histog Example 3- reading the full power Meter Appendix C: SBRAM Memory Map 151 Appendix D: Dual Antenna SBRAM Memory Map 157 Revision histo Support Notice of disclai 158 APP1128(v1.0) March18,2009 Www.xuinX.com XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL List of Figures ￡ⅫLNX List of Figures Figure 1: Spectrum Analyzer Screenshot for CFR and DPD Figure 2: Spectrum Analyzer Screenshot for dPd With (yellow line) and Without Cfr (Blue Line) Figure 3: Various Output Power Dependencies of Adjacent Channel Power 9 10 Figure 4: Efficiency Versus Output Power Figure 5: DPD Functional view 13 Figure 6: U Matrix 14 Fiqure 7: Xilinx DPD Architecture 16 Figure 8: MP Predistorter with LUT Structure 17 Figure 9: DPD Estimation Core Function Processes ..17 Figure 10: DPD Sample Capture Acceptance Processes ..18 Figure 11: Predistortion Characteristics 19 Figure 12: DCL Tracking NsNL Characteristics 21 Figure 13: DCL Process for NsN Characteristics ,,,22 Figure 14: FPGA Hardware for Dual Tx paths 23 Figure 15: Quadrature Modt Imperfection EXample Figure 16: Generalized QMC Circuit 26 Figure 17: Simplified QMC Circuit 26 Figure 18: DPD With Integrated QMC Architecture Figure 19: DPD Estimation Core Function Processes 27 Figure 20: Effect of Number of Samples(L)on Tracking Error 29 Figure 21: Effect of Number of Gain Terms on Convergence Time 31 igure 22: QMC Processing T ime Vs 32 Figure 23: DPD Estimation Core Function Processes ,,,33 Figure 24: Estimated PA Inverse Response from LUT Contents 34 Figure 25: EXample of DPD Frequency Response with Coefficients Estimated Using 4 Carrier WCDMA-7.5.-2.5.+2.5 and +7.5 MHz Carriers .,35 Figure 26: Example of dPD Frequency Response with Coefficients Estimated Using 1 carrier WCDMA at-7.5 MHZ 36 Figure 27: PA Over-Drive Detection Steps 1 and 2 .,37 Figure 28: PA Over-Drive Detection Step 3 .38 Figure 29: ODD EXample Results 39 Figure 30: ODD Example with Various PAR Settings Using a WCDMA [110 1] Configuration 40 Figure 31: DPD IP Core(1 Tx): H re Implementation 41 Figure 32: DPD IP Core(2 Tx): Hardware Implementation 42 Figure 33: DPD IP Core(1 Tx): System Generator Design Top-Level Screenshot... 43 Figure 34: DPD IP Core(2 Tx): System Generator Design Top-Level Screenshot... 43 Figure 35: DPD IP Core(2 Tx): System Generator DPD Design Level Screenshot Figure 36: DPD IP Core(1 Tx): Samplerate Path Subsystem Screenshot(dpd_srp) Figure 37: DPD IP Core(2 Tx): Samplerate Path Subsystem Screenshot(srp_unreg).. 46 Figure 38: dpd_tx_path Structure(Parallel) 47 Figure 39: DPD IP Core(2 Tx): CORDIC Subsystem Screenshot Figure 40: dpd_tx_path Structure Three Clocks per Sample 48 Figure 41: DPD IP Core(2 Tx): Predistort Filter Subsystem Screenshot 49 Figure 42: dpd_tx_path LUT Detail ,,,50 Figure 43: DPD IP Core(2 Tx): Capture Data Subsystem 51 Figure 44: DPD IP Core(2 Tx): Capture Control Subsystem ,52 Figure 45: DPD IP Core(1 Tx): Capture Sigs Subsystem igure 46: DPD IP Core(2 Tx): Capture Sigs Subsystem 54 Figure 47: DPD IP Core(2 Tx): Measurements Subsystem 55 Figure 48: Average Measurements Subsystem Screenshot ..56 Figure 49: Interval Power Meter Subsystem Screenshot 57 Figure 50: Interval Histogram Subsystem Screenshot 58 Figure 51: readings_mux Subsystem Screenshot Figure 52: QMC Circuit 60 APP1128(v1.0) March18,2009 Www.xuinX.com XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL List of Figures ￡ⅫLNX Figure 53: DPD IP Core(2 Tx): QMC Subsystem 61 Figure 54: Screenshot of Configurable Subsystem Library for dPd 62 igure 55: DPD IP Core(2 Tx): updaterate_path Subsystem 63 Figure 56: ECF Update Times 69 Figure 57: Hardware Setup for DPD Testing 70 Figure 59: Spectra for a Single WCDMA Carrier Before and After DPD Figure 58: Test FPGA 73 igure 60: Spectra for Four WCDMA Carriers Before and After DPD 73 Figure 61: Spectra for Two Non-adjacent WCDMA Carriers 10 MHz Apart Before and After DPD 74 Figure 62: Spectra for a single 10 MHz WimAX Carrier Before and After dPD 75 Figure 63: Power and Adjacent Channel Power versus Time with the WCDMA Ramp Test with period 25 Seconds 76 Figure 64: Spectra for a Single 10 MHz LTE Carrier Before and After DPD igure 65: Spectra for a Single 20 MHz LTE Carrier Before and After DPD 78 Figure 66: Spectra for Four TD-SCDMa Carriers in 10 MHz Total Bandwidth Carrier Before and After DPD 79 Figure 67: Spectra for Six TD-SCDMA Carriers in 20 MHZ Total Bandwidth Carrier Before and After DPD 79 Figure 68: Spectra for Four GSM Carriers in 20 MHz Total Bandwidth Carrier Before and After dPD 80 Figure 69: Spectra for One 10 MHZ LTE Carrier and Four GSM Carriers in 20 MHz Total Bandwidth Carrier Before and After DPD 81 Figure 70: Out of Band Power Ratio Versus Iteration Count for a Single WCDMA Carrier 82 Figure 71: Power and Out of Band Power Ratio versus T ime with a Power Ramp with Period 10 Seconds 83 Figure 72: Adjacent Channel Power versus Iteration Count for WCDMA Pulsed Data.. 84 Figure 73: Spectra for a Single Offset WCDMA Carrier Before and After QMC and DPD Correction 85 Figure 74: Evolution of the Spectrum in dual Tx- Split Configuration 86 Figure 75. Power Measurement Setup on the FPGa 88 Figure 76: DPD IP Core Top-level Component Figure 77: Clock Generation Using dCm and BuFGmux to Avoid glitches Figure 78: Data Path Interface Timing Diagram 95 Figure 79: Shared Block RAM Interface Timing Diagram(WRITE_FIRST Mode)... 97 Figure 80: DPD IP Core: System Generator Block GU 98 Figure 81: Netlisting Process Popups 99 Figure 82: dpa_build. bat Command Options Help Screen............ 101 Figure 83: Example of dpd_1tx_wrap uct in the dpd_1tx_v4 Directory 102 igure 84: General 2 KB Shared SBRAM Structure 107 Figure 85: Control Shell Flow graph 108 Figure 86: Spectra with Selected Estimation Parameter Combinations....... 117 Figure 87: DCL Parameter Affects 118 Figure 88: DCL Monitoring Examples(NSNL and QSNL settings) 119 Figure 89:(a)Histogram with CFR(b)Histogram without CFR 124 Figure 90: DCL Command Pseudo Code :· ,,,,,,,,,135 APP1128(v1.0) March18,2009 Www.xuinX.com 6 XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL List of tables ￡ⅫLNX List of tables Table 1: dPd IP Core Resource Utilization Table 2: dpd_sampleratepath Measurements Port Data Selections 59 Table 3: Software Memory Map Components 65 Table 4: Control Registers ∴66 Table 5: dpd_sampleratepath LUT Map 67 Table 6: DPd IP Core Resource Utilization 8 Table 7: DPD IP Core Timing Performance .87 Table 8: Measured Power Consumption 99 Table 9: ZIP File Summary 90 Table 10: Top-level l/Os for the DPD IP Core 92 Table 11: Typical Clock Frequencies Used to Test DPD IP Core on AXIS CDRSX Boards 94 able12: Build Subdirectory Contents( Example with dpd_1ⅸ Design)…… 100 Tab/e 13 DCL Control modes 110 Table 14: Coefficient Set Control modes 110 Table 15: Diagnostic Control Modes 111 Table 16: Maintenance Control modes 112 Table 17: QMC Control modes 112 Table 18: RX path select Control Modes 112 Table 19 COMMANDSTATUS[8] Register Codes ∴113 Table 20: Code Pointer values 115 Table 21: Estimation Parameter Combinations .116 Table 22: Base Word Address for each Coefficient Set 120 Table 23: Coefficient Scaling Registers 121 Table 24: Capture Scaling values 121 Table 26: Typical Bandwidth and Recommended Minimum Sample Rates for Variou..121 Table 25: Max Capture for Coefficient Sets Configurations 122 Table 27: Parameters for UPDATE_ ECF_ PARAMETERS 171 129 Table 28: Possible Response to UPDATE_ECF_PARAMETERS(17 Command 130 7ab/e29: Parameters for SET QMC_ PARAMS{26}……………… 131 Table 30: Possible Response to UPDATE_ECF_PARAMETERS(17) Command 131 Table 31: Parameters for SET_DCL_PARAMETERS(12) 132 Table 32: Continuous Responses During RUN_DCL(14) Operation 133 Table 33: Responses During RUN_ DCL[14 Operation After a Coefficient Update .......134 Table 34: Possible Status Response to CAPTURE_NEW SAMPLES( 20) Command . ...136 Table 35: Possible Status Response to COMPUTE_ NEW_COEFFICIENTS2) Command 面着套面1B 137 Table 36: QMC Coefficient Registers 138 Table 37: Possible Status Response to QMC_SINGLE_STEP(22) Command 138 Table 38: EXternal Port Switch Hand-Shake Registers 139 Table 39: Parameters for SET_METER_ LENGTH6 140 Table 40: Response from READ_POWER_METERS(13 141 Table 41: Response from READ_CAPTURE_POWER_ METERS(16] 142 Table 42: Parameters for GET_CAPTURE_RAM_PAGE4 142 Table 43: Response from GET_ CAPTURE_RAM_PAGE[4 143 Table 44: Capture RAM Sample Formatting Prior to Down Conversion 143 Table 45: Required Parameters for GET_HISTOGRAM_PAGE[5] 143 Table 46: Response from GET_ HISTOGRAM_PAGE5 144 Table 47: Parameters for GET_ CAPTURE_HISTOGRAM_PAGE 151 144 Table 48: Response from GET_CAPTURE_HISTOGRAM_PAGE[) 144 Table 49: Required Parameters for SET_ CAPTURE_ PARAMS( 111 146 Table 50: Response from READ_ CONFIGURATION 1 Command 146 ab/e51: SBRAM Memory Map……… 151 Table 52: SBRAM Memory Map for Port B Specific Values 157 APP1128(v1.0) March18,2009 Www.xuinX.com XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL ntroduction ￡ⅫLNX Introduction Benefits of dPd DPD provides a means to reduce the capital expenditure(CAPEX)and operational expenditure (OPEX) for wireless basestation vendors and operators by allowing the power amplifiers (Pas) to be driven at higher output powers while still maintaining spectral mask performance. CAPEX is reduced via deploying lower cost PAs for a given output power requirement and OPEX is reduced through improvements in power efficiency. Spectral Mask Compliance Figure 1 shows the spectra obtained from driving a class-AB Laterally Diffused Metal Oxide Silicon(LDMOS)2140 MHz PA at 44. 5 dBm. These results are obtained with the test setup described in"Performance Testing The signal is UMTS Test Model 1 with 64 DCH as specified in the 3GPP standards [ref 1. the pink line is the original signal, the yellow line is obtained when Crest Factor Reduction(CFR)is applied, the blue line is obtained when both CFR and DPD are applied. The data was obtained using the Xilinx WCDMA Digital Front-End reference design [Ref 3]. The peak-to-average ratio is 6.5 dB. this result is an example of DPD performance Agilent的7:的9:170ut22,2的的7 Trace Mkr- 2.7 MH Rot e de Atton1的dB 32.78dB Face Avg Clear Write Max hole Min hold PAvg Hiew E(f Blank Center2,14的GH span1的MH RcsE3的kH乙 cp袋9 6的1pt Figure 1: Spectrum Analyzer Screenshot for CFR and DPD Comprehensive test results for many different signals are given in"Performance Testing. It is interesting to note the effects of cfr, which are widely believed to be beneficial. Here CfR in itself does not show any significant improvement in spectral emissions. It is, however, useful in reducing the signals dynamic range at the converter, but especially it is a vital enabler for DPD in that the leveling of the signal peaks allows dPd to estimate its function with much greater accuracy. The reasons behind this are discussed in later sections of this application note, but the benefits are apparent in Figure 2, which shows the results of running the previous predistortion test both with, and without CFR APP1128(v1.0) March18,2009 Www.xuinX.com XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL ntroduction ￡ⅫLNX Agilent 67: 18: 37 Oct 22, 200 Trace △M;r12,7MH HAtte 10 dB Trace Clear hrit Hax hold PAY Min hold 1V2 FC View ￡(f) 2Aw学举吗 Center 2. G+z 1的MHz #R÷B3kHz E3的kHz #ep8啊r(!1pts) Figure 2: Spectrum Analyzer Screenshot for DPD With(Yellow line) and Without CFR(Blue Line) Figure 3 shows the dependence of adjacent channel power(ACP)on PA output power both with, and without CFR and DPD. The acP is measured as defined in the 3GPP specification TS25. 141, absolute power in a 1 MHz wide band offset by 4 MHz from the carrier center. The ACP mask specification, as shown in Figure 3 as the green line, is at -13 dBm. Figure 3 indicates that this Pa could theoretically be driven to about 48 dBm. In practice though, some margin to mask should be retained to allow for gain variations and signal dynamics. Operation at 46 dBm(40 Watts) appears to be suitable. The AcP improvement of the CFR-DPD combination at this power is about 23 dB Without DPD, spectral mask compliance limits the output power to 37 dBm (5 Watts APP1128(v1.0) March18,2009 Www.xuinX.com XILINX CONFIDENTIAL- XILINX CONFIDENTIAL XILINX CONFIDENTIAL ntroduction ￡ⅫLNX Figure 3: Various Output Power Dependencies of Adjacent Channel Power Output Power Efficiency The efficiency of an individual amplifier, that is the percentage of dc power draw that appears as RF power, depends primarily on the output power It is virtually independent of the signal bandwidth and peak-to-average ratio With class-A and class-AB amplifiers, power efficiency improvements are always obtained when the amplifier can be driven to higher output powers DPD, therefore, improves the efficiency of power output in a given installation by allowing an amplifier to be driven to higher output powers while still maintaining spectral mask compliance Strictly speaking, the situation is a little more complex because the requirement would be to provide a basestation with a given maximum output power. The comparison should be between the efficiencies of the amplifier configurations that meet that requirement, with and without DPD. For a given output power, operating without DPD a different amplifier, with a much higher compression point, would be required, and this has both efficiency and component cost implications. Nonetheless, for a direct numerical evaluation, it is instructive to look at how DPD improves the efficiency of one individual amplifier Figure 4 shows the power efficiency(RF power output divided by total dc power input for the packaged amplifier) versus output power for the Pa under test APP1128(v1.0) March18,2009 Www.xuinX.com 10 【实例截图】
【核心代码】