tm4c123 datasheet.pdf

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【文件目录】

Table of Contents
Revision History ............................................................................................................................. 38
About This Document .................................................................................................................... 42
Audience .............................................................................................................................................. 42
About This Manual ................................................................................................................................ 42
Related Documents ............................................................................................................................... 42
Documentation Conventions .................................................................................................................. 43
1 Architectural Overview .......................................................................................... 45
1.1 Tiva™ C Series Overview .............................................................................................. 45
1.2 TM4C123GH6PM Microcontroller Overview .................................................................... 46
1.3 TM4C123GH6PM Microcontroller Features ..................................................................... 49
1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 49
1.3.2 On-Chip Memory ........................................................................................................... 51
1.3.3 Serial Communications Peripherals ................................................................................ 53
1.3.4 System Integration ........................................................................................................ 57
1.3.5 Advanced Motion Control ............................................................................................... 63
1.3.6 Analog .......................................................................................................................... 65
1.3.7 JTAG and ARM Serial Wire Debug ................................................................................ 67
1.3.8 Packaging and Temperature .......................................................................................... 67
1.4 TM4C123GH6PM Microcontroller Hardware Details ........................................................ 68
1.5 Kits .............................................................................................................................. 68
1.6 Support Information ....................................................................................................... 68
2 The Cortex-M4F Processor ................................................................................... 69
2.1 Block Diagram .............................................................................................................. 70
2.2 Overview ...................................................................................................................... 71
2.2.1 System-Level Interface .................................................................................................. 71
2.2.2 Integrated Configurable Debug ...................................................................................... 71
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 72
2.2.4 Cortex-M4F System Component Details ......................................................................... 72
2.3 Programming Model ...................................................................................................... 73
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 73
2.3.2 Stacks .......................................................................................................................... 74
2.3.3 Register Map ................................................................................................................ 74
2.3.4 Register Descriptions .................................................................................................... 76
2.3.5 Exceptions and Interrupts .............................................................................................. 92
2.3.6 Data Types ................................................................................................................... 92
2.4 Memory Model .............................................................................................................. 92
2.4.1 Memory Regions, Types and Attributes ........................................................................... 95
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 95
2.4.3 Behavior of Memory Accesses ....................................................................................... 95
2.4.4 Software Ordering of Memory Accesses ......................................................................... 96
2.4.5 Bit-Banding ................................................................................................................... 97
2.4.6 Data Storage ................................................................................................................ 99
2.4.7 Synchronization Primitives ........................................................................................... 100
2.5 Exception Model ......................................................................................................... 101
2.5.1 Exception States ......................................................................................................... 102
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2.5.2 Exception Types .......................................................................................................... 102
2.5.3 Exception Handlers ..................................................................................................... 106
2.5.4 Vector Table ................................................................................................................ 106
2.5.5 Exception Priorities ...................................................................................................... 107
2.5.6 Interrupt Priority Grouping ............................................................................................ 108
2.5.7 Exception Entry and Return ......................................................................................... 108
2.6 Fault Handling ............................................................................................................. 111
2.6.1 Fault Types ................................................................................................................. 112
2.6.2 Fault Escalation and Hard Faults .................................................................................. 112
2.6.3 Fault Status Registers and Fault Address Registers ...................................................... 113
2.6.4 Lockup ....................................................................................................................... 113
2.7 Power Management .................................................................................................... 114
2.7.1 Entering Sleep Modes ................................................................................................. 114
2.7.2 Wake Up from Sleep Mode .......................................................................................... 114
2.8 Instruction Set Summary .............................................................................................. 115
3 Cortex-M4 Peripherals ......................................................................................... 122
3.1 Functional Description ................................................................................................. 122
3.1.1 System Timer (SysTick) ............................................................................................... 123
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 124
3.1.3 System Control Block (SCB) ........................................................................................ 125
3.1.4 Memory Protection Unit (MPU) ..................................................................................... 125
3.1.5 Floating-Point Unit (FPU) ............................................................................................. 130
3.2 Register Map .............................................................................................................. 134
3.3 System Timer (SysTick) Register Descriptions .............................................................. 137
3.4 NVIC Register Descriptions .......................................................................................... 141
3.5 System Control Block (SCB) Register Descriptions ........................................................ 156
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 185
3.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 194
4 JTAG Interface ...................................................................................................... 200
4.1 Block Diagram ............................................................................................................ 201
4.2 Signal Description ....................................................................................................... 201
4.3 Functional Description ................................................................................................. 202
4.3.1 JTAG Interface Pins ..................................................................................................... 202
4.3.2 JTAG TAP Controller ................................................................................................... 204
4.3.3 Shift Registers ............................................................................................................ 204
4.3.4 Operational Considerations .......................................................................................... 205
4.4 Initialization and Configuration ..................................................................................... 207
4.5 Register Descriptions .................................................................................................. 208
4.5.1 Instruction Register (IR) ............................................................................................... 208
4.5.2 Data Registers ............................................................................................................ 210
5 System Control ..................................................................................................... 212
5.1 Signal Description ....................................................................................................... 212
5.2 Functional Description ................................................................................................. 212
5.2.1 Device Identification .................................................................................................... 212
5.2.2 Reset Control .............................................................................................................. 213
5.2.3 Non-Maskable Interrupt ............................................................................................... 218
5.2.4 Power Control ............................................................................................................. 218
5.2.5 Clock Control .............................................................................................................. 219
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5.2.6 System Control ........................................................................................................... 227
5.3 Initialization and Configuration ..................................................................................... 231
5.4 Register Map .............................................................................................................. 231
5.5 System Control Register Descriptions ........................................................................... 237
5.6 System Control Legacy Register Descriptions ............................................................... 424
6 System Exception Module ................................................................................... 485
6.1 Functional Description ................................................................................................. 485
6.2 Register Map .............................................................................................................. 485
6.3 Register Descriptions .................................................................................................. 485
7 Hibernation Module .............................................................................................. 493
7.1 Block Diagram ............................................................................................................ 494
7.2 Signal Description ....................................................................................................... 494
7.3 Functional Description ................................................................................................. 495
7.3.1 Register Access Timing ............................................................................................... 495
7.3.2 Hibernation Clock Source ............................................................................................ 496
7.3.3 System Implementation ............................................................................................... 497
7.3.4 Battery Management ................................................................................................... 498
7.3.5 Real-Time Clock .......................................................................................................... 499
7.3.6 Battery-Backed Memory .............................................................................................. 501
7.3.7 Power Control Using HIB ............................................................................................. 501
7.3.8 Power Control Using VDD3ON Mode ........................................................................... 501
7.3.9 Initiating Hibernate ...................................................................................................... 501
7.3.10 Waking from Hibernate ................................................................................................ 501
7.3.11 Arbitrary Power Removal ............................................................................................. 502
7.3.12 Interrupts and Status ................................................................................................... 502
7.4 Initialization and Configuration ..................................................................................... 503
7.4.1 Initialization ................................................................................................................. 503
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 504
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 504
7.4.4 External Wake-Up from Hibernation .............................................................................. 504
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 505
7.5 Register Map .............................................................................................................. 505
7.6 Register Descriptions .................................................................................................. 506
8 Internal Memory ................................................................................................... 524
8.1 Block Diagram ............................................................................................................ 524
8.2 Functional Description ................................................................................................. 525
8.2.1 SRAM ........................................................................................................................ 525
8.2.2 ROM .......................................................................................................................... 526
8.2.3 Flash Memory ............................................................................................................. 528
8.2.4 EEPROM .................................................................................................................... 534
8.3 Register Map .............................................................................................................. 540
8.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 541
8.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 559
8.6 Memory Register Descriptions (System Control Offset) .................................................. 576
9 Micro Direct Memory Access (μDMA) ................................................................ 585
9.1 Block Diagram ............................................................................................................ 586
9.2 Functional Description ................................................................................................. 586
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9.2.1 Channel Assignments .................................................................................................. 587
9.2.2 Priority ........................................................................................................................ 588
9.2.3 Arbitration Size ............................................................................................................ 588
9.2.4 Request Types ............................................................................................................ 588
9.2.5 Channel Configuration ................................................................................................. 589
9.2.6 Transfer Modes ........................................................................................................... 591
9.2.7 Transfer Size and Increment ........................................................................................ 599
9.2.8 Peripheral Interface ..................................................................................................... 599
9.2.9 Software Request ........................................................................................................ 599
9.2.10 Interrupts and Errors .................................................................................................... 600
9.3 Initialization and Configuration ..................................................................................... 600
9.3.1 Module Initialization ..................................................................................................... 600
9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 601
9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 602
9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 604
9.3.5 Configuring Channel Assignments ................................................................................ 606
9.4 Register Map .............................................................................................................. 606
9.5 μDMA Channel Control Structure ................................................................................. 608
9.6 μDMA Register Descriptions ........................................................................................ 615
10 General-Purpose Input/Outputs (GPIOs) ........................................................... 649
10.1 Signal Description ....................................................................................................... 649
10.2 Functional Description ................................................................................................. 652
10.2.1 Data Control ............................................................................................................... 653
10.2.2 Interrupt Control .......................................................................................................... 654
10.2.3 Mode Control .............................................................................................................. 655
10.2.4 Commit Control ........................................................................................................... 656
10.2.5 Pad Control ................................................................................................................. 656
10.2.6 Identification ............................................................................................................... 656
10.3 Initialization and Configuration ..................................................................................... 656
10.4 Register Map .............................................................................................................. 658
10.5 Register Descriptions .................................................................................................. 661
11 General-Purpose Timers ...................................................................................... 704
11.1 Block Diagram ............................................................................................................ 705
11.2 Signal Description ....................................................................................................... 706
11.3 Functional Description ................................................................................................. 707
11.3.1 GPTM Reset Conditions .............................................................................................. 708
11.3.2 Timer Modes ............................................................................................................... 709
11.3.3 Wait-for-Trigger Mode .................................................................................................. 718
11.3.4 Synchronizing GP Timer Blocks ................................................................................... 719
11.3.5 DMA Operation ........................................................................................................... 720
11.3.6 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 720
11.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 720
11.4 Initialization and Configuration ..................................................................................... 722
11.4.1 One-Shot/Periodic Timer Mode .................................................................................... 722
11.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 723
11.4.3 Input Edge-Count Mode ............................................................................................... 723
11.4.4 Input Edge Time Mode ................................................................................................. 724
11.4.5 PWM Mode ................................................................................................................. 724
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11.5 Register Map .............................................................................................................. 725
11.6 Register Descriptions .................................................................................................. 726
12 Watchdog Timers ................................................................................................. 774
12.1 Block Diagram ............................................................................................................ 775
12.2 Functional Description ................................................................................................. 775
12.2.1 Register Access Timing ............................................................................................... 776
12.3 Initialization and Configuration ..................................................................................... 776
12.4 Register Map .............................................................................................................. 776
12.5 Register Descriptions .................................................................................................. 777
13 Analog-to-Digital Converter (ADC) ..................................................................... 799
13.1 Block Diagram ............................................................................................................ 800
13.2 Signal Description ....................................................................................................... 801
13.3 Functional Description ................................................................................................. 802
13.3.1 Sample Sequencers .................................................................................................... 802
13.3.2 Module Control ............................................................................................................ 803
13.3.3 Hardware Sample Averaging Circuit ............................................................................. 807
13.3.4 Analog-to-Digital Converter .......................................................................................... 807
13.3.5 Differential Sampling ................................................................................................... 810
13.3.6 Internal Temperature Sensor ........................................................................................ 812
13.3.7 Digital Comparator Unit ............................................................................................... 813
13.4 Initialization and Configuration ..................................................................................... 817
13.4.1 Module Initialization ..................................................................................................... 817
13.4.2 Sample Sequencer Configuration ................................................................................. 818
13.5 Register Map .............................................................................................................. 818
13.6 Register Descriptions .................................................................................................. 820
14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 893
14.1 Block Diagram ............................................................................................................ 894
14.2 Signal Description ....................................................................................................... 894
14.3 Functional Description ................................................................................................. 895
14.3.1 Transmit/Receive Logic ............................................................................................... 895
14.3.2 Baud-Rate Generation ................................................................................................. 896
14.3.3 Data Transmission ...................................................................................................... 897
14.3.4 Serial IR (SIR) ............................................................................................................. 897
14.3.5 ISO 7816 Support ....................................................................................................... 898
14.3.6 Modem Handshake Support ......................................................................................... 899
14.3.7 9-Bit UART Mode ........................................................................................................ 900
14.3.8 FIFO Operation ........................................................................................................... 900
14.3.9 Interrupts .................................................................................................................... 900
14.3.10 Loopback Operation .................................................................................................... 901
14.3.11 DMA Operation ........................................................................................................... 902
14.4 Initialization and Configuration ..................................................................................... 902
14.5 Register Map .............................................................................................................. 903
14.6 Register Descriptions .................................................................................................. 905
15 Synchronous Serial Interface (SSI) .................................................................... 952
15.1 Block Diagram ............................................................................................................ 953
15.2 Signal Description ....................................................................................................... 953
15.3 Functional Description ................................................................................................. 954
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15.3.1 Bit Rate Generation ..................................................................................................... 954
15.3.2 FIFO Operation ........................................................................................................... 955
15.3.3 Interrupts .................................................................................................................... 955
15.3.4 Frame Formats ........................................................................................................... 956
15.3.5 DMA Operation ........................................................................................................... 964
15.4 Initialization and Configuration ..................................................................................... 965
15.5 Register Map .............................................................................................................. 967
15.6 Register Descriptions .................................................................................................. 968
16 Inter-Integrated Circuit (I2C) Interface ................................................................ 997
16.1 Block Diagram ............................................................................................................ 998
16.2 Signal Description ....................................................................................................... 998
16.3 Functional Description ................................................................................................. 999
16.3.1 I2C Bus Functional Overview ........................................................................................ 999
16.3.2 Available Speed Modes ............................................................................................. 1003
16.3.3 Interrupts .................................................................................................................. 1005
16.3.4 Loopback Operation .................................................................................................. 1006
16.3.5 Command Sequence Flow Charts .............................................................................. 1007
16.4 Initialization and Configuration .................................................................................... 1015
16.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 1015
16.4.2 Configure the I2C Master to High Speed Mode ............................................................ 1016
16.5 Register Map ............................................................................................................ 1017
16.6 Register Descriptions (I2C Master) .............................................................................. 1018
16.7 Register Descriptions (I2C Slave) ............................................................................... 1035
16.8 Register Descriptions (I2C Status and Control) ............................................................ 1045
17 Controller Area Network (CAN) Module ........................................................... 1048
17.1 Block Diagram ........................................................................................................... 1049
17.2 Signal Description ..................................................................................................... 1049
17.3 Functional Description ............................................................................................... 1050
17.3.1 Initialization ............................................................................................................... 1051
17.3.2 Operation .................................................................................................................. 1051
17.3.3 Transmitting Message Objects ................................................................................... 1052
17.3.4 Configuring a Transmit Message Object ...................................................................... 1053
17.3.5 Updating a Transmit Message Object ......................................................................... 1054
17.3.6 Accepting Received Message Objects ........................................................................ 1054
17.3.7 Receiving a Data Frame ............................................................................................ 1055
17.3.8 Receiving a Remote Frame ........................................................................................ 1055
17.3.9 Receive/Transmit Priority ........................................................................................... 1056
17.3.10 Configuring a Receive Message Object ...................................................................... 1056
17.3.11 Handling of Received Message Objects ...................................................................... 1057
17.3.12 Handling of Interrupts ................................................................................................ 1059
17.3.13 Test Mode ................................................................................................................. 1060
17.3.14 Bit Timing Configuration Error Considerations ............................................................. 1062
17.3.15 Bit Time and Bit Rate ................................................................................................. 1062
17.3.16 Calculating the Bit Timing Parameters ........................................................................ 1064
17.4 Register Map ............................................................................................................ 1067
17.5 CAN Register Descriptions ......................................................................................... 1068
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18 Universal Serial Bus (USB) Controller ............................................................. 1099
18.1 Block Diagram ........................................................................................................... 1100
18.2 Signal Description ..................................................................................................... 1100
18.3 Functional Description ............................................................................................... 1101
18.3.1 Operation as a Device ............................................................................................... 1101
18.3.2 Operation as a Host ................................................................................................... 1107
18.3.3 OTG Mode ................................................................................................................ 1110
18.3.4 DMA Operation ......................................................................................................... 1112
18.4 Initialization and Configuration .................................................................................... 1113
18.4.1 Pin Configuration ....................................................................................................... 1113
18.4.2 Endpoint Configuration .............................................................................................. 1114
18.5 Register Map ............................................................................................................ 1114
18.6 Register Descriptions ................................................................................................. 1120
19 Analog Comparators .......................................................................................... 1215
19.1 Block Diagram ........................................................................................................... 1216
19.2 Signal Description ..................................................................................................... 1216
19.3 Functional Description ............................................................................................... 1217
19.3.1 Internal Reference Programming ................................................................................ 1218
19.4 Initialization and Configuration .................................................................................... 1220
19.5 Register Map ............................................................................................................ 1220
19.6 Register Descriptions ................................................................................................. 1221
20 Pulse Width Modulator (PWM) .......................................................................... 1230
20.1 Block Diagram ........................................................................................................... 1231
20.2 Signal Description ..................................................................................................... 1233
20.3 Functional Description ............................................................................................... 1234
20.3.1 Clock Configuration ................................................................................................... 1234
20.3.2 PWM Timer ............................................................................................................... 1234
20.3.3 PWM Comparators .................................................................................................... 1234
20.3.4 PWM Signal Generator .............................................................................................. 1235
20.3.5 Dead-Band Generator ............................................................................................... 1236
20.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 1236
20.3.7 Synchronization Methods .......................................................................................... 1237
20.3.8 Fault Conditions ........................................................................................................ 1238
20.3.9 Output Control Block .................................................................................................. 1239
20.4 Initialization and Configuration .................................................................................... 1239
20.5 Register Map ............................................................................................................ 1240
20.6 Register Descriptions ................................................................................................. 1243
21 Quadrature Encoder Interface (QEI) ................................................................. 1305
21.1 Block Diagram ........................................................................................................... 1305
21.2 Signal Description ..................................................................................................... 1307
21.3 Functional Description ............................................................................................... 1308
21.4 Initialization and Configuration .................................................................................... 1310
21.5 Register Map ............................................................................................................ 1310
21.6 Register Descriptions ................................................................................................. 1311
22 Pin Diagram ........................................................................................................ 1328
23 Signal Tables ...................................................................................................... 1329
23.1 Signals by Pin Number .............................................................................................. 1330
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23.2 Signals by Signal Name ............................................................................................. 1337
23.3 Signals by Function, Except for GPIO ......................................................................... 1344
23.4 GPIO Pins and Alternate Functions ............................................................................ 1351
23.5 Possible Pin Assignments for Alternate Functions ....................................................... 1353
23.6 Connections for Unused Signals ................................................................................. 1356
24 Electrical Characteristics .................................................................................. 1358
24.1 Maximum Ratings ...................................................................................................... 1358
24.2 Operating Characteristics ........................................................................................... 1359
24.3 Recommended Operating Conditions ......................................................................... 1360
24.4 Load Conditions ........................................................................................................ 1362
24.5 JTAG and Boundary Scan .......................................................................................... 1363
24.6 Power and Brown-Out ............................................................................................... 1365
24.6.1 VDDA Levels ............................................................................................................ 1365
24.6.2 VDD Levels ............................................................................................................... 1366
24.6.3 VDDC Levels ............................................................................................................ 1367
24.6.4 VDD Glitches ............................................................................................................ 1368
24.6.5 VDD Droop Response ............................................................................................... 1368
24.7 Reset ........................................................................................................................ 1370
24.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1373
24.9 Clocks ...................................................................................................................... 1374
24.9.1 PLL Specifications ..................................................................................................... 1374
24.9.2 PIOSC Specifications ................................................................................................ 1375
24.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 1375
24.9.4 Hibernation Clock Source Specifications ..................................................................... 1375
24.9.5 Main Oscillator Specifications ..................................................................................... 1376
24.9.6 System Clock Specification with ADC Operation .......................................................... 1380
24.9.7 System Clock Specification with USB Operation .......................................................... 1380
24.10 Sleep Modes ............................................................................................................. 1381
24.11 Hibernation Module ................................................................................................... 1383
24.12 Flash Memory and EEPROM ..................................................................................... 1384
24.13 Input/Output Pin Characteristics ................................................................................. 1385
24.13.1 GPIO Module Characteristics ..................................................................................... 1385
24.13.2 Types of I/O Pins and ESD Protection ......................................................................... 1385
24.14 Analog-to-Digital Converter (ADC) .............................................................................. 1389
24.15 Synchronous Serial Interface (SSI) ............................................................................. 1392
24.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1395
24.17 Universal Serial Bus (USB) Controller ......................................................................... 1396
24.18 Analog Comparator ................................................................................................... 1397
24.19 Pulse-Width Modulator (PWM) ................................................................................... 1398
24.20 Current Consumption ................................................................................................. 1399
A Package Information .......................................................................................... 1402
A.1 Orderable Devices ..................................................................................................... 1402
A.2 Device Nomenclature ................................................................................................ 1402
A.3 Device Markings ........................................................................................................ 1403
A.4 Packaging Diagram ................................................................................................... 1404