Digital Design 5th - Morris Mano.pdf

【实例截图】

【核心代码】

Contents 
vi Contents
3 G a t e ‐ L e v e l M i n i m i z a t i o n 7 3
 3.1 Introduction 73
 3.2 The Map Method 73
 3.3 Four‐Variable K-Map 80
 3.4 Product‐of‐Sums Simplification 84
 3.5 Don’t‐Care Conditions 88
 3.6 NAND and NOR Implementation 90
 3.7 Other Two‐Level Implementations 97
 3.8 Exclusive‐OR Function 103
 3.9 Hardware Description Language 108
4 C o m b i n a t i o n a l L o g i c 125
 4.1 Introduction 125
 4.2 Combinational Circuits 125
 4.3 Analysis Procedure 126
 4.4 Design Procedure 129
 4.5 Binary Adder–Subtractor 133
 4.6 Decimal Adder 144
 4.7 Binary Multiplier 146
 4.8 Magnitude Comparator 148
 4.9 Decoders 150
 4.10 Encoders 155
 4.11 Multiplexers 158
 4.12 HDL Models of Combinational Circuits 164
5 S y n c h r o n o u s S e q u e n t i a l L o g i c 190
 5.1 Introduction 190
 5.2 Sequential Circuits 190
 5.3 Storage Elements: Latches 193
 5.4 Storage Elements: Flip‐Flops 196
 5.5 Analysis of Clocked Sequential Circuits 204
 5.6 Synthesizable HDL Models of Sequential Circuits 217
 5.7 State Reduction and Assignment 231
 5.8 Design Procedure 236
6 R e g i s t e r s a n d C o u n t e r s 255
 6.1 Registers 255
 6.2 Shift Registers 258
 6.3 Ripple Counters 266
 6.4 Synchronous Counters 271
 6.5 Other Counters 278
 6.6 HDL for Registers and Counters 283
Contents vii
7 Memory and Programmable Logic 299
 7.1 Introduction 299
 7.2 Random‐Access Memory 300
 7.3 Memory Decoding 307
 7.4 Error Detection and Correction 312
 7.5 Read‐Only Memory 315
 7.6 Programmable Logic Array 321
 7.7 Programmable Array Logic 325
 7.8 Sequential Programmable Devices 329
8 D e s i g n a t t h e R e g i s t e r
Transfer Level 351
 8.1 Introduction 351
 8.2 Register Transfer Level Notation 351
 8.3 Register Transfer Level in HDL 354
 8.4 Algorithmic State Machines (ASMs) 363
 8.5 Design Example (ASMD Chart) 371
 8.6 HDL Description of Design Example 381
 8.7 Sequential Binary Multiplier 391
 8.8 Control Logic 396
 8.9 HDL Description of Binary Multiplier 402
 8.10 Design with Multiplexers 411
 8.11 Race‐Free Design (Software Race Conditions) 422
 8.12 Latch‐Free Design (Why Waste Silicon?) 425
 8.13 Other Language Features 426
9 L a b o r a t o r y E x p e r i m e n t s
with Standard ICs and FPGAs 438
 9.1 Introduction to Experiments 438
 9.2 Experiment 1: Binary and Decimal Numbers 443
 9.3 Experiment 2: Digital Logic Gates 446
 9.4 Experiment 3: Simplification of Boolean Functions 448
 9.5 Experiment 4: Combinational Circuits 450
 9.6 Experiment 5: Code Converters 452
 9.7 Experiment 6: Design with Multiplexers 453
 9.8 Experiment 7: Adders and Subtractors 455
 9.9 Experiment 8: Flip‐Flops 457
 9.10 Experiment 9: Sequential Circuits 460
 9.11 Experiment 10: Counters 461
 9.12 Experiment 11: Shift Registers 463
 9.13 Experiment 12: Serial Addition 466
 9.14 Experiment 13: Memory Unit 467
 9.15 Experiment 14: Lamp Handball 469
viii Contents
 9.16 Experiment 15: Clock‐Pulse Generator 473
 9.17 Experiment 16: Parallel Adder and Accumulator 475
 9.18 Experiment 17: Binary Multiplier 478
 9.19 Verilog HDL Simulation Experiments
and Rapid Prototyping with FPGAs 480
1 0 S t a n d a r d G r a p h i c S y m b o l s 488
 10.1 Rectangular‐Shape Symbols 488
 10.2 Qualifying Symbols 491
 10.3 Dependency Notation 493
 10.4 Symbols for Combinational Elements 495
 10.5 Symbols for Flip‐Flops 497
 10.6 Symbols for Registers 499
 10.7 Symbols for Counters 502
 10.8 Symbol for RAM 504
Appendix 507