IBIS仿真模型的生成指南

【实例简介】
很好的一份IBIS制作指南，全英文，但是十分官方，很有指导意义。如果你是要制作IBIS模型，或者用IBIS模型进行仿真，这份文档会给你很大帮助
ADVANCED KEYWORDS AND CONSTRUCTS IBIS Open Forum IBIS Modeling Cookbook P age Figure 3. 1-Standard 3-state Buffer(Pulldown I-V Table Extraction Shown) 13 Figure 3.2-Simulation Setup for Extracting Ramp Rate Information( Rising Edge Shown).......1 8 Figure 3. 3- Fixture for Extraction of C comp information 20 Figure 3.4- Surface Plot of Buffer Capacitance versus Frcqucncy and DC Bias voltage 21 Figure 3.5- Fixture for Extraction of C comp Information 22 Figure 4.1- Device with Independent Input, Output and Power Supply Ports 24 Figure 4.2-Device with Ports Using Common Ground Figure4.3- Input Port with Locally Generated Reference…….……….……….…….25 Figure 4.4- Single-ended Receiver.... ··· Figure4.5- Fully Differential Receiver…… 27 Figure 4.6-Half-differential Receiver 27 Figure 4.7-Pseudo-differential Receiver 28 Figure 4.8- Singlc-cnded Driver. 29 Figure 4.9- Fully differential driver with external load 29 Figure 4.10-Half-differential Driver with External load 30 Figure 4.11- Pseudo-differential Driver Example Figure 4.12- Block Diagram of a Fully Differential Model using IBis Version 3.2 Constructs Figure 4.13-I-V Table Extraction Fixture for a Differential Buffer. ..................................................................35 Figure 4.14- Surface Plots of Raw Data from I-V Sweep of Differential Buffer 35 Figure 4.15-I-V Curves of Common Mode Characteristics of Differential Buffer .36 Figure 4.16-Differential Current Plot of Output Current versus P and n Voltage 36 Figure 4.17- Plots of Various Vds Values for a [Scrics MOSFET] Buffer ∴.38 Figure 4.18-V-T Table Extraction Fixture for a Differential Buffer 40 Figure4.l9- Fixture for extraction of differential buffer c_comp.……… 42 Figure 4.20- Surface Plot of Differential Capacitance versus Frequency and DC Bias Voltage .:··· 43 Figure5.l- Conceptual Diagram of Model Keyword Structure…….….….…….…….……149 Figure 5.2- Model Keyword Structure with Added Diode Detail.... Figure 5.3-Raw I-V and Final [GNd Clamp] Data Graphs Figure 5.4- Graph of [GND Clamp I-V Table Data 52 Figure 5. 5-Raw I-V and Final [PowEr Clamp] Data Graphs Figure5.6- Graph of[ POWER Clamp] V Table Data after Clamp Subtraction………….….…….54 Figure 5.7-Graph of [Pulldown] I-V Table Data, after Clamp Subtraction 55 Figure 5.8- Graph of[ Pullup] I-V Table Data after Clamp Subtraction.…….….……….55 Figure 5.9- Diagram of Resistive Load for Rising Waveform Figure 5.10-V- T Table Loading Example………….… 61 Figure 5. 11-V-T Table Loading Example, Simplified 62 Figure 5. 12-[Pullup] i-V Table Data with Load Line Intercept 63 Figure 5. 13- Data Point Selection Examplc Figure 5.14- Diagram of T/O Buffer with Internal Termination 65 Figure 5.15- Graph of Power and ground Clamp I-V Data for Ground-connected Termination ............66 Figure 5. 16-Graph of I-V Data for Ground-connected Termination in High-Impedance State 67 Figure 5.17-Graph of Power and Ground clamp l-y data for Vcc-connected Termination.......... 68 Figure5.19- Block Diagram of a Two- Tap Differential Buffer Featuring Pre- Emphas………….69 Figure 5.18-Graph of I-V Data for Vcc Terminated Buffer in High-Impedance State 75 Figure 5.20-Output of a Scheduled Driver Configured as an Inverter............76 Figure 5.21-Component Diagram Showing Buffer and Supply buses 78 Figure 5.22-Conncction of Single-ended and Series [Model]s 80 Page 4 IBIS Modeling cookbook IBIS Open Forum Table 3.1- Recommended Load Circuits and waveforms for v-t Data Extraction Table 5.1- IBIS File Header Keywords.….… 45 Table 5.2-ibis Component and pin Information 46 Table 5.3-BIS [Model] Subparameters 47 Table 5.4-IBIS [Model] Temperature and Voltage Keywords 48 Table5.5-[ Model]- V Table Keywords…….….….….….….….….….….….…..…....50 Table 5.6-Summary of recommended I-V Table Sweep Ranges Table 5.7-Poorly Extrapolated [GNd Clamp] table, Typical Corner .56 Table 5.8-[GND Clamp] table, Typical Corner, with Improved Extrapolation Table 5.9-[Ramp] and Waveform Table Keywords Table 5.10-I-V table Keywords and Buffer Types · 58 Table 5. 11-V-T Fixtures and Buffer Types 59 Table 5.12-v-t table loading recommendations 9 Table 5.13 -Example V-T Table Data for Rising Waveform. IBIS Open Forum IBIS Modeling Cookbook P age This document describes the recommended steps for producing IBIS files for digital integrated circuits(ICs) IBIS (officially, Ela standard 656-A-1999, EC 62014-1) stands for 1/0 Buffer Information Specification. IBIS models provide a standardized way of representing the clectrical characteristics of a digital IC's pins (input output,I/0 buffers and the like) behaviorally, i.e., without revealing the underlying circuits structure or process nformation Note that the basic behavioral information in an IBIS model can be obtained either by direct measurement of the component or transistor level simulation of the components buffers. This cookbook describes both methods though with a strong emphasis on data extraction through simulation. The cookbook is targeted toward generating models for CMOS, Gtl and bipolar parts, and applies to models generated for IBIS version 4.0 and earlier. For the most recent version of the specification and other Ibis documents, visit the ibis web page(see the scction) The intended audience of this document is those responsible for performing the measurements or simulations to gather I/O buffer data, as well as those responsible for actual IBIS model creation. Persons involved in SI or system level PC board simulations using IBis files may also benefit by reading this document. Some familiarity with behavioral modeling of l/o buffers and analog simulation is assumed Finally, this document does not address every keyword or feature of the IBIS specification and should not be considered a substitute for the specification itself. Readers are strongly encouraged to study closely the details of the IBIs specification An IBis file contains, in a human readable ascll format, the data required to model behaviorally a component's input, output and l o buffers. Specifically the data in an ibis file is used to construct a buffer fundamental information needed to perform these simulations is the buffer's I-V(current versus voltage)ald a model useful for performing signal integrity(SD) simulations and timing analysis of printed circuit boards. TI switching(output voltage versus time) characteristics. Please note that the IBIS specification does not define an executable simulation model-it is a standard for the formatting and transfer of data. as such the specification defines what the information included in an iBiS file represents and how it is to be gathered. It does not specify what an analog simulation application does with the data IBIS models are component-centric. That is, an IBiS file allows one to model an entire component, not just a particular buffer. Therefore, in addition to the clectrical characteristics of a component's buffers, an IBIS file includes the components pin-to-buffer mapping, and the electrical parameters of the components package The buffer's output I-V characteristics when the output is in the logic low state mation In general, an output or 1o buffer is characterized behaviorally using the following info The buffer's output I-V characteristics when the output is in the logic high state The buffer's output I-V characteristics when the output is forced below ground and above the power supply rail(referred to as its "beyond the rail"characteristics The time it takes a buffer's output to switch logic states (i.e, from low to high and high to low) The buffers capacitance For an input buffer the required information reduces to The buffer's I-V characteristics (including its "beyond the rail characteristics) The buffer's capacitance Page 6 IBIS Modeling cookbook IBIS Open Forum The above information is included in an IBiS file using"keywords". a keyword is a word or phrase surrounded by square brackets. Keywords are followed by either specific parameters or tables of data. For instance, the Model] keyword would be used to encapsulate the I-V and V-T tables, plus other data, for an individual single ended i/o buffer. Some keywords are required but most are optional. At a minimum a valid ibis file contains the following data and keywords: 1. Information regarding the file itself and name of the component being modeled. This information is contained under the keywords [ibis Ver], [File Name], [File Rev], [Component] and [Manufacturer 2. Information about the package's electrical characteristics and the pin to buffer model mapping(i. e, which pins are connected to which buffer models). This information is included under the [Package and [pin] keywords 3. The data required to model each unique input, output and i/o buffer design on the component. The Model] keyword introduces the data set for each unique buffer. As described above, buffers are characterized by their i-v behaviors and switching characteristics This information is included using the keywords [Pullup, [pulldown], [GNd Clamp], [POWER Clamp] and [ramp]. In addition, the required parameters to the [model] keyword specify a model's type(Input, Output, I O, Open drain, etc. )and its input or output capacitance The details of constructing an ibis model from data are included in later in this document There arc five basic steps to creating an IBis model of a component 1. Perform the pre-modeling activities. These include deciding on the models complexity, determining the voltage, temperature and process limits over which the IC operates and the buffer model will be characterized, and obtaining the component related (electrical characteristics and and pin-out)and information about the component see the chapter titled 2. Obtain the electrical (I-V and switching response) data for output or 1/O buffers either by direct measurement or by simulation. See the chapter entitled This chapter may also be used by those who are doing the simulations required to gather the data but not actually creating the IBIS file 3. Format the data into an IBIS file. Scc the chapter titled 4. Check the file using ibisChK4. If the model is generated from simulation data, validate the model by comparing the results from the original analog(transistor level)model against the results of a behavioral lator that he ibis file as input data. See the chapter titled 5. When the actual silicon is available(or if the model is from measured data ), compare the IBis model data to the measured data. See the chapter titled The rest of this cookbook documents these steps in detail. IBIS Open Forum IBIS Modeling Cookbook Page 7 Before one creates an lO buffer model there are several basic questions that must be answered regarding the models complexity, operational limits, and use requirements. Answering these questions requires not only knowledge of the buffers physical construction, but also knowledge of the final application in which the IC will be used, and any specific requirement the model users may place on the model. These questions cannot be answered by the model creator alone; they generally require the involvement of both the buffer designer and members of the team responsible for insuring that the io buffers are useable in a system environment This team is referred to as the interconnect simulation team. Together, the model creator and interconnect simulation team must determine the following Model Version and Complexity Spccification Model versus Part Mode Fast and Slow Corner Model limits Inclusion of sso effects Based on the characteristics and construction of the yo buffer itself, and the model users simulator capability you must decide what IBIS version of the model is most appropriate. Different IBIS versions, as denoted by the [IBIS Ver] keyword, support different features. Additionally, the checking rules used by IBISCHK4 change slightly with cach version. In gencral, models should use the highest [ibis ver] version number supported by IBISCHK 4 and by their simulation tools(see ) Similarly, following good engineering practice, use the simplest model that will suffice A version 1. 1 model describes a buffer using a low state and high state I-V table, along with a linear ramp that describes how fast the buffer switches between states. For standard Cmos buffers with a single stage push-pull or open-drain outputs, a version 2. 1 model is the recommended minimum. IBIS version 2. 1 adds support for tables of V-t data, in addition to support for ECL and dual-supply buffers, ground bounce from shared power rails, differential I/O buffers termination components and controlled rise-time buffers. A version 2.1 or above model will be required if the i/o buffer has any of the following characteristics Multiple supply rails-A version 2. 1(or higher ) model is required if the buffer contains diode effects from parasitic diodes or electrostatic discharge(esd)diodes- which are referenced to a different power rail than the pullup or pulldown transistors, or if the i/O uses more than one supply Non-Lincar Output Switching Waveform- A version 2. 1(or higher) model is required if the 1/0 buffer's output voltage versus time behavior (its v-t behavior) when switching low-to-high or high-to low cannot be accurately described using a linear ramp rate value. This is the case for gtl technology or for any buffer that uses"graduated turn on" type technology perform ground bounce simulations by connecting several buffers together on a common supply rai o In addition, a version 2. 1 model description is required if the model maker wishes to enable the user See the [Pin mapping] keyword description below IBIS version 3.2 adds support for an electrical board description format, multi-staged buffers or buffers that may use multiple I-V tables and diode transient times, among other features. IBIS version 4.0 extends the maximum number of points permitted in V-T tables, supports the inclusion of independent validation data tables and adds more parameters for expressing"databook"criteria for evaluating buffer performance Page 8 IBIS Modeling cookbook IBIS Open Forum A model can be made to represent a particular existing component or can be made as a representative encapsulation of the limits of the specification for a class of components. Making a model appropriate for a specification versus a particular part or design is a major factor in determining if and how much guard-banding or de-rating a model requires. Generally, a"spec model "is based on an existing part, with the strength and edge rate of the model is adjusted to meet the best and worst case parameters of a particular specification. For example, a gtl buffer model for a particular processor may give a worst case Vol of 0. 4V at 36 mA However, if the gtl specification allows for a worst case vol of 0.6 V at 36 ma the models pulldown table may be adjusted (or de-rated) to describe the specification and not just the behavior of an individual part The Ibis format provides for minimum, typical and maximum corner data within each individual model Further, additional variations can be associated through keywords such as [model Selector](see below ) The model corners are generally determined by the environmental (temperature and power supply conditions under which the silicon is expected to operate and the silicon process limits. Note that the definitions for"typical minimum"and"maximum"are not defined by the IBIs specification. Generally, however, common usage associates the"minimum?"corner with the weakest drive strength and or slowest edge rate, while the maximum"corner is associated with the strongest drive and/or fastest edge rate The interconnect team or project must supply the model developer with the environmental and silicon process conditions that define the corners of the model for proper data extraction Closely related to the discussion on model limits is the decision on how to include simultancous switching output(SSO)effects(sometimes called simultaneous switching noise). SSO effects can be included explicitly in a model by measuring the I-V and edge rate characteristics under SSO conditions. For example, a buffer's I-V characteristic can be measured with all the adjacent buffers turned on and sinking current, or the buffers edge rate may be measured while adjacent buffers are also switching. Alternatively, a model that represents a single buffer in isolation may be created. Several such buffers may then be connected to a common power or ground rail via the [Pin mapping] keyword. The former method (including SSO effects in the I-V and V-t tables )has the advantage that the resulting model is straightforward to verify and less dependent on any particular simulator's capability. Note however, the [Pin Mapping] keyword method also adds data to enable explicit ground bounce simulations and device-specific what if"scenarios Note that the information provided under IBis version 4.0 and earlier versions only describes the output behavior of buffers under loaded conditions. Therefore, SSo simulations will only be based on the behavior at the pad and not upon information extracted about the current profile of the supplies as the buffer switches Different distributions of internal buffer current may result in the same behavior at the pad. different simulation tools may therefore make radically different assumptions regarding Sso behavior for the same iBis data Check with your simulation tool vendor for details on their specific assumptions and ibIs Sso simulation algorithms IBIS Open Forum IBIS Modeling Cookbook P age Once the above decisions have been made, the model maker can begin acquiring the specific information needed to generate the Ibis model for the component. Some of this information is specific to the component as a whole and goes directly into the IBiS file itself, while some items are needed to perform the required simulations. In general, the model maker will need the following IBIS Specification A squIre read and become familiar with the IBIS specification Buffer schematics Acquire a schematic of each of the different types of input, output, I/O etc. buffers on the component. If possible, use the same schematic that the silicon designers use for simulating buffer output timings. Make sure that the schematic includes Esd diodes (if present in the design) and a representation of the power distribution network of the package From these schematics, determine the type of each buffer structure (standard CMOs totem pole, open-drain, ctc. on the component Clamp diode and Pullup references Determine if the buffer uses different voltage references(power and/or ground supply rails) for the clamp diodes than those used for the pullup or pulldown transistors. This may apply for components that are designed for use in mixed 3. 3 V/5 V systems Packaging Information Find out in what packages the component is offered. A scparate IBIS model is required for each package type. Acquire a pinout list of the component (pin name to signal name mapping)and determine the pin name to buffer type mapping Packaging Electricals Acquire the electrical characteristics (inductance capacitance and resistanceof the components package for each pin to buffer connection(package stub). This becomes theR pin, L pin and c pin parameters of the [Pin] keyword or ther pkg, L pkg and C pkg of the 「 Package] keyword Signal Information Determine which signals can be ignored for digital component modeling purposes. For example, purely analog pins cannot be modeled using IBis 4.0, while test pads or static control signals may not need an IBIS model. These may be listed as NC in the [Pin] list Die Capacitance Obtain the capacitance of each pad (the C comp parameter). This is the capacitance seen when looking from the into the buffer for a fully placed and routed buffer design ( note that the phrases"Cdie”or‘ die capacitance” may be used in other industry contexts to refer to the capacitance of the entire component as measured between the power and ground supply rails Vinl and Vinh Parameters Determine the input logic thresholds of any input or i/o buffers. Vinl is the maximum pad or pin voltage at which the receiving buffers logical state would still be a logical‘low”or“0.” Vinh is the minimul Page 10 IBIS Modeling cookbook IBIS Open Forum 【实例截图】
【核心代码】