TSMC0.35um工艺库说明文件

【实例简介】
该文档对TSMC0.35um工艺库进行了详细的说明
tsmc Taiwan Semiconductor Manufacturing Co, LTD Document no TA-1095-6004(T-035LOSP-001) age 2 1 INTRODUCTION This document is intended as a design reference guide for those who use the TSMc 0.35um LOGIC polycide SPTM process in 3. 3V application. The V2. 1 spice model is generated based on volume production silicon In section 2, the testkey, SPICE Simulators are introduced In section 3 the mos models of bsim3v3 are listed In section 4. the 3. 3V mos models for esd device are listed In section 5, the bipolar model for P+/NW/Psub vertical bipolar device is listed In section 6. the diode models for p+/nW. n+/pw nwpw devices are listed In section 7. the data of resistors are included. In section 8, the comparison on model simulation results and wafer data are shown In section 9, the history of this document is listed For information regarding the process flow, design rule pCm spec, please refer to TSMC's documents PROCESS FLOW: DOC. TA-1095-2001 DESIGN RULE: DoC. TA-1095-4002 PCM SPEC Doc.TA-1095-3110 The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC tsmc Taiwan Semiconductor Manufacturing Co, LTD Documen TA-1095-6004(T-035LOSP-001) age 2 EXTRACTION AND SIMULATION TOOL The SPiCe models are measured and extracted from testkey PCm3 8 CADENCE Spectre (V4.4.1),Star-HSPICE (H97.2)are used to verify Qa the BSIM3v3 model Accuracy Qa on other simulators are not guaranteed SPICE model release notes for h97.2.h97. 4 and h98.2 (1)New parameter " CALCACM"is added in the H98.2 In h97.2 h97 4. the default values of as/ad and PS/pd are zero when bsim3v3. 1 model with ACM=12 is used. This results in zero junction capacitance and incorrect junction leakage current, if AS/AD and PS/PD are not specified in the netlist. In H98.2, with CALCACM >0, the default calculation of AS/ AD and PS/PD will be calculated using HDIF if AS/AD and PS/PD are not specified in the netlist. However with CalCaCm=0, the default is zero for as/ad and PS/pd 3. MOS MODEL 3.1 COMPATIBILITY In h97.2 and H97. 4. if users choose to use acm to model the source/drain resistance and capacitance, users must specify AS, AD, Ps, PD in the netlist to avoid zero junction capacitance and to obtain correct junction leakage current. Please refer to the Cadence Spectre and star- HSPICE manuals for details on AS, AD, PS, PD. Temperature coefficients are also included in this model it is valid from 25 to 125. Those values are listed in model card Model usage guideline: The normal mos device models with model name nch. x(nch x)and pch.x(pch x)are valid for devices with length: 20-0.35 um width: 200-04um. Using these models for devices out of above valid-ranges may invoke large simulation error Bias range for these models: Vgs: 0-3.3V, ds 0-3. V, Vbs 0-33V The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC tsmc Taiwan Semiconductor Manufacturing Co, LTD Document no TA-1095-6004(T-035LOSP-001) age 3.2 FLEXIBILITY OF MODEL AND CORNER MODEL Multiple-device models are described as follows pe There are 12 models for each ofn PMOS 20 devices for N, P-MOS of different L, w sizes were used for model fitting. The device sizes (in the parentheses) and the valid-ranges for each model are shown in the map below: W几L 20020 20/20 12/20 0.8/2004/20 (200/20) (20/20) (1.2/20) (0.8/20) (0.4/20) n,pch.10 n, pch. n,pch.4 n,pch.7 L200/1.2 -20/1.2 2/1.2-0.8/1.20.4/1.2 (200/1.2) 20/1.2 1.2/1.2)(0.8/1.2) (0.4/1.2) n, p n,pch. 2 n, pch.5 n, pch. 8 200/0.8 200.8-1.2/0.80.8/0.8 -0.40.8 (2000.8 200.8)(1.2/0.8) (08/0.8) (0.4/0.8) n,pch. 12 n,pch. 3 n, pch. 6 n, pch. 9 200/0.35 20/0.35 1.2/0.35 0.8/0.35 0.40.35 ↓(p:200/0.35) (200.35)(1.20.35) (0.8/0.35 (0.40.35 (n:1000.35) Notes: I The model names with nch. x and pch. x are for HSPICE; and with nch x and pch x are for SPECTRE 2. All the above model libraries are stored in a 31/2 inch floppy disk The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC tsmc Taiwan Semiconductor Manufacturing Co, LTD Document no TA-1095-6004(T-035LOSP-001) age 5 Corner model table The skew parameters are listed below for corner-case simulation. Users can change (ex: TOX) or add (ex DVTN, DVTP)these parameters in the model file to generate the worst case simulation The skewed parameters of worst cases are listed below: unit TT FF SE NMOS TOX 7.5E-9 8.0F-9 7.0E-9 75E-9 7.5F9 PMOS TOX n 7.7E-9 8.2E-9 7.2F9 77E-97.7F-9 NMOS DXI 0.0 4E-8 4E-8 0.0 0.0 PMOS DXL 0.0 4E-8 4E-8 0.0 0.0 NMOS DXW m 0.0 6E-8 6E8 0.0 0.0 PMOS DXW 0.0 6E-8 6E-8 0.0 0.0 NMOS DVTN 0.0 0.1 0.1 0.1 0.1 PMOS DVTP 0.0 0.1 0.1 0.1 0.1 NMOS CJ F/mP1.0189E31.1208E391704E411208E39.1704E4 PMOS CJ F/m21.4168E-31.585E-31.2751E31.2751E-31.585E-3 MOS CSWF/m3058-103.364E-102752E-103.364E-102752E-10 PMOS CJSW Fm4.173E-104.591E-103756E-103.756E-104.591E-10 NMOS CJSWGF/m1.524E-101.677E-101.372E-101.677E-101.372E-10 PMOS CJSWG F/1.013E-101.5E-109.119-119.19E-111.5E-10 NMOS CGDO 上m1,960E-102.156E-101.764E-101.960E-101.960E-10 PMOS CGDO F/m2.307E-102538E-12.077E-102.307E-102.307E-10 NMOS CGSO上/m1,960E02,156E-101764E-01.960E-101.960E10 PMOS CGSO上2.307E-102538-102077E-102.307E-102307E-10 (1)Using corner model, you can add these skew parameters directly into typical model(e.g. like TOX, XL, XW, DVTON, DVTP, CJ, CJSW, CJSWG, CGDO, CGSO) (2) To generate the worst case, you can add or replace those parameters in the typical model, c g add XL (worst)=XL(typical)+DXL (skew) similarly for: DXL, DXW, DVTN, DVTP (3) The worst case values for CJ and CjSW are based on the assumption of 10% variation in the process variation ofp+, N+ and well implantation (4)All the corner model files are stored in the 3"1/2 inch floppy disk The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC tsmc Taiwan Semiconductor Manufacturing Co, LTD Document no TA-1095-6004(T-035LOSP-001) age 3.3 MODEL PARAMETERS FOR BSIM3V3 Parameters Description LEVEL In Spectre set level l l and level=49 in Star-HSPICE for BSIM3v3 model TNOM Parameters measurement temperature LMAX Maximum channel length LMIN Minimum channel length WMAX Maximum channel width WMIN Minimum channel width binunit Bin unit scale selector VTHO Threshold voltage at Vbs =0 for large L K1 First order body-effect coefficient K2 Second order body-effect coefficient K3 Narrow width coefficient K3B Body-effect coefficient of K3 W Narrow width coefficient NCH Channel doping concentration NLX Lateral non-uniform doping parameter XT Doping depth VBX Vbs at which the depletion region width equals xt VBI Substrate junction build-in potential VBM Maximum applied body bias in vth calculation DVTO First coefficient of short-channel effects on Vth DVTI Second coefficient of short-channel effects on vth DVT2 Body-bias coefficient of short-channel effects on Vth DVTOW First coefficient of narrow width effects on vth for small channel length DVTIW Second coefficient of narrow width effects on vth for small channel length DVT2W Body-bias coefficient of narrow width effect for small channel length AO Bulk charge effect coefficient for channel length Al First non-saturation coefficient parameter a2 Second non-saturation coefficient parameter The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC tsmc Taiwan Semiconductor Manufacturing Co, LTD Document no TA-1095-6004(T-035LOSP-001) age 7 NSUB Substrate doping concentration NGATE Poly-gate doping concentration Source/drain junction depth LINT Length offset fitting parameter from I-V without bias WINT Width offset fitting parameter from I-v without bias WL Coefficient of length dependence for width offset WLN Power of length dependence for width offset WW Coefficient of width dependence for width offset WWN Power of width dependence for width offset Coefficient of length dependence for length offset LLN Power of length dependence for length offset Coefficient of width dependence for length offset LWN Power of width dependence for length offset Coefficient of length and width cross term for length offset XL the masking and etching effects of channel length XW the masking and etching effects of channel width DWG Coefficient of Weff's gate dependence DWB Coefficient of Weff's substrate body bias dependence TOX Gate oxide thickness RDSW Width dependence of drain-source resistance PRWB Body effect coefficient of RDs w PRWG Gate bias effect coefficient ofrRDSw Mobility at TEMP- tNOM VSAT Saturation velocity at TEMP=tNOM UA First-order mobility degradation coefficient UB Second-order mobility degradation coefficient Body-effect of mobility degradation coefficient AGS Gate bias coefficient of bulk BO Bulk charge effect coefficient for channel width B Bulk charge effect width offset KETA Body-bias coefficient of bulk charge effect MOBMOd Mobility model selector The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC tsmc Taiwan Semiconductor Manufacturing Co, LTD Document no TA-1095-6004(T-035LOSP-001) age droUt L dependence coefficient of Dibl correction parameter in rout ALPha The first parameter of impact ionization current BETA The second parameter of impact ionization current DELTA Effective Vds parameter EM Saturation field PCLM Channel length modulation coefficient PDIBLCl First output resistance DIBl effect correction parameter PDIBLC2 Second output resistance dibL effect correction parameter Pdiblcb Body-effect coefficient of DIBL correction parameter PSCBEl First substrate current body -effect parameter PSCBE2 Second substrate current body-effect parameter PAG Gate dependence of early voltage CDSC Source/drain and channel coupling capacitance CDSCB Body-bias sensitivity of Cdsc CDSCD Drain-bias sensitivity of CDSC nfactoR Subthreshold swing coefficient CIT Interface trap capacitance VOFF Offset voltage in the subthreshold region at large W and L DSUB DIBL coefficient exponent in subthreshold region ETAO DIBL coefficient in subthreshold region ETAB Body-bias coefficient for the subthreshold dibl effect Source drain junction saturation current per unit area Sw Sidewall Source drain junction saturation current Zero-bias area junction capacitance CJSW Zero-bias sidewall junction capacitance by FOX side CJSWG Zero-bias sidewall junction capacitance by poly side PB P/N junction potential PBSW P/N sidewall junction potential by FOX side PBSWG P/N Sidewall junction potential by POLY Side MJ Area junction grading coefficient MJSW Sidewall junction grading coefficient by FOX side MJSWG Sidewall junction grading coefficient by PolY Side The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC tsmc Taiwan Semiconductor Manufacturing Co, LTD Document no TA-1095-6004(T-035LOSP-001) age CDO Gate-drain overlap capacitance CGSO Gate-source overlap capacitance CBO Gate-bulk overlap capacitance DLC Length offset fitting parameter from C-V DWC Width offset fitting parameter from C-V CAPMOD Intrinsic charge model NOSMod Flag for NQs model XPART Channel charge partitioning rate flag CF Fringing field capacitance ELM Elmore constant of the channel TLEV DC temperature selector TLEVC aC temperature selector TNOM Temperature at which parameters are extracted KTI Tempcrature coefficient for threshold voltage KTIL Channel length dependence of the temperature coefficient for threshold voltage KT2 Body-bias coefficient of Vth temperature effect At Temperature coefficient for VSAT UAl Temperature coefficient for UA UB1 Temperature coefficient for UB UC1 Temperature coefficient for UC UTE Mobility temperature exponent PRT Temperature coefficient for RDSw CTA Junction capacitance temperature coefficient CTP Sidewall junction capacitance temperature coefficient PTA Junction potential temperature coefficient PTP Junction sidewall potential temperature coefficient CALCACM Flag for AS/AD and PS/PD calculation from HDIF(H98.2 only Note: Most of the parameters have root, W-, L, and P-(W,L-product )terms, e.g. vtho (root), wvtho (width sensitively). LVtho (length sensitively). and PVthO (WL-product sensitively). For more detailed information about these parameters pleasc refer to Cadence Spectre(v4.4.1), Avant Star-HSPICE and U C. Berkeley BSIM3v3 manual The information contained herein is the exclusive property of TSMC and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of TSMC 【实例截图】
【核心代码】