实例介绍
以verilog写的FPGA 18B20驱动
module ds18b20_ctr(
input clk,
input rst_n,
inout io_signel
) /*synthesis noprune*/;
input clk,
input rst_n,
inout io_signel
) /*synthesis noprune*/;
// wire/*synthesis keep*/
// reg/*synthesis preserve*/
// reg/*synthesis noprune*/
// reg/*synthesis attribute*/
// reg/*synthesis preserve*/
// reg/*synthesis noprune*/
// reg/*synthesis attribute*/
localparam FRE_HZ = 50_000_000;
localparam M_RESET_WAIT = 0.001_000*FRE_HZ;
localparam M_FREE_WAIT = 0.000_060*FRE_HZ;
localparam SEC_WAIT = 1*FRE_HZ;
localparam ACK_WAIT = 0.000_240*FRE_HZ;
localparam FREE_WAIT = 0.000_240*FRE_HZ;
localparam M_RESET_WAIT = 0.001_000*FRE_HZ;
localparam M_FREE_WAIT = 0.000_060*FRE_HZ;
localparam SEC_WAIT = 1*FRE_HZ;
localparam ACK_WAIT = 0.000_240*FRE_HZ;
localparam FREE_WAIT = 0.000_240*FRE_HZ;
localparam M_WL_WAIT = 0.000_013*FRE_HZ;
localparam M_WD_WAIT = 0.000_040*FRE_HZ;
localparam M_WZ_WAIT = 0.000_001*FRE_HZ;
localparam M_WD_WAIT = 0.000_040*FRE_HZ;
localparam M_WZ_WAIT = 0.000_001*FRE_HZ;
localparam N_CH_WAIT = 0.800_000*FRE_HZ;
localparam M_RL_WAIT = 0.000_002*FRE_HZ;
localparam M_RZ_WAIT = 0.000_010*FRE_HZ;
localparam M_RR_WAIT = 0.000_045*FRE_HZ;
localparam M_RZ_WAIT = 0.000_010*FRE_HZ;
localparam M_RR_WAIT = 0.000_045*FRE_HZ;
localparam M_DSB_IDLE = 8'd0;
localparam M_DSB_RESET = 8'd1;
localparam M_DSB_RFEE = 8'd2;
localparam S_DSB_ACK = 8'd3;
localparam s_DSB_FRE = 8'd4;
localparam M_DSB_RESET = 8'd1;
localparam M_DSB_RFEE = 8'd2;
localparam S_DSB_ACK = 8'd3;
localparam s_DSB_FRE = 8'd4;
localparam M_DSB_WL_0 = 8'd5;
localparam M_DSB_WD_0 = 8'd6;
localparam M_DSB_Wz_0 = 8'd7;
localparam M_DSB_WL_1 = 8'd8;
localparam M_DSB_WD_1 = 8'd9;
localparam M_DSB_Wz_1 = 8'd10;
localparam M_DSB_WL_2 = 8'd11;
localparam M_DSB_WD_2 = 8'd12;
localparam M_DSB_Wz_2 = 8'd13;
localparam M_DSB_WL_3 = 8'd14;
localparam M_DSB_WD_3 = 8'd15;
localparam M_DSB_Wz_3 = 8'd16;
localparam M_DSB_WL_4 = 8'd17;
localparam M_DSB_WD_4 = 8'd18;
localparam M_DSB_Wz_4 = 8'd19;
localparam M_DSB_WL_5 = 8'd20;
localparam M_DSB_WD_5 = 8'd21;
localparam M_DSB_Wz_5 = 8'd22;
localparam M_DSB_WL_6 = 8'd23;
localparam M_DSB_WD_6 = 8'd24;
localparam M_DSB_Wz_6 = 8'd25;
localparam M_DSB_WL_7 = 8'd26;
localparam M_DSB_WD_7 = 8'd27;
localparam M_DSB_Wz_7 = 8'd28;
localparam M_DSB_WL_8 = 8'd29;
localparam M_DSB_WD_8 = 8'd30;
localparam M_DSB_Wz_8 = 8'd31;
localparam M_DSB_WL_9 = 8'd32;
localparam M_DSB_WD_9 = 8'd33;
localparam M_DSB_Wz_9 = 8'd34;
localparam M_DSB_WL_10 = 8'd35;
localparam M_DSB_WD_10 = 8'd36;
localparam M_DSB_Wz_10 = 8'd37;
localparam M_DSB_WL_11 = 8'd38;
localparam M_DSB_WD_11 = 8'd39;
localparam M_DSB_Wz_11 = 8'd40;
localparam M_DSB_WL_12 = 8'd41;
localparam M_DSB_WD_12 = 8'd42;
localparam M_DSB_Wz_12 = 8'd43;
localparam M_DSB_WL_13 = 8'd44;
localparam M_DSB_WD_13 = 8'd45;
localparam M_DSB_Wz_13 = 8'd46;
localparam M_DSB_WL_14 = 8'd47;
localparam M_DSB_WD_14 = 8'd48;
localparam M_DSB_Wz_14 = 8'd49;
localparam M_DSB_WL_15 = 8'd50;
localparam M_DSB_WD_15 = 8'd51;
localparam M_DSB_Wz_15 = 8'd52;
localparam M_DSB_WE = 8'd53;
localparam M_DSB_WD_0 = 8'd6;
localparam M_DSB_Wz_0 = 8'd7;
localparam M_DSB_WL_1 = 8'd8;
localparam M_DSB_WD_1 = 8'd9;
localparam M_DSB_Wz_1 = 8'd10;
localparam M_DSB_WL_2 = 8'd11;
localparam M_DSB_WD_2 = 8'd12;
localparam M_DSB_Wz_2 = 8'd13;
localparam M_DSB_WL_3 = 8'd14;
localparam M_DSB_WD_3 = 8'd15;
localparam M_DSB_Wz_3 = 8'd16;
localparam M_DSB_WL_4 = 8'd17;
localparam M_DSB_WD_4 = 8'd18;
localparam M_DSB_Wz_4 = 8'd19;
localparam M_DSB_WL_5 = 8'd20;
localparam M_DSB_WD_5 = 8'd21;
localparam M_DSB_Wz_5 = 8'd22;
localparam M_DSB_WL_6 = 8'd23;
localparam M_DSB_WD_6 = 8'd24;
localparam M_DSB_Wz_6 = 8'd25;
localparam M_DSB_WL_7 = 8'd26;
localparam M_DSB_WD_7 = 8'd27;
localparam M_DSB_Wz_7 = 8'd28;
localparam M_DSB_WL_8 = 8'd29;
localparam M_DSB_WD_8 = 8'd30;
localparam M_DSB_Wz_8 = 8'd31;
localparam M_DSB_WL_9 = 8'd32;
localparam M_DSB_WD_9 = 8'd33;
localparam M_DSB_Wz_9 = 8'd34;
localparam M_DSB_WL_10 = 8'd35;
localparam M_DSB_WD_10 = 8'd36;
localparam M_DSB_Wz_10 = 8'd37;
localparam M_DSB_WL_11 = 8'd38;
localparam M_DSB_WD_11 = 8'd39;
localparam M_DSB_Wz_11 = 8'd40;
localparam M_DSB_WL_12 = 8'd41;
localparam M_DSB_WD_12 = 8'd42;
localparam M_DSB_Wz_12 = 8'd43;
localparam M_DSB_WL_13 = 8'd44;
localparam M_DSB_WD_13 = 8'd45;
localparam M_DSB_Wz_13 = 8'd46;
localparam M_DSB_WL_14 = 8'd47;
localparam M_DSB_WD_14 = 8'd48;
localparam M_DSB_Wz_14 = 8'd49;
localparam M_DSB_WL_15 = 8'd50;
localparam M_DSB_WD_15 = 8'd51;
localparam M_DSB_Wz_15 = 8'd52;
localparam M_DSB_WE = 8'd53;
localparam M_DSB_RL_0 = 8'd60;
localparam M_DSB_RZ_0 = 8'd61;
localparam M_DSB_RR_0 = 8'd62;
localparam M_DSB_RL_1 = 8'd63;
localparam M_DSB_RZ_1 = 8'd64;
localparam M_DSB_RR_1 = 8'd65;
localparam M_DSB_RL_2 = 8'd66;
localparam M_DSB_RZ_2 = 8'd67;
localparam M_DSB_RR_2 = 8'd68;
localparam M_DSB_RL_3 = 8'd69;
localparam M_DSB_RZ_3 = 8'd70;
localparam M_DSB_RR_3 = 8'd71;
localparam M_DSB_RL_4 = 8'd72;
localparam M_DSB_RZ_4 = 8'd73;
localparam M_DSB_RR_4 = 8'd74;
localparam M_DSB_RL_5 = 8'd75;
localparam M_DSB_RZ_5 = 8'd76;
localparam M_DSB_RR_5 = 8'd77;
localparam M_DSB_RL_6 = 8'd78;
localparam M_DSB_RZ_6 = 8'd79;
localparam M_DSB_RR_6 = 8'd80;
localparam M_DSB_RL_7 = 8'd81;
localparam M_DSB_RZ_7 = 8'd82;
localparam M_DSB_RR_7 = 8'd83;
localparam M_DSB_RL_8 = 8'd84;
localparam M_DSB_RZ_8 = 8'd85;
localparam M_DSB_RR_8 = 8'd86;
localparam M_DSB_RL_9 = 8'd87;
localparam M_DSB_RZ_9 = 8'd88;
localparam M_DSB_RR_9 = 8'd89;
localparam M_DSB_RL_10 = 8'd90;
localparam M_DSB_RZ_10 = 8'd91;
localparam M_DSB_RR_10 = 8'd92;
localparam M_DSB_RL_11 = 8'd93;
localparam M_DSB_RZ_11 = 8'd94;
localparam M_DSB_RR_11 = 8'd95;
localparam M_DSB_RL_12 = 8'd96;
localparam M_DSB_RZ_12 = 8'd97;
localparam M_DSB_RR_12 = 8'd98;
localparam M_DSB_RL_13 = 8'd99;
localparam M_DSB_RZ_13 = 8'd100;
localparam M_DSB_RR_13 = 8'd101;
localparam M_DSB_RL_14 = 8'd102;
localparam M_DSB_RZ_14 = 8'd103;
localparam M_DSB_RR_14 = 8'd104;
localparam M_DSB_RL_15 = 8'd105;
localparam M_DSB_RZ_15 = 8'd106;
localparam M_DSB_RR_15 = 8'd107;
localparam M_DSB_RE = 8'd108;
localparam M_DSB_RZ_0 = 8'd61;
localparam M_DSB_RR_0 = 8'd62;
localparam M_DSB_RL_1 = 8'd63;
localparam M_DSB_RZ_1 = 8'd64;
localparam M_DSB_RR_1 = 8'd65;
localparam M_DSB_RL_2 = 8'd66;
localparam M_DSB_RZ_2 = 8'd67;
localparam M_DSB_RR_2 = 8'd68;
localparam M_DSB_RL_3 = 8'd69;
localparam M_DSB_RZ_3 = 8'd70;
localparam M_DSB_RR_3 = 8'd71;
localparam M_DSB_RL_4 = 8'd72;
localparam M_DSB_RZ_4 = 8'd73;
localparam M_DSB_RR_4 = 8'd74;
localparam M_DSB_RL_5 = 8'd75;
localparam M_DSB_RZ_5 = 8'd76;
localparam M_DSB_RR_5 = 8'd77;
localparam M_DSB_RL_6 = 8'd78;
localparam M_DSB_RZ_6 = 8'd79;
localparam M_DSB_RR_6 = 8'd80;
localparam M_DSB_RL_7 = 8'd81;
localparam M_DSB_RZ_7 = 8'd82;
localparam M_DSB_RR_7 = 8'd83;
localparam M_DSB_RL_8 = 8'd84;
localparam M_DSB_RZ_8 = 8'd85;
localparam M_DSB_RR_8 = 8'd86;
localparam M_DSB_RL_9 = 8'd87;
localparam M_DSB_RZ_9 = 8'd88;
localparam M_DSB_RR_9 = 8'd89;
localparam M_DSB_RL_10 = 8'd90;
localparam M_DSB_RZ_10 = 8'd91;
localparam M_DSB_RR_10 = 8'd92;
localparam M_DSB_RL_11 = 8'd93;
localparam M_DSB_RZ_11 = 8'd94;
localparam M_DSB_RR_11 = 8'd95;
localparam M_DSB_RL_12 = 8'd96;
localparam M_DSB_RZ_12 = 8'd97;
localparam M_DSB_RR_12 = 8'd98;
localparam M_DSB_RL_13 = 8'd99;
localparam M_DSB_RZ_13 = 8'd100;
localparam M_DSB_RR_13 = 8'd101;
localparam M_DSB_RL_14 = 8'd102;
localparam M_DSB_RZ_14 = 8'd103;
localparam M_DSB_RR_14 = 8'd104;
localparam M_DSB_RL_15 = 8'd105;
localparam M_DSB_RZ_15 = 8'd106;
localparam M_DSB_RR_15 = 8'd107;
localparam M_DSB_RE = 8'd108;
localparam N_DSB_EXCEP = 8'd200;
reg[7:0] state = M_DSB_IDLE;
reg[31:0] cnt = 32'd0;
reg out_en = 1'b0;
reg out_data;
reg[31:0] cnt = 32'd0;
reg out_en = 1'b0;
reg out_data;
reg[15:0] w_cmd = {8'h44,8'hcc};
reg[15:0] r_cmd = {8'hbe,8'hcc};
reg[15:0] r_cmd = {8'hbe,8'hcc};
reg[15:0] r_Data;
reg[7:0] oft;
reg[1:0] r_w_falg;
reg[7:0] index;
reg[1:0] r_w_falg;
reg[7:0] index;
reg[31:0] ack_cnt;
reg[31:0] free_cnt;
reg[31:0] free_cnt;
assign io_signel = out_en?out_data:1'bz;
always@(posedge clk or negedge rst_n)
begin
if(rst_n ==1'b0)
begin
state<=M_DSB_IDLE;
cnt<=0;
out_data <=0;
out_en <=1'b0;
end
else
begin
always@(posedge clk or negedge rst_n)
begin
if(rst_n ==1'b0)
begin
state<=M_DSB_IDLE;
cnt<=0;
out_data <=0;
out_en <=1'b0;
end
else
begin
if(~|cnt)
begin
case(state)
M_DSB_IDLE:
begin
out_en <=1'b0;
r_w_falg <=2'd0;
if(io_signel==1'b1)
begin
state <= state 8'd1;
cnt <=SEC_WAIT;
end
else
begin
state <= M_DSB_IDLE;
cnt<=0;
end
end
M_DSB_RESET://拉低600us
begin
state <= state 8'd1;
out_en <=1'b1;
out_data <= 1'b0;
cnt <=M_RESET_WAIT;
end
M_DSB_RFEE://释放60us
begin
out_en <=1'b0;
out_data <= 1'b1;
state <= state 8'd1;
cnt <=M_FREE_WAIT;
ack_cnt <=SEC_WAIT;
free_cnt <=SEC_WAIT;
end
S_DSB_ACK:
begin
out_en <=1'b0;
out_data <= 1'b1;
if(io_signel==1'b0)
begin
state <= state 8'd1;
cnt <=ACK_WAIT;
end
else
begin
ack_cnt<= ack_cnt-32'd1;
if(~|ack_cnt)
begin
state <=N_DSB_EXCEP;
end
end
end
s_DSB_FRE:
begin
if(io_signel==1'b1)
begin
oft <=8'd0;
if(r_w_falg==2'd2)
begin
state <= M_DSB_IDLE;
cnt <=FREE_WAIT;
end
else
begin
state <= M_DSB_WL_0;
cnt <=FREE_WAIT;
end
end
else
begin
free_cnt<= free_cnt-32'd1;
if(~|free_cnt)
begin
state <=N_DSB_EXCEP;
end
end
end
M_DSB_WL_0,M_DSB_WL_1,M_DSB_WL_2,M_DSB_WL_3,M_DSB_WL_4,M_DSB_WL_5,M_DSB_WL_6,M_DSB_WL_7,
M_DSB_WL_8,M_DSB_WL_9,M_DSB_WL_10,M_DSB_WL_11,M_DSB_WL_12,M_DSB_WL_13,M_DSB_WL_14,M_DSB_WL_15:
begin
state <= state 8'd1;
out_en <=1'b1;
out_data <= 0;
cnt <=M_WL_WAIT;//低13us
end
M_DSB_WD_0,M_DSB_WD_1,M_DSB_WD_2,M_DSB_WD_3,M_DSB_WD_4,M_DSB_WD_5,M_DSB_WD_6,M_DSB_WD_7,
M_DSB_WD_8,M_DSB_WD_9,M_DSB_WD_10,M_DSB_WD_11,M_DSB_WD_12,M_DSB_WD_13,M_DSB_WD_14,M_DSB_WD_15:
begin
state <= state 8'd1;
out_en <=1'b1;
cnt <=M_WD_WAIT;//data 40us
if(r_w_falg==2'd0)
out_data <= w_cmd[oft];
else
out_data <= r_cmd[oft];
end
M_DSB_Wz_0,M_DSB_Wz_1,M_DSB_Wz_2,M_DSB_Wz_3,M_DSB_Wz_4,M_DSB_Wz_5,M_DSB_Wz_6,M_DSB_Wz_7,
M_DSB_Wz_8,M_DSB_Wz_9,M_DSB_Wz_10,M_DSB_Wz_11,M_DSB_Wz_12,M_DSB_Wz_13,M_DSB_Wz_14,M_DSB_Wz_15:
begin
state <= state 8'd1;
oft <=oft 8'd1;
out_en <=1'b0;
cnt <=M_WZ_WAIT;//data 1us
end
M_DSB_WE:
begin
if(r_w_falg==2'd0)
begin
state <= M_DSB_RESET;
out_en <=1'b0;
r_w_falg <=r_w_falg 2'd1;
cnt <=N_CH_WAIT;//data 800ms
end
else
begin
state <= M_DSB_RL_0;
index <=8'd0;
end
end
M_DSB_RL_0,M_DSB_RL_1,M_DSB_RL_2,M_DSB_RL_3,M_DSB_RL_4,M_DSB_RL_5,M_DSB_RL_6,M_DSB_RL_7,
M_DSB_RL_8,M_DSB_RL_9,M_DSB_RL_10,M_DSB_RL_11,M_DSB_RL_12,M_DSB_RL_13,M_DSB_RL_14,M_DSB_RL_15:
begin
state <= state 8'd1;
out_en <=1'b1;
out_data <= 0;
cnt <=M_RL_WAIT;//拉低2US
end
M_DSB_RZ_0,M_DSB_RZ_1,M_DSB_RZ_2,M_DSB_RZ_3,M_DSB_RZ_4,M_DSB_RZ_5,M_DSB_RZ_6,M_DSB_RZ_7,
M_DSB_RZ_8,M_DSB_RZ_9,M_DSB_RZ_10,M_DSB_RZ_11,M_DSB_RZ_12,M_DSB_RZ_13,M_DSB_RZ_14,M_DSB_RZ_15:
begin
state <= state 8'd1;
out_en <=1'b0;
cnt <=M_RZ_WAIT;//释放10US
end
M_DSB_RR_0,M_DSB_RR_1,M_DSB_RR_2,M_DSB_RR_3,M_DSB_RR_4,M_DSB_RR_5,M_DSB_RR_6,M_DSB_RR_7,
M_DSB_RR_8,M_DSB_RR_9,M_DSB_RR_10,M_DSB_RR_11,M_DSB_RR_12,M_DSB_RR_13,M_DSB_RR_14,M_DSB_RR_15:
begin
state <= state 8'd1;
out_en <=1'b0;
r_Data[index] <=io_signel;
cnt <=M_RR_WAIT;
index <= index 8'd1;
end
M_DSB_RE:
begin
state <= M_DSB_RESET;
r_w_falg <=r_w_falg 2'd1;
end
N_DSB_EXCEP:
begin
state <=M_DSB_IDLE;
cnt <=SEC_WAIT;
out_en <=1'b0;
end
default:
begin
state <=M_DSB_IDLE;
cnt <=SEC_WAIT;
out_en <=1'b0;
end
endcase
end
else
begin
cnt <=cnt-1;
state <= state;
end
end
end
begin
case(state)
M_DSB_IDLE:
begin
out_en <=1'b0;
r_w_falg <=2'd0;
if(io_signel==1'b1)
begin
state <= state 8'd1;
cnt <=SEC_WAIT;
end
else
begin
state <= M_DSB_IDLE;
cnt<=0;
end
end
M_DSB_RESET://拉低600us
begin
state <= state 8'd1;
out_en <=1'b1;
out_data <= 1'b0;
cnt <=M_RESET_WAIT;
end
M_DSB_RFEE://释放60us
begin
out_en <=1'b0;
out_data <= 1'b1;
state <= state 8'd1;
cnt <=M_FREE_WAIT;
ack_cnt <=SEC_WAIT;
free_cnt <=SEC_WAIT;
end
S_DSB_ACK:
begin
out_en <=1'b0;
out_data <= 1'b1;
if(io_signel==1'b0)
begin
state <= state 8'd1;
cnt <=ACK_WAIT;
end
else
begin
ack_cnt<= ack_cnt-32'd1;
if(~|ack_cnt)
begin
state <=N_DSB_EXCEP;
end
end
end
s_DSB_FRE:
begin
if(io_signel==1'b1)
begin
oft <=8'd0;
if(r_w_falg==2'd2)
begin
state <= M_DSB_IDLE;
cnt <=FREE_WAIT;
end
else
begin
state <= M_DSB_WL_0;
cnt <=FREE_WAIT;
end
end
else
begin
free_cnt<= free_cnt-32'd1;
if(~|free_cnt)
begin
state <=N_DSB_EXCEP;
end
end
end
M_DSB_WL_0,M_DSB_WL_1,M_DSB_WL_2,M_DSB_WL_3,M_DSB_WL_4,M_DSB_WL_5,M_DSB_WL_6,M_DSB_WL_7,
M_DSB_WL_8,M_DSB_WL_9,M_DSB_WL_10,M_DSB_WL_11,M_DSB_WL_12,M_DSB_WL_13,M_DSB_WL_14,M_DSB_WL_15:
begin
state <= state 8'd1;
out_en <=1'b1;
out_data <= 0;
cnt <=M_WL_WAIT;//低13us
end
M_DSB_WD_0,M_DSB_WD_1,M_DSB_WD_2,M_DSB_WD_3,M_DSB_WD_4,M_DSB_WD_5,M_DSB_WD_6,M_DSB_WD_7,
M_DSB_WD_8,M_DSB_WD_9,M_DSB_WD_10,M_DSB_WD_11,M_DSB_WD_12,M_DSB_WD_13,M_DSB_WD_14,M_DSB_WD_15:
begin
state <= state 8'd1;
out_en <=1'b1;
cnt <=M_WD_WAIT;//data 40us
if(r_w_falg==2'd0)
out_data <= w_cmd[oft];
else
out_data <= r_cmd[oft];
end
M_DSB_Wz_0,M_DSB_Wz_1,M_DSB_Wz_2,M_DSB_Wz_3,M_DSB_Wz_4,M_DSB_Wz_5,M_DSB_Wz_6,M_DSB_Wz_7,
M_DSB_Wz_8,M_DSB_Wz_9,M_DSB_Wz_10,M_DSB_Wz_11,M_DSB_Wz_12,M_DSB_Wz_13,M_DSB_Wz_14,M_DSB_Wz_15:
begin
state <= state 8'd1;
oft <=oft 8'd1;
out_en <=1'b0;
cnt <=M_WZ_WAIT;//data 1us
end
M_DSB_WE:
begin
if(r_w_falg==2'd0)
begin
state <= M_DSB_RESET;
out_en <=1'b0;
r_w_falg <=r_w_falg 2'd1;
cnt <=N_CH_WAIT;//data 800ms
end
else
begin
state <= M_DSB_RL_0;
index <=8'd0;
end
end
M_DSB_RL_0,M_DSB_RL_1,M_DSB_RL_2,M_DSB_RL_3,M_DSB_RL_4,M_DSB_RL_5,M_DSB_RL_6,M_DSB_RL_7,
M_DSB_RL_8,M_DSB_RL_9,M_DSB_RL_10,M_DSB_RL_11,M_DSB_RL_12,M_DSB_RL_13,M_DSB_RL_14,M_DSB_RL_15:
begin
state <= state 8'd1;
out_en <=1'b1;
out_data <= 0;
cnt <=M_RL_WAIT;//拉低2US
end
M_DSB_RZ_0,M_DSB_RZ_1,M_DSB_RZ_2,M_DSB_RZ_3,M_DSB_RZ_4,M_DSB_RZ_5,M_DSB_RZ_6,M_DSB_RZ_7,
M_DSB_RZ_8,M_DSB_RZ_9,M_DSB_RZ_10,M_DSB_RZ_11,M_DSB_RZ_12,M_DSB_RZ_13,M_DSB_RZ_14,M_DSB_RZ_15:
begin
state <= state 8'd1;
out_en <=1'b0;
cnt <=M_RZ_WAIT;//释放10US
end
M_DSB_RR_0,M_DSB_RR_1,M_DSB_RR_2,M_DSB_RR_3,M_DSB_RR_4,M_DSB_RR_5,M_DSB_RR_6,M_DSB_RR_7,
M_DSB_RR_8,M_DSB_RR_9,M_DSB_RR_10,M_DSB_RR_11,M_DSB_RR_12,M_DSB_RR_13,M_DSB_RR_14,M_DSB_RR_15:
begin
state <= state 8'd1;
out_en <=1'b0;
r_Data[index] <=io_signel;
cnt <=M_RR_WAIT;
index <= index 8'd1;
end
M_DSB_RE:
begin
state <= M_DSB_RESET;
r_w_falg <=r_w_falg 2'd1;
end
N_DSB_EXCEP:
begin
state <=M_DSB_IDLE;
cnt <=SEC_WAIT;
out_en <=1'b0;
end
default:
begin
state <=M_DSB_IDLE;
cnt <=SEC_WAIT;
out_en <=1'b0;
end
endcase
end
else
begin
cnt <=cnt-1;
state <= state;
end
end
end
endmodule
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