altera公司IP核使用手册.PDF

【实例简介】
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用
A吉RA Contents Chapter 1. About this MegaCore Function Release informat 1-1 Device Family Support ··· Introduction .····· ····· Features Open core plus evaluation 1-3 Performance ··· Chapter 2. Getting Started Design Flow 衡·鲁·,看·,音番 2-1 Megacore Function walkthrough 2-2 Create a New quartus II Pi 2-2 Launch the mega Wizard Plug-in Manager Step 1: Parameterize 2-5 Step 2: Set Up Simulation Step 3: Generate ..,2-11 Simulate the design 2-13 Compile the design 2-13 P a Device 2-14 Set Up Licensing 2-15 ppend the license to your dat file 2-15 Specify the License File in the Quartus II Software ...2-15 Example Simulation and Compilation ..2-16 Example quartus Ii project 2-16 Example simulation with Test Vectors ,,,,,,2-16 Chapter 3. Specifications yperTransport Technology Overview 1 HT SyStems 3-2 HT Flow Control Hyper Transport MegaCore Function Specification Physical Interface Synchronization and alignment ... Protocol interf Clocking Options....... HyperTransport Mega Core Function Parameters and HT Link Performance 3-10 Signals 3-14 CSR Module ...3-31 OpenCore plus time-Out Behavior Appendix A. Parameters Introduction 鲁鲁鲁 A-1 Parameter lists Device Family and Read Only registers ··········· ,,,,,,,,,,A-1 Base Address Registers 番鲁 ,A-2 Clocking Options A-3 Advanced settings o March 2009 Altera corporation HyperTransport MegaCore Function User Guide Appendix B. Stratix Device Pin Assignments Introduction B-1 Guidelines Appendix C. Example design General description Additional information Revision history Into-l How to Contact altera Info-1 Typographic Conventions .......... Info-2 Hyper Transport MegaCore Function User Guide o March 2009 Altera Corporation A吉RA 1. About this MegaCore Function Release Information Table 1-1 provides information about this release of the Hyper Transport Mega Coret functio Table 1-1. Hyper Transport Mega Core Function Release Information it enl Description ∨ ersion 9.0 Release date March 2009 Ordering code IP-HT Product ID(s) 0098 Vendor iD(s) 6AF7 Altera verifies that the current version of the quartus@ll software compiles the previous version of each MegaCore function. Any exceptions to this verification are reported in the Mega Core lP Library release Notes and Errata. Altera does not verify compilation with Mega Core function versions older than one release Device Family Support MegaCore functions provide either full or preliminary support for target Altera device families: Full support means the Mega Core function meets all functional and timing requirements for the device family and may be used in production designs a Preliminary support means the Mega Core function meets all functional requirements, but may still be undergoing timing analysis for the device family;it may be used in production designs with caution Table 1-2 shows the level of support offered by the Hyper Transport MegaCore function for each of the altera device families Table 1-2. Device Family Support Device Family Support Hard Copy Stratix@ Full Stratix Ful Stratix II Ful Stratix‖GX Preliminary Stratix GX Other device families No support C March 2009 Altera Corporation HyperT ransport Mega Core Function User Guide 1-2 Chapter 1: About this MegaCore Function Introduction Introduction The Hyper Transport Mega Core function implements high-speed packet transfers between physical(PhY) and link-layer devices, and is fully compliant with the HyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allows designers to interface to a wide range of Hyper TransportTm technology(hT)enabled devices quickly and easily, including network processors, coprocessors, video chipsets, and ASICs Features The Hyper Transport Mega Core function has the following features 8-bit fully integrated hT end-chain interface Packet-based protocol Dual unidirectional point-to-point links Up to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction) 200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices 200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devices Low-swing differential signaling with 100-Q2 differential impedance Hardware verified with Hyper fransport interfaces on multiple industry standard processor and bridge devices Fully parameterized mega core function allows flexible, easy configuration Fully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GX evice familles Application-side interface uses the Altera AtlanticTM interface standard Manages Hr flow control, optimizing performance and ease of use Independent buffering for each HT virtual channel Automatic handling of ht ordering rules Stalling of one virtual channel does not delay other virtual channels(subject to orderin g Flexible parameterized buffer sizes, allowing customization depending on system requirements User interface has independent interfaces for the HT virtual channels, allowing independent user logic design Cyclic redundancy code(crc) generation and checking to preserve data integrity Integrated detection and response to common HT error conditions ■ CRC errors End-chain errors Fully integrated HT configuration space includes all required configuration space registers and HT capabilities list registers Hyper Transport MegaCore Function User Guide o March 2009 Altera Corporation Chapter 1: About this MegaCore Function Performance 32-bit and 64-bit support across all base address registers bars) automatically handles all csr space accesses Verilog HDL and VHdL simulation support Open Core Plus Evaluation With the Altera free Open Core Plus evaluation feature, you can perform the following Simulate the behavior of a mcgafunction(Altera MegaCore function or AMPP megafunction) within your system a Verify the functionality of your design, as well as quickly and easily evaluate its size and speed Generate time-limited device programming files for designs that include MegaCore functions Program a device and verify your design in hardware You only need to purchase a license for the Mega Core function when you are completely satisfied with its functionality and performance and want to take your design to production o For more information about Open Core Plus hardware evaluation using the HyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"on page 3-40 and AN 320: Open Core Plus Evaluation of megafunctions Performance The Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2 single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 show typical performance and adaptive look-up table (alut) or logic element (LE)usage for the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, and Stratix GX devices respectively, using the Quartus@ II software version 7.1 Table 1-3 shows the maximum supported data rates in megabits per second(Mbps) by device family and speed grade Table 1-3. Maximum Supported Hyper Transport Data Rates (Note 1) Speed Grade Device Family -3 6 Stratix ll GX devices 1000 Mbps 1000 Mbps 800 Mbps NA(2) N/A(2 NA(2) Stratix devices 1000 Mbps 1000 Mbps 800 Mbps N/A(2) NA(2) NA(2) Stratix devices N/A(2 N/A(2) 00 Mbps 800 Mbps 600 Mbps 400 Mbps Flip-Chip packages Stratix devices NA(2) NA(2) NA(2) 600 Mbps 400 Mbps 400 Mbps (Wire Bond packages Stratix GX devices N/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2) Notes to table 1-3 (1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face (2) Devices ot this speed grade are not ottered in this device family C March 2009 Altera Corporation HyperTransport Mega Core Function User Guide Chapter 1: About this MegaCore Function Performance Table 1-4 shows performance and device utilization for the Hyper Transport MegaCore function in Stratix II and Stratix II GX devices Table 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX Devices Parameters Memory User RX Combinational HT Link Interface Posted Non-Posted Response Clocking ALUTS Logic fMAX(MHz) MAx(MHz) Buffers Buffers Buffers Option(1 2) Registers M4K M512 ( 3) 3) Shared 3.500 5200120 500 125(4 RX/TX/Ref 3500 5200 500 Ref/x 8 Shared 3600 5400160500 >150 RX/TX Shared 4.000 6,000 16 150 RX/TX 16 Shared 4,100 6,200 500 125(4) RX/TX/Ref Shared 4.100 6200 500 125(4 Ref/Tx Shared 4.200 6400160 150 RX/TX Notes to table 1-4. Refer to " Clocking Options "on page 3-7 for more information about these options (2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200 (3)Figures for -3 speed grade devices only (4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided by Table 1-5 shows performance and device utilization for the Hyper Transport MegaCore function in Stratix and Stratix GX devices Table 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX Devices User Interface fmax Parameters Utilization HT Link fMAX MHz) MHZ) RX RX Speed Grade Posted Non-Posted Response Clocking Option LEs M4K Buffers Buffers Buffers ) (2 Blocks.5 -6 6 Shared rx/tx/ref 12 400 10073)10073 4448888 Shared Ref/Tx 7, 600 14 400400100{3)100(3) Shared rxtx 7,900 16 400 400>125>100 Shared rxtx 8.900 125>100 16 8 Shared Rx/T×Ref9,400 12 400 4001003)1003 16 Shared ref/ ix 9.500 14 4001003)10073) 16 Shared rx/x 9.700 400 125 Notes to table 1-5: (1)Refer to Clocking Options"on page 3-7 for more information about these options (2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES (3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by four Hyper Transport MegaCore Function User Guide C March 2009 Altera Corporation A吉RA 2. Getting Started Design Flow To evaluate the HyperTransport Mega Core function using the Open Core Plus feature, include these steps in your design flow Obtain and install the HyperTransport Mega Core function The HyperTransport Mega Core function is part of the MegaCore IP Library, which is distributed with the Quartus ii software and downloadable from the altera website www.altera.com o For system requirements and installation instructions, refer to Quartus II Installation Licensing for Windows and Linux Workstations on the Altera website at www.altera.com/literature/lit-qts.isp Figure 2-1 shows the directory structure after you install the HyperTransport MegaCore function, where <path> is the installation directory. The default installation Windows is C: altera\ <version number>; on Linux it is lopt/altera<version number> Figure 2-1. Directory Structure Installation directory p Contains the Altera MegaCore IP Library and third-party IP cores altera Contains the Altera MegaCore IP Library common Contains shared components ht Contains the Hyper Transport Hyper Transport Megacore function files and documentation doc Contains the documentation for the Hyper Transport MegaCore function lib Contains encrypted lower-level design files example Contains the design example for the Hyper Transport Mega Core function 2. Create a custom variation of the Hyper Transport Mega Core function 3. Implement the rest of your design using the design entry method of your choice 4. Use the IP functional simulation model to verify the operation of your design o For more information about Ip functional simulation models, refer to the Simulating Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook 5. Use the Quartus II software to compile your design C March 2009 Altera Corporation HyperT ransport Mega Core Function User Guide 2-2 Chapter 2: Getting Started Mega Core Function Walkthrough Ig You can also generate an Open Core Plus time-limited programming file, which you can use to verify the operation of your design in hardware 6. Purchase a license for the hypertransport Mega Core function After you have purchased a license for the Hyper transport mega Core function follow these additional steps 1. Set up licensing 2. Generate a programming file for the Altera device(s)on your board 3. Program the Altera device(s)with the completed design MegaCore Function Walkthrough This walkthrough explains how to create a custom variation using the Altera Hyper Transport IP Toolbench and the Quartus II software, and simulate the function using an ip functional simulation model and the modelsim software when you are finished generating your custom variation of the function, you can incorporate it into ⅴ our overall project Ie IP Toolbench allows you to select only legal combinations of parameters, and warns ou of any invalid configurations In this walkthrough you follow these steps Create a New Quartus II Project a Launch the MegaWizard Plug-in Manager ■Step1: Parameterize a Step 2: Set Up Simulation ■Step3: Generate ■ Simulate the design To generate a wrapper file and Ip functional simulation model using default values, omit the procedure described in"Step 1: Parameterizeon page 2-5 Create a New Quartus ll Project Create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity To create a new project, perform the following steps 1. On the Windows Start menu, select Programs> Altera> Quartus II <version> to start the Quartus lI software. Alternatively, you can use the Quartus II Web edition software 2. In the Quartus II window, on the File menu, click New Project Wizard. If you did not turn it off previously, the New Project Wizard Introduction page appears 3. On the New Project Wizard Introduction page, click Next Hyper Transport MegaCore Function User Guide o March 2009 Altera Corporation 【实例截图】
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