ug898-vivado-embedded-design

【实例简介】
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L XILINX ALL PROGRAMMABLEIN Table of contents Revision History 2 Chapter 1: Introduction Overview。,,,,,,,,,,,,,,。,,,,,,,,,,,,,,,,, Hardware and Software Tool flow overview 5 Starting a Zynq 7000 Based Design 看D D意 Chapter 2: Using a Zynq-7000 Processor in an Embedded Design Introduction ■。·DD曹 Designing for Zyng-7000 Devices in the vivado Ide...................8 Overview of the Zyng block Design and Configuration Window.............. 13 Using the Programmable logic (PL) 31 Vivado Pin Planner View of PS 1/o .,.,,,,,,.,,,,,,...43 Vivado IDE Generated Embedded files 43 Using the Software Development Kit(SDK) 43 Chapter 3: Using a MicroBlaze Processor in an Embedded Design Introduction to Micro Blaze Processor Design ... 46 Creating an IP Integrator Design with the Micro blaze Processor ,,,,47 MicroBlaze Configuration Window........ 50 Cross- Trigger Feature of MicroBlaze Processors .................... 66 Custom Logic............... 72 Embedded IP Catalog.,... DD··D看 72 Completing Connections 73 Chapter 4: Designing with the MIG Core Overview ··· 80 Project Creation∴..… 81 Designing in IP Integrator ,,83 Chapter 5: Reset and clock Topologies in IP Integrator verview 91 Micro blaze design without a MIG Core b·鲁·D曹··鲁 92 Embedded processor hardware design www.xilinx.com Send feedback UG898(v2014.1)May9,2014 sXL|NⅩ ALL PROGRAMMABLEN MicroBlaze Design with a MIG Core 95 Zynq Design without PL Logic....….…….…….99 Zyng-7000 Design with PL Logic .........,................. 101 Zynq design with a MIG core in the Pl.............. ,,,。,。,,105 Designs with MIG and the clocking Wizard 。107 Appendix A: Additional Resources and Legal notices Xilinx resources 108 References,,,,,,,,,,,,。,,,,,, 着看···DD曹··曹着非非曹鲁鲁·看 108 Please Read: Important Legal Notices ,,,。108 Embedded processor hardware design www.xilinx.com Send feedback UG898(v2014.1)May9,2014 ⅩL|NX ALL PROGRAMMABLEIN Chapter 1 Introduction Overview This chapter provides an introduction to using the Xilinx Vivado Design Suite flow for programming an embedded design using the Zyng@ -7000 All Programmable(Ap) Soc device or the microBlazeTm processor Embedded systems are complex. Hardware and software portions of an embedded design are projects in themselves. Merging the two design components so that they function as one system creates additional challenges. Add an FPga design project, and the situation can become very complicated To simplify the design process, Xilinx offers several sets of tools. It is a good idea to know the basic tool names project file names, and acronyms for these tools The v ivado Integrated Design Environment(IDE)includes the IP integrator tool, which you can use to stitch together a processor-based design. This tool, combined with the xilinx Software Development Kit(SDK), provides an integrated environment to design and debug microprocessor-based systems and embedded software applications Hardware and software tool flow overview The vivado tools provide specific flows for programming based on the processor. the Vivado iDE uses the IP integrator with graphic connectivity screens to specify the device, select peripherals, and configure hardware settings. The Zynq-7000 AP Soc uses the Vivado ip integrator to capture hardware platform information in XML format applications, along with other data files. These are used in software design tools to create and configure Board Support Package(BSP)libraries, infer compiler options, program the Pl, define jTAG settings, and automate other operations hat require information about the hardware. The Zyng 7000 Soc solution reduces the complexity of an embedded design by offering an ARM Cortex a9 dual core as an embedded block, and programmable logic along with it, on a single Soc Embedded processor hardware design www.xilinx.com Send feedback UG898(v2014.1)May9,2014 K XILINX Chapter 1: Introduction Xilinx provides the following design tools for developing and debugging software applications for Zyng 7000 AP Soc and micro blaze processor devices Software ide GNU-based compiler tool-chain JTAG debugger These tools let you develop both bare-metal applications that do not require an operating system, and applications for the open-source Linux operating system. the Vivado Ip ntegrator captures information about the Processing System(PS)and peripherals, including configuration settings, register memory map, and associated logic in the Processing Logic(PL) fabric. Bitstream can then be generated for PL initialization Software solutions are also available from third-party sources that support Cortex-A9 processors, including but not limited to Software ides Compiler tool-chains Debug and trace tools Embedded os and software libraries Simulators Models and virtual prototyping tools Third-party tool solutions vary in the level of integration and direct support for Zyng -7000 devices See the Zyng-7000 All Programmable Soc Software Developers Guide(UG821)[Ref 1] for more information about the sdk and programming for zyng devices. the sdk is a standaloneproductandisavailablefordownloadfromwww.xilinx.com Figure 1-1 illustrates the tools flow for embedded hardware Specificat Contiguration File ( Xml) Generate Export to Configure Hardware Add IP Bitstream Softw Handoff optional Tools PL BRAM Configuration Configuratio (bitstream) BMM) X12502 Figure 1-1: Hardware Design Tool Handoff to Software Tools Embedded processor hardware design www.xilinx.com Send feedback UG898(v2014.1)May9,2014 K XILINX Chapter 1: Introduction Starting a Zyng-7000 Based Design To start a Zyng-7000-based design, do the following 1. Create a new Vivado ide project 2. Create a block design in the IP Integrator tool and instantiate the Zyng processing ystem 7 IP along with any other Xilinx IP or your custom IP. 3. Run the design through synthesis and implementation and export the hardware to SDK 4. In SDK, you create your software application, which you can then program into the target board Embedded processor hardware design www.xilinx.com Send feedback 7 UG898(v2014.1)May9,2014 ⅩL|NX ALL PROGRAMMABLEIN Chapter 2 Using a Zyng-7000 Processor in an Embedded design Introduction This chapter describes how to use the Xilinx vivadoR Design Suite flow for using the Zyng r-7000 All Programmable(AP)Soc device The examples target the Xilinx ZC702 Rev 1.0 evaluation board and the tool versions in the 2013. 2 Vivado Design Suite release IMPORTANT: The Vivado /p integrator is the replacement for xilinx Platform Studio(XpS) for embedded processor designs, including designs targeting Zyng devices and MicroBlaze TM processors XPS only supports designs targeting Micro blaze processors. Both ip integrator and Xps are available from the vivado integrated design environment(DE) Designing for Zyng-7000 Devices in the vivado IDE Designing for Zyng 7000 AP Soc devices is different using the vivado ide than in the ise Design Suite and Embedded Development Kit(EDK The Vivado ide uses the ip integrator tool for embedded development. The IP integrator is a GUI-based interface that lets you stitch together complex IP subsystems a variety of ip are available in the vivado ide ip catalog to accommodate complex designs You can also add custom ip to the ip catalog see the vivado design Suite User guide Designing /P Subsystems Using /P Integrator(UG994)[Ref 2] for more information Embedded processor hardware design www.xilinx.com Send feedback UG898(v2014.1)May9,2014 K XILINX Chapter 2: Using a Zyng-7000 Processor in an Embedded design Creating an IP Integrator Design with the Zyng-7000 Processor Click the IP integrator Create block Design button t Create Blod Design to open the create Block Design dialog box, where you can enter the design Name as shown in the figure below A Create Block Design Please specify name of block design Design name: design_1 Directory:6<Local to Project> OK Cancel Figure 2-1: Design Name Dialog Box The block design can be created as a part of a project, or it can be created in a different location that you can specify in the Directory field Embedded processor hardware design www.xilinx.com Send feedback UG898(v2014.1)May9,2014 K XILINX Chapter 2: Using a Zyng-7000 Processor in an Embedded design The block design window opens, as shown in Figure 2-2 Block Design- design_1 Design Hierarchy x Diagram x 口X 〓图 品 design1 La, design 1 a@ This design is empty. To get started, Add IP from the catalog & Source.DsL.回sgns崛Bar.」 Properti 中中 Figure 2-2: block Design Window 1. In the empty block design canvas, you are prompted to Add IP from the IP Catalog (Figure 2-3). You can also right-click in the canvas and select Add IP 上 Diagram x ① This desiyn is empLy. Tu yel sldr led Ir uirI Lle coldly Ctrl+E x Delete Delete Paste Clrl+v earch Clrl+F A Select A‖ Ctrl+A Ctrl+I F6 Figure 2-3: Adding IP in the block Design Canvas Embedded Processor hardware design www.xilinx.com Send feedback 10 UG898(v20141)May9,2014 【实例截图】
【核心代码】