DP 1.2a标准协议

【实例简介】
DP 1.2a标准协议
2.5.5 Topology Discovery 136 2.5.6 Topology Maintenance 136 2.5.7 Topologies with SST-only Source devices 2.5.8 Loop Handling 137 2.6 Multi-Stream Transport Operation 138 2.6.1 Link Timing Generation Based on Multi-Stream Transport Packet 144 2.6.2 Symbol Sequence Mapping into VC Payload …145 2.6.3 Time Slot Count Allocation to VC Payload 153 2.6.4 VC Payload Allocation Synchronization Management....... 2.6. 5 ALLOCATE PAYLOAD Timing s .163 2.6.6 Impacts of Various Events on VC Payload ID Table 170 2.6.7 Robustness Requirement 2.6.8 Control Functions, Control Symbols and K-Code Assignment ,173 2.6.9 Conversion Between MST and SsT Symbol Mapping 2.6.10 MTPH Usages for CP Extension in MST Mode 176 2.7 AUX Transaction Syntax in Manchester Transaction Format 178 2.7.1 Command definition…… 179 2.7. 2 AUX Transaction Response/Reply Time-outs 2.7.3 Native AUX Request Transaction Syntax 274 Native AUX Reply Transaction Syntax…… 2.7.5 IC Bus Transaction Mapping onto AUX Syntax………… 2.7.6 Conversion ofI C Transaction to Native AUX Transaction(Informative) 200 2.7.7 I C-overAUX Transaction Clarifications and Implementation rules 200 2.8 Transaction Syntax in FaUX Transaction Format 12 2.9 AUX CH Services ······ 2.91 Stream tra Initiation si 213 2.9.2 Stream Transport Termination Sequence 214 2.9.3 AUX Link services 21 2.9.4 AUX Device Services 267 2. 10 Protocol Differentiation for Embedded Display Port(eDP) ? 2.10.1 Overview……………………………………; 269 2.10.2 Protocol Differentiation Methods 269 2.10.3 eDP Source Behavior(Informative) ··…·· 2. 10.4 Symbol Error Rate Measurement Pattern Output(Informative) ? 2. I Messaging AUX Client.……… 2.11.1 Messaging AUX Client Layers 273 2. 11. 2 Message Transaction Layer..... 274 2. 11. 3 Sideband MSG layer 283 2. 11. 4 AUX CH Support for Messaging AUX Client 287 2. 11.5 RAD Updated by Mst devices in the Path.. 2. 11.6 Broadcast Message Transactions....... 289 2.11.7 Message Delivery…… 2.11.8 Error Handling 293 2.11. 9 Descril f Available Message Transaction Requests 295 2. 12 Audio-to-Vidco Audio-to- Audio synchronization 2.12.1 Overview 3l1 2. 12.2 Display Port AV Sync Data Block 313 2. 12.3 Delay Compensation . 313 2. 13 Global Time Code and Audio Inter-channel Sync ···· 319 2.13.1 Global Time Code ..319 2. 13.2 Application of GiTC for Audio Inter-channel Synchronization ..329 3 Physical layer..........................131 3.1 Introduction 3.1.1 PHY Functions 3.1.2 Link Layer-PHY Interface Signals 3. 1. 3 PHY-Media Interface Signals 333 VESA Display port Standard MEMBER USE ONLY Ver.1.2 O Copyright 2007-2012 Video Electronics Standards association Page 3 of554 3. 1.4 Compliance measurement Points 333 3.1.5 Electrical Signal Definitions 3.1.6 Scrambling…… 345 3.1.7 Symbol Coding and Serialization/De-serialization 346 3.2 DP PWR for Box-to-Box Display port Connection 347 3.2.1 DP PWR User Detection Method 348 3. 2. 2 DP PWR Wire 348 323 Inrush Energy… 349 3.2.4 Voltage Droop..... ········*···:·*·4········““·*· 349 3.2.5 Over-Current protection 349 3.3 Hot Plug/Unplug detect Circuitr ·····“ 349 3. 4 AUX Channel 352 3.4.1 AUX Channel Logical Sub-block 352 3. 4.2 AUX Channel electrical sub-block 中· 364 3.5 Main Link 376 3.5.1 Main Link Logic Sub-block 376 5.2 Main Link electrical Sub-Block 3.5.3 Transmitter and Receiver Electrical Parameters 38: ..385 3.5.4 ESD and Eos Protection 402 4 Mechanical 403 4.1 Cable-Connector Assembly Specifications( for box-to-box)……… .403 4.1.1 Cable-Connector Assernbly Definition 403 4.1.2 Type of Bulk Cable 407 4.1.3 Impedance Profile .408 4.1. 4 Insertion Loss Return loss 410 4. 1. 5 High Bit Rate Cable-Connector Assembly Specification 4l1 4.1.6 Reduced Bit Rate Cable-Connector Assembly Specification 421 4.2 Connector Specification .425 4.2.1 External Full-size Connector 4.2.2 Mini Display Port External Connector 437 4.2.3 Panel-side Internal Connector (Informative). 5 Source/Sink/ Branch Device Policy Requirements for Interoperability ………471 5.1 Source device in sst mode ·垂 471 Stream Source requirement 471 5.1.2 Source Device Link Configuration requirement 474 5. 1. 3 Source Device Behavior on Stream Timing Change 475 5. 1. 4 Source Device Behavior upon HPd Pulse detection ….475 5. 1.5 Downstream Device uPacket RX Power Management by a Source Device ..477 5.1.6 Source device Connected to a branch device 477 5.2 Sink device in SSt mode 478 5.2. 1 Stream Sink requirement ..478 5.2.2 Sink Device Link Configuration Requirement. 478 5.2.3 Sink Device Behavior on Stream Timing Change 480 5.2.4 Toggling of HPD Signal for Status Change Notification 480 5.2.5 Sink Device uPacket RX Power-Save Mode 480 5.3 Branch Device in SST-only mode 484 EDID Access Handling requirement 484 5.3.2 Branch Device Link Configuration Requirements 485 53.3 Active Protocol Converter Adaptors…… .489 5.4 Source Device in Mst mod 492 5.5 Sink device in mst mode 493 5.6 Branch device in mst mode 493 5. 7 Cable-Connector Assembl 494 5.7.1 BoX-to-Box. End-User-Detachable Cable Assembly ..494 5.7.2 Embedded and Captive Cable assembly ……494 VESA Display port Standard MEMBER USE ONLY Ver.1.2 O Copyright 2007-2012 Video Electronics Standards association Page 4 of554 7. 3 Active Cable assembly 494 6 Appendix A: Audio Transport (Informative) 496 6.1 Audio Stream Components 496 6.2 Association of Three Packet Types via Packet ID….….………496 6.3 Scheduling of Audio Stream Packet 6.3. 1 Handling of an Audio Format Change 497 6. 4 Structure of Audio stream packet 498 6.4.1 One or two Channel audio 498 6.4.2 Three to Eight Channel Audio 498 6.5 Channel-to- Speaker Mapping…… 4 6.6 Transfer of Sample Frequency Information 500 7 Appendix B: Sink Event Notification Example(Informative).............50 1 7.1 Mutual Identification by Source and Sink 7.2 IRQ HPD Pulse and Sink- Specific ir……… … 501 ..501 8 Appendix C: Link Quality Management (Informative). 8.1 Marginal Link Quality 502 8.2 Analysis 502 8.3 tolerance to Bit Errors...... ………………… 502 8. 4 Link re-training 503 8.5 Long-term Link Quality Monitoring(Guidelines)..... 503 9 Appendix D: Electrical Specifications (Informative) 504 9.1 AUX Parameters 504 9. 1.1 FAUX Electrical Parameter Background.. 505 9.2 Main Link parameters 508 9.3 The dual-Dirac Jitter Model........... 512 10 Appendix E: Scrambler C Code Reference(Informative) 514 11 Appendix F: Topology Management/Payload Bandwidth Management Usage Examples ..520 12 Appendix G: Link Management During System Initialization (Informative) 2 12.1 Background… 521 12.2 Problem statements 521 12.2. 1 Problem#1: Sink Attached and Powered, but HPD Low 21 12.2.2 Problem #2: Sink HPD Unplug Event Followed by Plug Event 521 13 Appendix h: Protocol Support for 3D Stereo Display 526 13. 1 In-band 3D Stereo Signaling Methods 526 13.1.1 MSA MISCI Method 526 13. 1. 2 Video Stream Configuration Packet Method.... 13.2 3D Stereo Display Capability Declaration 532 13.2.1 EDID 3D Stereo Display Capability Declaration 13.2.2 DisplayID 3D Stereo Display Capability Declaration... 133 Display port Stereo3 D Policy Requirements for Interoperability………… …534 …535 Minimum vertical blanking will be that specified by CVT reduced blanking 536 13.3.2 Required Support for a Display Port Stereo 3D Source Device 537 14 Appendix I: QUERY STREAM ENCRYPTION STATUS Message Transaction Handling in a CP Tree Topology.... 538 14.1 Self-checking by Branch Devices...............538 14.2 Merit of QUERY STREAM ENCRYPTION STATUS Message Transaction .538 14.3 QUERY STREAM ENCRYPTION STATUS Message Transaction Handling in a CP Tree Topology 539 VESA Display port Standard MEMBER USE ONLY Ver 1.2a O Copyright 2007-2012 Video Electronics Standards association Page 5 of554 14.3.1 IDs Provided by Source Device for QUERY STREAM ENCRYPTION STATUS Request Message Transaction 540 14.3.2 Stream Status in QUERY STREAM ENCRYPTION STATUS Reply transaction 14.3.3 Stream Status Signature in QUERY STREAM ENCRYPTION STATUS Reply message Transaction 542 14.3.4 USage of Sink Type in Stream Status by a Source Device........ 542 14.3.5 Status Query 542 14.3.6 Application of QUERY STREAM ENCRYPTION STATUS Message Transaction to HDCP 545 15 Appendix J: 16 Bit Frame CRC Example 着 546 16 Main Contributor History(Previous Versions) 548 VESA Display port Standard MEMBER USE ONLY Ver 1.2a O Copyright 2007-2012 Video Electronics Standards association Page 6 of 554 Tables Table l: main Contributors to version 1.2a 22 Table 1-1: List of acronyms 30 Table 1-2: Glossary of Terms ·看垂垂音·垂垂垂垂垂 33 Table1-3: Reference documents∴.……………………37 Table 2-1: Control Symbols for Framing 53 Table 2-2: Pixel Steering into Main Link Lanes ........54 Table 2-3: VB-ID Bit Definition 6 Table 2-4: 30bpp rgb(10 Bits/Component)1366x768 Packing to a 4-Lane Main Link 59 Table 2-5: 24bpp rgb to a 4-Lane Main Link mapping .60 Table 2-6: 24bpp RGB Mapping to a 2-Lane Main Link ·,音 60 Table 2-7: 24bpp rGB Mapping to a 1-Lane Main Link ·······,·········· .60 Table 2-8: 1 bpp rgb mapping to a 4-Lane Main Link ········· 61 Table 2-9: 18bpp RGB Mapping to a 2-Lane Main Link..........61 Table 2-10: 1 bpp rGB Mapping to a 1-Lane Main Link ··甲 Tablc 2-11: 30bpp rgb mapping to a 4-Lanc Main Link …62 Table 2-12: 30bpp RGB Mapping to a 2-Lane Main Link ……62 Table 2-13: 30bpp RGB Mapping to a l-Lane Main Link …63 Table 2-14: 36bpp rgB mapping to a 4-Lane Main Link 63 Table 2-15: 36bpp RGB Mapping to a 2-Lane Main Link Table 2-16 3E PP RGB Mapping to a 1-Lane Main Lin 64 ....····:·····.·····.························.······:···· 64 Table 2-17: 48bpp rgb mapping to a 4-Lane Main Link............ 65 Table 2-18: 48bpp RGB Mapping to a 2-Lane Main Link 65 Table 2-19: 48bpp RGB Mapping to a l-Lane Main Link 66 Table2-20:l6 bpp y Cbcr42:2 Mapping to a4- Lane main Link…………….…….66 Table 2-21: 16bpp y cbCr 4:2: 2 Mapping to a 2-Lane Main Link 66 Table 2-22: 16bpp y 4: 2: 2 Mapping to a 1-Lane Main Link ...................67 Table2-23:20 bpp y cbCr422 Mapping to a4- Lane main link………………………167 Table 2-24: 20bpp YCbCr 4: 2: 2 Mapping to a 2-Lane Main Link .68 Tablc 2-25: 20bpp y CbCr 4: 2: 2 Mapping to a Onc Lanc Main Link 68 Table2-26:24 bpp y CbCr4:22 Mapping to a4- Lane main link…………68 Table 2-27: 24bpp Y CbCr 4: 2: 2 Mapping to a 2-Lane Main Link 69 ····,.·······,··丰····丰····丰···卡· Tablc 2-28: 24bpp yCbCr 4: 2: 2 Mapping to a 1-Lanc Main Link 69 Table 2-29: 32bpp Y 4: 2: 2 Mapping to a 4-Lane Main Link .······· 69 Table 2-30: 32bpp Y CbCr 4: 2: 2 Mapping to a 2-Lane Main Link 70 Table 2-31: 32bpp y cbCr 4:2 2 Mapping to a l-Lane Main Link................70 Table 2-32: 8bpp Y-only to a 4-Lane Main Link Mapping 70 Table 2-33: 8bpp Y-only Mapping to a 2-Lane Main Link 71 Table 2-34: 8bpp Y-only Mapping to a 1-Lane Main Link 71 Table2-35:l0bppY- only Mapping to a4- Lane main link……………………..……….…171 Table 2-36: 10bpp Y-only Mapping to a 2-Lane Main Link 71 Table2-37:l0bppY- only mapping to a I- lane main link………………………………72 Table 2-38: 12bpp Y-only Mapping to a 4-lane Main Link 72 Table 2-39: 12bpp Y-only Mapping to a 2-lane Main Link 垂。D· Table2-40:12bppY- only Mapping to a I- lane main Link…………….…………….…72 Table 2-41: 16bpp Y-only Mapping to a 4-lane Main Link ..72 Table 2-42: 1 6bpp Y-only Mapping to a 2-lane Main Link :····· 73 VESA Display port Standard MEMBER USE ONLY Ver.1.2 O Copyright 2007-2012 Video Electronics Standards association Page 7 of 554 Table2-43:l6bppY- only mapping to a 1- lane main Link.……………………………173 Table 2-44: Transfer Unit of 30bpp rgb video Over 2.7Gbps per Lane main Link 75 Table 2-45: MISCI and Misco Fields for Color Encoding Format Indication............84 Table2-46: Secondary- data Packet Header………… 非音非。垂垂,音,.·垂垂,音音音非垂· 85 Table 2-47: Secondary-data Packet Type …85 Table 2-48: Header Bytes of Info Frame Packet ·着音 ····:·· 87 Table 2-49: Header Bytes of Audio Time Stamp Packet 89 Table "5): Header Bytes of Audio Stream Packet Table 2-50: Examples of maud and naud values 89 91 Table 2-52 Bit Definition of an Audio Stream Packet Payload with IEC60958-like Coding 94 Table 2-53: Header Bytes of Audio Copy Management Packet .....................96 Table 2-54: Header Bytes of ISRC Packet .99 Table 2-55: Header Bytes of VSC Packet 101 Table 2-56: VSC Packet Payload .....................101 Table 2-57: Header Bytes of an Extension Packet........... 108 Table 2-58: uPacket TX AUX CH State and Event descriptions …120 Tablc2-59: u Packct RX aUⅹ CH State and event description……………….…121 Table 2-60: Summary of VC Payload Control Symbol Sequence...... …148 Table 2-61: VC Payload Bandwidth for One Time slot per mtp allocation for Various Link Configurations …156 Table 2-62: VC Payload ID Table of uPacket RX Mapped to dPCD Address Space........160 Table 2-63: DPCD Address Map for C Payload Table Update and ACT Status Verification..161 Table 2-64: Various Events and Impacts on VC Payload ID Table................171 Table 2-65: mTP Header Control functions 174 Table 2-66: MTP Payload Control Functions......... 174 Table 2-67: K-code Scrambled Index Table 2-68: Bit/Byte Size of Various Data Types of AUX Transaction Syntax ········ 179 Table 2-69: I-C Write Transaction Example 1 …185 Table 2-70: 1 C Write Transaction Method I with a Slow 1?C Bus in the Sink Device..... 187 Table 2-71: I-C Write Transaction Method 2 ··:·.·,·,· 191 Table 2-72: I-C Read Transaction Method 1 …………………193 Table 2-73: I C Read Transaction Example 2............................................................................195 Table 2-74: IC Write Followed by an IC Read 198 Tablc 2-75: Address Mapping for DPCD 216 Table2-76:ANSI8B/l0 B Encoding and Scrambling rules for Link Management……………266 Table 2-77: Display Port Address Mapping for Device Services........... 268 Tablc 2-78: Mcssagc Transaction Scqucncc Syntax …275 Table2-79: Message Transaction Request Syntax…………,….…………… Table 2-80: Request Names and request Identifiers 275 Table 2-81: Request data 276 Table 2-82: Message Transaction Reply Syntax 278 Table 2-83: Reply data......... 279 Table 2-84: reasons for naK …………………279 Table 2-85: ACK DATA 281 Table 2-86: Sideband MSG Syntax ·音,··,垂·垂看音垂章垂垂章·垂音·垂音非音音垂音·音着章 283 Table2-87: Sideband MSG Header Syntax…………………….….,,…………….,83 Table 2-88: Sideband msg Body syntax 286 Table 2-89: ALLOCATE PAYLOAD Message Syntax.........296 VESA Display port Standard MEMBER USE ONLY Ver 1.2a O Copyright 2007-2012 Video Electronics Standards association Page 8 of 554 Table2-90: CLEAR PAYLOAD ID TABLE Message Syntax…………………………298 Table 2-91: CONNECTION STATUS NOTIFY Message Syntax D。看酯4 298 Table 2-92: Peer Device Type 299 Table 2-93: Peer Device Type Determination …300 Table 2-94: ENUM PATH RESOURCES Message Syntax.........300 Table 2-95: linK AddreSS Message syntax 30 Table 2-96: POWer dOWn PHY Message syntax …303 Table 2-97: Power uP Phy Message Syntax. .........................................................304 Table 2-98: QUERY PAYLOAD Message Syntax 305 Table2-99: REMOTE DPCD READ Message Syntax……… 1305 Table 2-100: REMOTE DPCD WRITE Message Syntax 307 Table 2-101: REMOTE IC READ Message Syntax...........308 Table 2-102: REMOTE IC WRITE Message Syntax 310 Table 2-103: RESOURCE STATUS NOTIFY Message Syntax...........311 Table 2-104: DPCD Fields for GTC Operation. ...................320 Table 3-1: Allowed Vdiff pp- Pre-emphasis Combinations 342 Tablc 3-2: Post Cursor Tap Cocfficicnts (Informative).......344 Table3-3:DP_ PWR Specification for Box-to- Box Display Port Connection…………347 Table 3-4: Hot Plug Detect Signal Specification ····· .3.50 Tablc 3-5: anSi 8B/10B Spccial Charactcrs for display port Control Symbols 355 Table3-6: Display port aUX Channel Electrical Specifications……,……364 Table 3-7: FAUX Differential Noise budget 370 Table 3-8: Mask Vertices for auX ch for manchester transactions at Connector pins of tX device 371 Table 3-9: Mask Vertices for AUX CH for Manchester transactions at Connector Pins of rX device …71 Table 3-10: FaUX Forward Channel Transmitter mask Vertices 373 Table3-11: FAUX Back Channel Transmitter Mask vertices .373 Table3-12:FAUⅩ Forward channel receiver eyeⅤ ertices∴374 Table 3-13: FAUX Back Channel Receiver EYE vertices 374 Table 3-14: ANSI 8B/10B Special Characters for Display port Control Symbols 376 Table3-l5: Symbol Patterns of Link Training………………….………………379 Table 3-16: Display Port Main Link Transmitter System Parameters .385 Tablc 3-17: Display Port Main Link Transmitter TP2 Paramctcrs........ 386 Table3-l8: Display Port Main Link Transmitter TP3 EQ Parameters………………,…… 387 Table 3-19: Display Port Main Link Receiver System Parameters.......387 Tablc 3-20: Display port Main Link Rcccivcr tP3 Paramctcrs............388 Table3-2l: Display Port Main Link Receiver Tp3 EQ Parameters………………………389 Table 3-22: Differential Noise Budget 394 Table 3-23: Upstream Device Mask Vertices for High Bit Rate ........................................397 Table3-24: Upstream Device Mask Vertices for Reduced Bit rate………………...397 Table 3-25: Downstream Device EYE Vertices for TP3 EQ at HBR 98 Table 3-26: Downstream device eye vertices at tP3 for rbr.....m......... 398 Table 3-27: TP3 EYE Mask Vertices at HBR for Embedded Connection(Informative) 401 Table 3-28: TP3 EYE Mask Vertices for RBR for Embedded Connection(Informative)....402 Table4-l: Impedance Profile values for Cable assembly…………………… 408 Table 4-2: Impedance Profile Values for Cable assembly......409 Table 4-3: Mixed Mode Differential/ Common Relations of S-Parameters 410 VESA Display port Standard MEMBER USE ONLY Ver 1.2a O Copyright 2007-2012 Video Electronics Standards association Page 9 of 554 Table4-4: Downstream Port Connector Pin Assignment…………425 Table 4-5: Upstream Port Connector pin assignment 426 Table 4-6: Mating Sequence Level ...·.:·.······.·· 427 Table 4-7: Connector Mechanical Performance 着春 428 Table 4-8: Connector electrical Performance …429 Table 4-9: Connector Environment Performance 430 Table 4-10: Downstream Port mDP Connector Pin Assignment 437 Table4-1l: Upstream Port mDP Connector Pin assignment.……….…438 Table4-12; mDP Connector Mechanical Performance Requirements……………,……….450 Table 4-13: mDP Connector Electrical Performance Requirements .451 Table 4-14: mDP Connector Environment Performance Requirements........... 452 Table 4-15: Mating Sequence Level ·垂··4音·。音 457 Table 4-16: Display Port Panel-side Internal Connector Pin Assignment 462 Table 4-17: Panel-side Connector Mechanical Requirements 469 Table 4-18: Panel-side Connector Electrical Requirements.................470 Table 4-19: Panel-side Connector Environmental Requirements …470 Tablc 5-1: Display Port Colorimetry Format Support...... 音音音鲁垂 471 Table 5-3: Required Lane Count for Typical Data Projector Timings at RR/P Table 5-2: Required lane count for typical tv timings at rbr. …479 479 Tablc 5-4: DPCD Paramctcrs Branch Devicc in SST Modc may update ........... 485 Table 5-5: UP REQ EN/MST EN Setting …………492 Table 6-1: Channel to Speaker Mapping of Three Channel Audio with Ca=04h........499 Table 9-1: FAUX Electrical Parameters at the Transmitting IC Packages Pins (Informative)...504 Table 9-2: Mask Vertices for AUX CH at Transmitting IC Packages Pins(Informative)....504 Table 9-3: Mask Vertices for AUX CH at Receiving IC Packages Pins(Informative).....505 Table 9-4: FAUX Channel Topology parameters 506 Table 9-5: Upstream and Downstream Silicon RJ and dJ assumptions ········ 507 Table 9-6: DP Main Link TX Silicon Parameters(Informative) 509 Table97: DP Main link tX tpl package Pin parameters( Informative)……………….510 Table 9-8: DP Main Link RX TP4 Package Pin Parameters(Informative) 510 Table 9-9: DP Main Link Receiver(Main rX) Silicon Pads with HBR/RBR (Informative)...511 Table 9-10: DP Main Link Receiver(Main RX)RX Silicon Pads with HBR2 (Informative)..511 Table 13-1: Header Bytes of VSC Packet..... 526 Tablc 13-2: VSC Payload 527 Table13-3: EDID Ver.1.43 D Stereo Display Capability Declaration…………532 Table 13-4: DisplayID Ver. 1.1, 3D Stereo Display Capability Declaration.... 534 Tablc 13-5: 3D Sterco Display Format Supported in Display lD v1. 2 .535 Table 14-1: IDs Provided by source Device for QUERY STREAM ENCRYPTION STATUS Request message transaction 540 Table1 14-2: Stream Status Information Replied by the Branch device…………..41 Table 14-3: Stream Status Signature …542 Table 16-1: Main Contributors to Version 1. 0 .............................. 548 Table 16-2: main contributors to version 1.1 549 Table 16-3: Main Contributors to Version 1.1a 50 VESA Display port Standard MEMBER USE ONLY Ver 1.2a O Copyright 2007-2012 Video Electronics Standards association Page 10 of554 【实例截图】
【核心代码】