实例介绍
【实例简介】
vivado简明教程,对新手来说很有帮助，有助于快速上手。
新建工程 Vvad020132 File tools wind VIVADO E XILINX 2013.2 ALL PROGRAMMABLE. tting started Documentati New Proiect Documentation and Tutorials New Project 画 bIe for first time user Yye"士 Open Proiect User Guide Open Example Proiect 盘 ui ck Take videos d methodology Release otes guide .on about installation and new IDs features iP to be used in a new proj 區T 新建工程 New Prolect Create a New vivado Project This wizard will gui de you through the creation of a new project To create a Vivado project you will need to provide a name and a location for you project files. Hext, you will specify the type of flow you' ll be working with. Finally you will specify your project sources and choose a default part VIVADO 2013.2 lich Iext Back C ne> Finish 新建工程 New proiect P Tar Enter a name for your project and specify a directory where the project data files will be stored Project loc tion: D: /Project/'vivad v Create project subdirectory ect/Vivadofl Je 仁《k:xt>Ens[ cancel 新建工程 New Proiect P pecify the type of project to creat RTL Proiect You will be able to add sources, generate IP, run RTL analysis, synthesis, implementation, design planning aIk 回 Do not fy sources at this ti Post-synthesis p You will be able to add sources, view device resources, run design analysis, planning and implementation □ Do not t this time 工/0P1 Do not specify design sou You will be able to view partpackage resources Create a vivado project from a Synplify, Isf or ISE Project file Bach Finish E 新建工程 选定所用的器件 心 New Proj e￡牲 ut Part Choose a default ilin board for ect, This be changed 1 Filter Product catezo 1 Package All Family All All Sub-Family All All All Filt Osx 200tfbg 8 matches〕 I/O Pi LUT Block Part FlipFlops Count EI RAM Transceivers t r xg7200b484344 285 13480 269200 35 740 xC7a200ttb484-2 484 285 13480 269200 740 命x7a200ttbg484-2L!484 285 134800 269200 740 争xc7a200t土b284-1 285 13480 269200 740 yittazuutIbET6 7 13480289200 38 740 S xcTa200tfb2576-2 6T6 0122一5 740 7408 像xg7200be76-176 400 13480 2E92D 3E 740 Bach 新建工程 New proiect Newr Project Sunnary ①)真 new RTL project named’且ow_ demo wi1 be created Q The default part and product family for the new project Default Part: xcTa200tfbE576-2 Produc t FamilY: Ar fb25t6 Speed G: VIVADO 20132 To create the project, click Finish 《 BackRest>Pm Cancel 示例工程的內容 源代码输入 调用及例化|P 功能仿真 Chipscope例化 时钟约束 管脚锁定 工程实现 生成bit文件 示例工程的架构 FPGA 源代码 100MHZ Counter port CLK OSC port PLL SOMHZ 200MHZ DDS Chipscope P P Debug 【实例截图】
【核心代码】
vivado简明教程,对新手来说很有帮助，有助于快速上手。
新建工程 Vvad020132 File tools wind VIVADO E XILINX 2013.2 ALL PROGRAMMABLE. tting started Documentati New Proiect Documentation and Tutorials New Project 画 bIe for first time user Yye"士 Open Proiect User Guide Open Example Proiect 盘 ui ck Take videos d methodology Release otes guide .on about installation and new IDs features iP to be used in a new proj 區T 新建工程 New Prolect Create a New vivado Project This wizard will gui de you through the creation of a new project To create a Vivado project you will need to provide a name and a location for you project files. Hext, you will specify the type of flow you' ll be working with. Finally you will specify your project sources and choose a default part VIVADO 2013.2 lich Iext Back C ne> Finish 新建工程 New proiect P Tar Enter a name for your project and specify a directory where the project data files will be stored Project loc tion: D: /Project/'vivad v Create project subdirectory ect/Vivadofl Je 仁《k:xt>Ens[ cancel 新建工程 New Proiect P pecify the type of project to creat RTL Proiect You will be able to add sources, generate IP, run RTL analysis, synthesis, implementation, design planning aIk 回 Do not fy sources at this ti Post-synthesis p You will be able to add sources, view device resources, run design analysis, planning and implementation □ Do not t this time 工/0P1 Do not specify design sou You will be able to view partpackage resources Create a vivado project from a Synplify, Isf or ISE Project file Bach Finish E 新建工程 选定所用的器件 心 New Proj e￡牲 ut Part Choose a default ilin board for ect, This be changed 1 Filter Product catezo 1 Package All Family All All Sub-Family All All All Filt Osx 200tfbg 8 matches〕 I/O Pi LUT Block Part FlipFlops Count EI RAM Transceivers t r xg7200b484344 285 13480 269200 35 740 xC7a200ttb484-2 484 285 13480 269200 740 命x7a200ttbg484-2L!484 285 134800 269200 740 争xc7a200t土b284-1 285 13480 269200 740 yittazuutIbET6 7 13480289200 38 740 S xcTa200tfb2576-2 6T6 0122一5 740 7408 像xg7200be76-176 400 13480 2E92D 3E 740 Bach 新建工程 New proiect Newr Project Sunnary ①)真 new RTL project named’且ow_ demo wi1 be created Q The default part and product family for the new project Default Part: xcTa200tfbE576-2 Produc t FamilY: Ar fb25t6 Speed G: VIVADO 20132 To create the project, click Finish 《 BackRest>Pm Cancel 示例工程的內容 源代码输入 调用及例化|P 功能仿真 Chipscope例化 时钟约束 管脚锁定 工程实现 生成bit文件 示例工程的架构 FPGA 源代码 100MHZ Counter port CLK OSC port PLL SOMHZ 200MHZ DDS Chipscope P P Debug 【实例截图】
【核心代码】
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