calibre 仿真超细教程，candence没有那么难

【实例简介】
超细的CADENCE后仿真，calibre教程，手把手教会你如何后仿真
西安交通大学微电子研究所 建立工作环境 Terminal x File Edit View Terminal Tabs Help Input the following cmd to setup the different application tools For synopsys tools, type synopsys setup For Mentor Calibre tool, type calibre. setup For cadence IC, type cds. setup and then type icfb /home/ mayzh>cd Calver/ /home/mayzh/ Calver>ls Project/ csmcO5pdk/ layoutrule/ layouter. sh* readme* /home/mayzh/Calver>source layouter. sh /home/mayzh/Calver>cd -/work/ layouter/ /home/mayzh/work/layouter>ls drc/ layout/ lvs/ setup xrc/ /home/mayzh/work/layouter>cd layout/ /home/mayzh/work/layouter/layout>ls Calibre@ cds.lib display drf /home/ mayzh/work/layouter/layout>cds. setup /home/mayzhwork/layouter/layout>icfb& [1]13448 /home/mayzh/work/layouter/layout> 将 ayoutver:sh脚本拷贝到自己的目录下,并运行,建立工作环境。 进入 layouter的 ayout目录下,启动 cadence画版图,并验证 西安交通大学微电子研究所 版图设计 Virtuoso@ Schematic Editing: tmp inv schematic amd sel: 0 Tools Design Window Edit Add Check Sheet Options Migrate Calibre Help AMs opts. Analog Environment Design Synthesis VDD CSI Diva 义L np Hoopla/schematics Hierarchy Editor Mixed signal opts PCD =3u Parasitics Simulation ZN mn W=U =6u GND mouse L: schSingleSelectPt( M: schHiMousePopUp() R: schzoomFit(1.0 0. 9) 打开 schematic。选择 Tools-> Design Synthesis> Layout XL 西安交通大学微电子研究所 版图设计 Startup Option LSW Sort Edit 中p Virtuoso XL Layout Editing: tmp inv layout OK Cancel X:-12.8 V:10.000 dew ()select: 0 DRD: OFF sto2 Tools Design Window Create Edit verify Connectivity Options Place Routing Assura Compact Show Objec save Create a New, or open an existing cellView? lnst■Pn Save As 州NA3Ns y Open ◆ Create New oPen EXisting Discard edits drw Make Read Only Suml set Default Application Remaster Instances drw Plot Create New File x OK Cancel Defaults Help drw o Template tml brary Name p d Cell Name anT D dry layout r ew name d Virtuoso 四 drw mouse L: mouse SingleSelectet M: leHiMousePopUp( R: hi ZoomAbsoluteScale(hiG Library path file mayzh/work/layouter/layout/cds. lib 创建版图文件后,选择 Design-> Gen From source. 西安交通大学微电子研究所 版图设计 oK Cancel Defaults Help Layout Generation Generate: Io Pns Instances Boundary Transistor chaining Transistor Folding Preserve Mappings Apply L抛 width Height Num Create Defaults Geometric」圈1 Select. Nunber selected: 0 ed a Pir Tem Name Net Name Pin ype Layer i Master wIdth Height Num create " GND GND G已口肌e七L⊥”(“五1““pirt) C"Al""pin") 1.口 set Pin Label Text style TDI Ge。metx⊥c ("A1”"pin" 1.0 1 Geomet⊥E “盈1 1.口 DK cancel Help HeI Font stick Pin Type Layer f Master Width Height Num Create Geometric-|圈1-1:a1.aⅡ Text options Drafting Overbar Pin Label shape: Label Text Display Pin abel optionS ATTEXT Layer Name Same As Pin Boundary Layer ■ PrBndry dg Layer Purpuse o awing Left- shape: Rectangle Botto centercenter Boundary Area Estimation utilization (o) 25 spect Ratio (wTH)一 Onentation Area calculation. PRBoundary Based- Load Template File for Layout Generation 的给非 ,3 将 Boundary复选框去掉。 在 O pins处选择各端口对应的层 点击 Pin Label Options,选择标识各端口所用的层。 西安交通大学微电子研究所 版图设计 Virtuoso Schematic Editing: tmp inv schematic Virtuoso XL Layout Editing: tmp inv layout amd: move sel: 2 19.5n Y:-2E.475 (R Select: 1 DRD: OFF x: 0.000 G Tools Design window Edit Add Check Sheet options Migrate Help Tools Design Window Create Edit venty Connectivity Options Pace Routing VDD 2 mr V翻DGD图 P w=3u ZN mn MN T mn [abed] GND mmouse L: schSingleSelectPt M: schHiMousePopUp( R: leHiEditProp() mouse L: Deselect Figure 1: Point at the new location for the move 貞线提示各节点的连接关系。各器件及pn已生成,将版图的其它部分完成 西安交通大学微电子研究所 版图设计 Virtuoso XL Layout Editing: tmp inv layout :3.995Y:-11.40 (P)Select: O DRD: OFF dX:-1.070 dY:8.150 Dist:62199 amd: Stretch Tools Design Window Create Edit Venty Connectivity options Place Routing Assura Compact Calibre Help Run DRc Run DFM Run LYS ■题 Run PEX 秒國mn/象 start RVE slights Setup About ■■藤顺■ abcd mouse L: Enter point M: Pop-up Menu Select the fiqure to be stretched 西安交通大学微电子研究所 版图验证 DRC---Design Rule Checking ERC--Electrical Rule Checking LVS--Layout Versus Schematic PEX---Post-layout Extraction RVE- Results viewing Environment(显示结果用的环境窗口) SVDB- Standard verification database(LVS结果) 西安交通大学微电子研究所 版图验证一DRC ● DRC RU|e LAYOUT PATH CELLNAME gds LAYOUT PRIMARY CELLNAME layout system GDS2 DRC RESULTS DATABASE CELLNAME, drc result DRC SUMMARY REPORT CELLNAME drc summary PREciSIon 1000//min number 0.001 RESOLUtIon 5 /grid 0.001*5 【实例截图】
【核心代码】