DDR and DDR2 SDRAM High-Performance Controller User Guide.pdf

【实例简介】
DDR and DDR2 SDRAM High-Performance Controller User Guide， 介绍DDR and DDR2 SDRAM High-Performance Controller IP核及其使用
A吉RA Contents Chapter 1. About These MegaCore Functions Release informat 1-1 Device Family Support∴… 垂鲁番 ·:··· ··· Teatures General description .,,1-2 Megacore verification 1-3 Performance and Resource Utilization 1-4 Installation and licensing Open Core plus evaluati 1-7 Open Core plus time-Out behavior .,18 Chapter 2. Getting started Design Flow 2-1 Select flow 2-2 SOPC Builder flow Specify parameters ··· Complete the sopc builder System Simulate the system 2-4 MegaWizard Plug-In Manager Flow Specify Parameters.…… ∴....2-5 Simulate the Example design ...,,,.2-8 Simulating Using nativeLink.................. ....2-8 IP Functional simulations 2-9 Compile the design Program Device and Implement the Design 2-13 ,,,,,,214 Chapter 3. Parameter Settings Memory Settings 1 PHY Settings 3-1 Controller settings 番鲁看 Chapter 4. Functional Description Block Description 4-2 Command FIFo ··· 4-3 Write data FIfo Write Data Tracking logic ·· 4-3 Main state machine .··:;· Bank management logic Timer logic ,·········· 43 Initialization State Machine 4-4 Address and command decode 4-4 PHY Interface Logic ,,,4-4 ODT Generation logic ,····. 4-4 Low Power Mode logic ·,······ 4-4 Control logic 4-5 Error Correction Coding(ECC) ,4-7 Interrupts 4-9 o March 2009 Altera corporation DDR and DDR2 SDRAM High-Performance Controller User Guide 4-9 Partial Bursts 4-10 ECC Latency ...4-10 Example desigr 4-11 Example driver 4-12 Interfaces and Signals 4-14 Interface Description ..4-14 Full Rate write, Avalon-MM Interface Mode 4-14 Full rate write, Native Interface Mode-Non-Consecutive write 4-17 Half rate Write, Avalon-MM Interface mode 4-20 Half rate write. Native interface mode 4-22 Full Rate rcad, Avalon -MM Interface Mode 425 Half Rate Read, Native Interface Mode Half Rate Read, Avalon-MM Inter face Mode--Non-Consecutivekeao 4-27 ,,,,,,,,428 Full rate, Native Interface Mode-Alternate Read-Write ,,4-31 User refresh ce 4-34 Self-Refresh and Power-Down Commands ...4-35 Auto-Precharge Commands 4-36 4-37 Chapter 5. Example Design Walkthrough Creating A Simulation Testbench Environment 5-1 Creating the example project 5-1 Configuring the DDR2 SDRAM High-Performance Controller 5-1 Understanding the Example Design and Testbench 5-2 Testbench Descriptive 5-2 Running the Example Testbench from Your Simulator∴……………… The Testbench Stages......... Memory device initialization Functional Memory Use·… Appendix A. ECC Register Description ECC Registers .,,,,,,,,A-1 Register Bits A-3 Additional information Revision history Info-1 How to contact altera 着垂 ,,,,,,,,,Info-1 Typographic Conventions nfo-2 DDR and DDR2 SDRAM High-Performance Controller User Guide o March 2009 Altera Corporation A吉RA 1. About These MegaCore Functions Release Information Table 1-1 provides information about this release of the ddr and ddr2 Sdram High-Performance Controller mega core@ functions Table 1-1. ddR and ddR2 SDRAM High-Performance Controller Release Information Item Description ∨ ersion 9.0 Release date March 2009 Ordering codes P-SDRAM/HPDDR(DDR SDRAM) IP-SDRAM/HPDDR2(DDR2 SDRAM) Product ids 0OBE (DDR SDRAM) 0OBF (DDR2 SDRAM) OOCO (ALTMEMPHY Megafunction Vendor d 6AFZ Altera verifies that the current version of the quartus ii software compiles the revious version of each MegaCore function. The MegaCore IP Library release notes and Errata report any exceptions to this verification. Altera does not verify compilation with Mega Core function versions older than one release Device Family Support Mega Core functions provide either full or preliminary support for target Altera device families, as described below Full support means the Mega Core function meets all functional and timing requirements for the device family and may be used in production designs Preliminary support means the Mega Core function meets all functional requirements but may still be undergoing timing analysis for the device family it may be used in production designs with caution Table 1-2 shows the level of support offered by the DDr and DDR2 SDRAM high performance controller to each of the Altera device families Table 1-2. Device Family Support(Part 1 of 2) Device Family Support Arrive gⅩ Fu‖ Arria II GX Preliminary Cyclone‖ Fu‖ Hard copy Full Hardcopy Ill Preliminary Hard copyⅣE Preliminary C March 2009 Altera Corporation DDR and DDR2 SDRAM High-Performance Controller User Guide 1-2 Chapter 1: About These Mega core Functions Features Table 1-2. Device Family Support(Part 2 of 2) Device Family Support Stratixo II Full Stratix‖GX Ful‖l Stratix‖ Full Stratix IV Preliminary Other device families No support Features a Integrated error correction coding(ECc) function Power-up calibrated on-chip termination(OCT) support for Cyclone Ill, Stratix Ill, nd Stratix iv dev Full-rate and half-rate support SOPC Builder ready Support for ALTMEMPHY megafunction a Support for industry-standard DDR and DDR2 SDRAM devices; and registered and unbuffered dImms Optional support for selt-refresh and power-down commands a Optional support for auto-precharge read and auto-precharge write commands Optional user-controller refresh a Optional Avalon Memory-Mapped(Avalon -MM) local interface a Optional Altera PHY interface(AFI)Controller- PHY Interface Optional multiple controller clock sharing in SOPC Builder flow Easy-to-use Mega wizardTM interface Support for Open Core Plus evaluation Support for the quartus II IP Advisor IP functional simulation models for use in Altera-supported VHDL and Verilog HDL Simulators General Description The Altera DDR and DDR2 SDRAM High-Performance Controller MegaCore unctions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The Mega Core functions work in conjunction with the Altera ALTMEMPHY megafunction For more information on the ALTMEMPHY megafunction, refer to the External Memory Phy Interface Megafunction User Guide(ALTMEMPHy) DDR and DDR2 SDRAM High-Performance Controller User Guide o March 2009 Altera Corporation Chapter 1: About These MegaCore Functions MegaCore verification Figure 1-1 on page 1-3 shows a system-level diagram including the example design that the ddR or dDr2 SDRAM High-Performance Controller Mega Core functions create for you. Figure 1-1. System-Level Diagran Example Design Control (Encrypted) Local DDR/DDR2 Interface Pass or fail Example DriverKt DRAM Interface DDR/DDR2 SDRAM ALTMEMPHY Megafunction P山 DLL DDR/DDR2 SDRAM High-Performance Controller Note for Figure 1-1 (1)When you choose Instantiate DLL EXternally, DLL is instantiated outside the controller. The mega wizard plug-In manager generates an example design consisting of an example driver, and your DDR or DDR2 SDRAM high-performance controller custom variation. The controller instantiates an instance of the altmemphy megafunction which in turn instantiates a PLL and DLL. You can optionally instantiate the dll outside the altmemphy megafunction to share the dll between multiple instances of the altmEMPHY megafunction The example design is a fully-functional design that you can simulate, synthesize, and use in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass /fail and test complete signals MegaCore Verification Mega core verification involves simulation testing Altera has carried out extensive random, directed tests with functional test coverage using industry-standard Denali models to ensure the functionality of the DDR and DDR2 SDRAM high-performance controller. In addition, Altera performs a wide variety of gate-level tests of the DDr and DDR2 SDRAM high-performance controllers to verify the post-compilation unctionality of the controllers C March 2009 Altera Corporation DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 1: About These Mega core Functions Performance and resource utilization Performance and resource utilization Table 1-3 shows maximum performance results for the ddr and ddR2 sdram high-performance controllers using the Quartus II software, version 9.0 with Arria Gx, Cyclone ill, hard copy ll, stratix Il, Stratix Il GX Stratix II, and stratix IV devic Table 1-3. Maximum performance for half rate and full rate controllers System fMAx MHz) DDR SDRAM DDR2 SDRAM Device Half rate Full rate Half rate Ful rate Arria gⅩ 200 167 233 167 Cyclone Ill 167 167 200 167 HardCopy ll 200 200 267 267 Stratix‖ 200 200 333 267 Stratix‖GⅩ 200 200 333 267 Stratix‖ 200 200 400 267 StratixⅣV 200 20400 267 e For more information on device performance, refer to the relevant device handbook Table 1-4 shows typical sizes for the dDr or dDR2 SDRAM high-performance controller in AFI mode (including ALTMEMPHY) for Arria GX devices Table 1-4. Resource Utilization in Arria gx devices Memory Local Data Memory Width Combinational Dedicated Logic Controller Rate Width(Bits) its) ALUTS Registers M512 M4K Half 32 1,851 1.562 2 64 16 1,904 1,738 4 256 64 2,208 2,783 15 288 2,289 2,958 4 Full 32 1,662 1,332 6 64 16 1.666 1,421 3 256 64 1738 1,939 288 72 1,758 2.026 DDR and DDR2 SDRAM High-Performance Controller User Guide o March 2009 Altera Corporation Chapter 1: About These MegaCore Functions 1一5 Performance and resource utilization Table 1-5 shows typical sizes for the DDR or DDR2 SDRAM high-performance controller in AFI mode(including ALTMEMPHY) for Cyclone Ill devices Table 1-5. Resource Utilization in Cyclone Ill Devices Local Data Width Memory Width Combinational Dedicated Logic Memory Controller rate (Bits) ( Bits ALUTS Registers (M9K) Half 32 8 2.683 64 16 2,905 1,760 256 64 4,224 2938 288 72 4.478 3,135 18 Full 32 2386 1,276 64 16 2,526 1,387 256 64 3,257 2037 9 72 3,385 2.146 Table 1-6 shows typical sizes for the Ddr or DDr2 SDRAM high-performance controller in aFi mode(including ALTMEMPHY) for Stratix II and Stratix II GX devices Table 1-6. Resource Utilization in stratix ll and stratix II GX Devices Memory Local Data Memory Width Combinational Dedicated Logic Controller Rate Width(Bits) (Bits) ALUTS Registers M512 M4K Half 32 8 1.853 1,581 64 1,901 1.757 4 256 64 2,206 2.802 288 2,281 2,978 17 Full 1.675 1371 64 16 1,675 1456 44546334 256 64 1740 1976 0399 288 1.743 2,062 C March 2009 Altera Corporation DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 1: About These Mega core Functions Performance and resource utilization Table 1-7 shows typical sizes for the DDR or DDR2 SDRAM high-performance controller in AFI mode (including ALTMEMPHY) for Stratix Ill devices Table 1-7. Resource Utilization in stratix Ill Devices Local date Memory Width Combinational Dedicated Logic Memory Controller Rate Width(Bits) Bits ALUTS Registers (M9K 32 1,752 1,432 64 16 1,824 1,581 256 64 2,210 2,465 9 288 72 2,321 2,613 10 1.622 1351 64 16 1,630 1,431 2 256 64 1,897 288 72 1749 1,975 Table 1-8 shows typical sizes for the ddr or ddr2 SDRaM high-performance controller in aFI mode(including ALTMEMPHY) for Stratix IV devices Table 1-8. Resource Utilization in Stratix IV Devices Local Data Memory Width Combinational Dedicated Logic Memory Controller Rate Width(Bits) (Bits) ALUTS Registers (9K) Half 1.755 1,452 64 16 1.820 1597 256 2,202 2457 288 2,289 2,601 32 8 1.631 1369 64 16 1,630 1448 256 64 1731 1906 288 1743 1983 DDR and DDR2 SDRAM High-Performance Controller User Guide o March 2009 Altera Corporation 【实例截图】
【核心代码】