MIPI CSI2 V1.3

【实例简介】
该文档为mipi_CSI-2_specification v1.3的协议，有需要的可以参考一下，很不错的文档
Version 1. 3 fication for cSI-2 29-Mav-2014 Contents Contents. Figures… XII Release history..,,,…,……,il 1 Introduction seems. cope .2 Purpose......,., 2 Terminology… 2. 1 Use of Special Terms 2.2 Definitions 222 2.3△ abbreviations 2.4 Acronyms 3 References . 4 Overview of cSI-2 5 CSI-2 Layer Definitions 6 Camera Control Interface(CCD) 6.1 Data Transfer protocol 6.1.1 Message Type…… 6.1.2 Read/Write Operations............................12 6.2 CCI Slave Addresses 6.3 CCI Multi-Byte Registers 6.3.1 Overview ··.····· .15 6.3.2 The Transmission Byte Order for Multi-byte Register values.............17 6.3.3 Multi-Byte Register Protocol 18 .4 Electrical Specifications and Timing for 1/O Stages…………..……...2 7 Physical Layer…,,...,..,,…,26 7.1D- PHY Physical Layer Option……… 6 7.2 C-PHY Physical Layer Option 26 8 Multi-- Lane Distribution and merging…..….….….….28 8.1 Lane Distribution for the D-PIlY Physical Layer Option 8.2 Lane Distribution for the C-PhY Physical Layer Option 35 8.3 Multi-Lane Interoperability 9 Low Level Protocol 39 9.1 Low Level protocol Packet Format 91.1 Low Level protocol long Packet Forma…… 39 39 9.1.2 Low Level protocol short Packet Format.......... 44 9.2 Data Identifier (di .45 9.3 Virtual Channel Identifier 45 9.4 Data Type ( Dt) 46 9.5 Packet Header Error Correction Code for D-PHY Physical Layer Option......46 9.5.1 General Hamming Code Applied to Packet Header 47 15-2014 MIPI Alliance. In All rights Confidential Specification for CSI-2 Ⅴ ersion1.3 29-May-2014 9.5.2 Hamming- Modified Code…………,.….,.……,,.……,….………...148 9.5.3 ECC Generation on TX Side 垂垂垂,垂音中垂 9.5.4 Applying ECC on RX Side 垂垂卡垂 9.6 Checksum Generation 53 9.7 Packet spacing 9.8 Synchronization Short Packet Data Type Codes. 9.8. 1 Frame Synchronization Packets 56 9.8.2 Line Synchronization Packets 57 9.9 Generic Short Packet Data Type Codes …57 9.10 Packet Spacing Examples 57 9.1 Packet Data Payload Size rules……………,….,.,,..…… .60 9 12 Frame Format Examples ···········; 9.13 Data Interleaving 9.3.1 Data Type Interleaving…………… 9.13.2 Virtual Channel Identifier Interleaving 66 10 Color Spaces…,.,,.,,.,.,.,.,..,,,68 10.1 RGB Color Space Definition 68 0.2 YUV Color Space Definition 68 11 Data formats…69 11.1 Generic 8-bit Long Packet Data Types 70 11.1 Null and blanking data...... 70 11.1.2 Embedded Information 70 11.2 YUV Image Data… 11.2.1 Legacy YUV4208-bit........12 11.2.2YUV4208-bit 74 11.2.3YUV42010-bit..……………76 11.24YUV4228-bit 78 11.2.5YUV42210-bit 80 11.3 RGB Image Data. 11.3.1RGB888 11.3.2RGB666. 11.3.3RGB565.84 11.34RGB555 11.3.5RGB444 .86 11.4 RAW Image Data 11.4.1RAW6 音·音 ······+···:········· b 87 114.2RAW7 88 11.4.3RAW8. 14.4RAW10 90 11.4.5RAW12 114.6RAW14. 92 11.5 User Defined Data formats 12 Recommended memory storage.eooooooooooecooooooooeeooooo00080000000000000000000000008000006696 12.1 General/ Arbitrary Data Reception……………………………… …96 12.2 RGB888 Data Reception....... .96 2.3RGB666 Data Reception…… ··· 12.4 RGB565 Data recepti .98 15-2014 MIPI Alliance. In All rights Confidential Version 1. 3 fication for cSI-2 29-Mav-2014 12.5 RGB555 Data Reception 12.6 RGB444 Data Reception ·中垂 .98 7 YUV422 8-bit Data Reception 12.8 YUV422 10-bit Data Reception 99 12.9YUV4208-bit( Legacy) Data Reception………… 100 12.10 YUV420 8-bit Data Reception 12.11 YUV420 10-bit Data Reception 102 12.12 RAW6 Data Reception 104 12.13 RAW7 Data Reception.. ……104 12 14 RAW8 Data Reception 12.15RAW10 Data Reception.....,…,,,,…05 12.16 RAW12 Data Reception.. ···········; 105 12. 17 RAW14 Data Reception 106 AnnexA JPEG8 Data format( informative)……,…,…,,,,,,107 A 1 Introduction 107 A2 JPEG Data definition 107 A 3 Image Status Information 108 A 4 Embedded Images a.5 JPEG8 Non-standard Markers .10 A6 JPEG& Data Reception 111 Annex b CSI-2 Implementation Example(informative) 112 B.1 Overview………………………………… 112 B2 CSI-2 Transmitter Detailed Block Diagram 112 B 3 CSI-2 Receiver Detailed Block Diagram 113 B 4 Details on the d-phy implementation 114 B 4. 1 CSI-2 Clock Lane Transmitter 115 B 42 CSI-2 Clock Lane receiver 116 B 4.3 CSI-2 Data Lane Transmitter............................. 117 B 4.4 CS[-2 Data Lane receiver Annex C CSl-2 Recommended Receiver Error Behavior (informative)...121 C1 Overview C 2 D-PHY Level error 121 Packet Level error 122 C4 Protocol Decoding Level error.....…….….……….….…….…..123 Annex d CSI-2 Sleep mode D1 Overview ····::····:········+··········· .····· 124 D.2SLMCommandPhase..124 D.3 SLM Entry phase… …124 D 4 SLM ExIt Phase 125 AnnexE Data Compression for RAW Data Types( normative)……………26 E 1 Predictors ...........................................................................................127 E.I Predictor l ··········“········+·;·· 128 E.1.2 Predictor 128 E.2 Encoders∴.…………128 E2.1 Coder for10-8-10 Data Compression…… 129 E.2.2 Coder for 10-7-10 Data Compression………… 130 Copyright C) 2005-2014 MIPI Alliance, Inc All rights reserved Confidential Specification for CSI-2 Ⅴ ersion1.3 29-May-2014 E 2.3 Coder for 10-6-10 Data Compression ...........................132 E. 2. 4 Coder for 12-8-12 Data Compression 134 E.2.5 Coder for 12-7-12 Data Compression 136 E 2.6 Coder for 12-6-12 Data Compression ········· 139 E.3 Decoders………… 141 E.3. 1 Decoder for 10-8-10 Data Compression .141 E.3.2 Decoder for 10-7-10 Data Compression 143 E. 3. 3 Decoder for 10-6-10 Data Compression 1145 E.3.4 Decoder for 12-8-12 Data Compression 148 E.3.5 Decoder for 12-7-12 Data Compression 150 E.3.6 Decoder for 12-6-12 Data Compression Annex F JPEG Interleaving(informative)………,,…,,…,,,,,157 15-2014 MIPI Alliance. In All rights Confidential Version 1. 3 Specification for CSI-2 29-Mav-2014 Figures Figure 1 CSi-2 and CCI Transmitter and Receiver Inter face for D-PHY 7 Figure 2 CSi-2 and CCI Transmitter and receiver Interface for C-PhY 着垂 Figure 3 CSI-2 Layer Definitions Figure 4 CCI Message Types..... 12 Figure 5 CCI Single read from Random Location......... 12 Figure6 CCI Single read from Current Location……… Figure 7 CCI Sequential Read Starting from a Random location 13 Figure8 CCI Sequential Read Starting from the Current Location…………….14 Figure 9 CCi Single write to a random location .14 Figure 10 CCI Sequential Write Starting from a Random Location 15 Figure ll Corruption of a 32-bit Wide Register during a read message 16 Figure 12 Corruption of a 32-bit Wide register during a Write Message 17 Figure 13 Example 16-bit Register Write ·:··:······· 17 Figure I4上 Xample32- bit Register Write( address not shown)…… Figure 15 Example 64-bit Register Write(address not shown) 18 Figure 16 Example 16-bit Register Read 19 Figure 17 Example 32-bit Register Read 20 Figure18 Example 16- bit Register Write…… Figure 19 Example 32-bit Register Write Figure 20 CCI Timing.. 25 Figure 2 1 Conceptual Overview of the Lane distributor Function for D-PHY. ...................28 Figure22 Conceptual Overview of the Lane distributor Function for C-Phy………………29 Figure 23 Conceptual Overview of the Lane Merging Function for D-PhY 30 Figure 24 Conceptual Overview of the Lane merging Function for C-PIlY ,31l Figure 25 Two Lane Multi-Lane Example for D-PhY 32 Figure 26 Three Lane Multi-Lane Example for D-PhY 3 Figure 27 N-Lane Multi-Lane Example for D-PHY ·;·········+·········;· 34 Figure28N- Lane mult-Lane上 xample for D- PHY Short packet transmission………35 Figure 29 Two Lane Multi-Lane Example for C-PhY 36 Figure 30 Three Lane Multi-Lane Example for C-PhY 356 Figure 3 1 General N-Lane Multi-Lane Distribution for C-PHY 36 Copyright C) 2005-2014 MIPI Alliance, Inc VIl All rights reserved Confidential Specification for CSI-2 Ⅴ ersion1.3 29-May-2014 Figure 32 One Lane Transmitter and n- Lane receiver example for D-PhY .37 Figure 33 M-Lane Transmitter and N-Lane Receiver Example(M<n for D-PhY......37 Figure34M- Lane transmitter and One Lane receiver Example for D-PHY……… Figure 35 M-Lane Transmitter and N-Lane receiver Example(N<M)for D-PhY 38 Figure 36 Low Level Protocol Packet Overview 39 Figure 37 Long Packet Structure for D-PHY Physical Layer Option Figure 38 Long packet Structure for C-PhY Physical Layer Option..............41 Figure 39 Packet Header Lane Distribution for c-PhY Physical Layer Option 41 Figure 40 Minimal Filler Byte Insertion Requirements for Three Lane C-Plly Figure4 I Short packet structure for D- PHY Physical Layer Option……….….…...4 Figure 42 Short Packet Structure for C-PHY Physical Layer Option 44 Figure 43 Data Identifier Byte 45 Figure 44 Logical Channel Block Diagram(Receiver) Figure 45 Interleaved Video data Streams Examples 46 Figure 46 24-bit ECC Generation Example 。,垂,··“,····垂 ········· Figure 4764-bit ECC Generation on TX Side 51 Figure 48 24-bit ECC Generation on TX Side Figure4964 bit ECC on rX Side Including Error Correction.……… 555 Figure 50 24-bit ECC on RX Side Including Error Correction Figure 51 Checksum Transmission Byte Order......53 Figure 52 Checksum Generation for long packet Payload data …54 Figure 53 Definition of 16-bit CRC Shift register 54 Figure 54 16-bit CRC Software Implementation Example 垂·垂 Figure 55 Packet Spacing 56 Figure 56 Multiple Packet Example 58 Figure 57 Single Packet Exampl 58 Figure 58 Line and frame blanking definitions 59 Figure 59 Vertical Sync exampl Figure 60 Horizontal Sync Example ·· 600 Figure bl General Frame Format Example.....................61 Figure 62 Digital Interlaced Video Example Figure 63 Digital Interlaced Video with Accurate Synchronization Timing Information Figure 64 Interleaved Data Transmission using Data Type value 15-2014 MIPI Alliance. In All rights Confidential Version 1. 3 fication for cSI-2 29-Mav-2014 Figure 65 Packet Level Interleaved Data Transmission Figure 66 frame Level Interleaved data Transmission 66 Figure 67 Interleaved Data Transmission using Virtual Channels Figure 68 Byte Packing Pixel Data to C-PHY Symbol lllustration 70 Figure 69 Frame Structure with Embedded data at the beginning and end of the frame Figure 70 Legacy YUV420 8-bit Figure 71 Legacy YUv420 8-bit Pixel to Byte Packing Bitwise Illustration. Figure 72 Legacy YUV420 Spatial Sampling for H.261, H 263 and MPEG 1 Figure 73 Legacy YUV420 8-bit Frame Format 74 Figure 74 YUV420 8-bit Data Transmission Sequence 74 Figure 75YUV4208-bit Pixel to Byte Packing Bitwise Illustration 75 Figure 76 YUV420 Spatial Sampling for H. 261, H263 and MPEG I...........75 Figure 77YUV420 Spatial Sampling for MPEG 2 and MPEG 4 76 Figure 78YUV420 8-bit Frame Format 176 Figure 79 YUV420 10-bit Transmission Figure 80 YUV420 10-bit Pixel to Byte Packing Bitwise Illustration 77 Figure 81 YUV420 10-bit Frame Format........78 Figure 82 8-bit Transmission 78 Figure 83 YUV422 8-bit Pixel to Byte Packing Bitwise Illustration Figure 84YUV422 Co-sited Spatial Sampling 79 Figure85Y∪V428- bit frame format.…….… 830 Figure 86YUV422 10-bit Transmitted Bytes 80 Figure 87YUV422 10-bit Pixel to Byte Packing Bitwise Illustration Figure88YUⅤ42210- bit frame format.…….…… 81 Figure 89 RGB888 Transmission... Figure 90 RGB888 Transmission in CSl-2 Bus Bitwise Illustration figure 91 RGB888 Frame Format Figure 92 RGB666 Transmission with 18-bit BGR Words ·+·+·++“ Figure93RGB666 Transmission on CSi-2 Bus bitwise illustration……………4 Figure 94 RGB666 Frame Format.................. 84 Figure 95 RGB565 Transmission with 16-bit BGR Word 5 Figure 96 RGB565 Transmission on Csi-2 Bus bitwise lllustration 85 Figure97RGB565 Frame Format……. 85 Copyright C) 2005-2014 MIPI Alliance, Inc All rights reserved Confidential Specification for CSI-2 Ⅴ ersion1.3 29-May-2014 Figure 98 RGB555 Transmission on CSI-2 Bus Bitwise Illustration.......86 Figure 99 RGB444 Transmission on CSI-2 Bus Bitwise Illustration 86 Figure 100 RAW6 Transmission Figure 101 RAW6 Data Transmission on CSI-2 Bus Bitwise Ilustration .88 Figure 102 RaW Frame Format 88 Figure 103 RAW7 Transmission .88 Figure 104 RAW7 Data Transmission on CSI-2 Bus Bitwise Illustration ...............89 Figure 105 RAW7 Frame Format 9 Figure 106 RAW8 Transmission 89 Figure107RAw8 Data Transmission on csl-2 Bus bitwise illustration………….9 Figure 108 RAW8 Frame Format .90 Figure 109 RAW10 Transmission 90 Figure 110 RAW1O Data Transmission on CSl-2 Bus Bitwise Illustration Figure lll raWls Frame Format Figure 112 RAW12 Transmission 。,垂,··“,····垂 ········· 92 Figure 113 RAW12 Transmission on CS-2 Bus Bitwise Illustration Figure 114 RaW12 Frame Format Figure 115 RAW14 Transmission Figure 116 RAW14 Transmission on CSI-2 Bus Bitwise Illustration Figure 117 RaW14 frame Format Figure 118 User Defined 8-bit Data(128 Byte Packet Figure 119 User Defined &-bit Data Transmission on csi-2 Bus bitwise Illustration 94 Figure 120 Transmission of User Defined 8-bit Data 94 Figure12 I General/ Arbitrary Data Reception…………….………….96 Figure 122 RGB888 Data Format Reception 97 Figure 123 RGB666 Data Format Reception .97 Figure124RGB565 Data Format Reception………… 8 Figure 125 RGB555 Data Format Reception ·· 98 Figure 126 RGB444 Data Format Reception …9 Figure 127YUV4228-bit Data Format Reception ....................................................99 Figure 128 YUV422 10-bit Data Format Reception 100 Figure 129YUv420 8-bit Legacy Data Format Reception 101 Figure I30YUV4208- bit Data Format Reception…………… 15-2014 MIPI Alliance. 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