Writing Testbenches using systemverilog.pdf

【实例简介】
verilog编写testbench国外经典教材 Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing
Writing Testbenches using systemverilog b Janick Bergeron S ynopsys, Inc. Springer Janick bergeron Verificationguild. com Writing Testbenches Using System Verilog Library of congress control Number: 2005938214 ISBN-10:0-387-29221-7 ISBN-10:0-387-31275-7(e-book ISBN-13:9780387292212 ISBN-13:9780387312750(e-book) Printed on acid-free paper c 2006 Springer Science+ Business Media, Inc All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher(Springer Science+ Business Media, Inc, 233 Sprin Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights Printed in the united states of america 987654321 springer. com TABLE OF CONTENTS About the cover l Preface Why This Book Is Important What This book is about ........... xvi What Prior Knowledge You Should Have .... xviii Reading Paths∴……∴∴……,xvil Why System Verilog? VHDL and verilog Hardware Verification Languages Code examples For more information ............ xxii Acknowledgements XXII CHAPTER 1 What is verification? hat is a Testbench The Importance of verification Reconvergence model The human factor Writing Testbenches using System Verilog Table of contents Redundancy What Is Being Verified? 7 Equivalence checking∴…∴……………∴…8 Property Checking∴…∴…∴ Functional verification ,,I0 Functional Verification Approache Black-Box verification White-Box Verification ........ 13 Grey-Box verification Testing Versus Verification 15 Scan-Based testi Design for Verific Design and Verification reuse Reuse is about trust 1 8 for reuse 19 Verification reuse 19 The Cost of verification 20 ummary ,,,,,,.22 CHAPTER 2 Verification Technologies 23 Linting ,24 The limitations of linting Technologi∴……∴.25 Linting System verilog source code 27 Code reviews 29 Simulat 29 Stimulus and response 30 Event-Driven simulation .......................31 Cycle-Based simulation Co-Simulators Verification intelle Property 38 Waveform Viewers 39 Code Coverage 41 Statement Coverage......... .43 Path co Expr erage FSM Coverage What Does 100 Percent Code Coverage Mean? ,48 Functional Coverage ,,,49 Writing Testbenches using Sys g Coverage Points ............... 51 Cross Coverage 53 Transition Cover ···· 53 What Does 100 Percent Functional Coverage Mean?. 54 Verification Language Technologies .............55 assertions ●·鲁 57 Simulated assertions 58 Formal Assertion proving∴…∴…………59 ReⅤ sion control The Software Engineering Experience∴… 6 Configuration Management Working with releases .........................65 Issue Tracking What is an is 67 The grapevine system ,,,,,,,,,,,,68 The Post-It System 68 The procedural system Computerized system Metrics,,。,,,,,,,,,,,,,,, Code-Related metrics Quality- Related metrics…∴∴…∴…………….73 nterpreting Metrics∴∴∴∴…∴∴74 Summary 76 ChaPTeR 3 The Verification Plan 77 The role of the verification plan ........ 78 Specifying the verification 鲁鲁鲁 ..,.78 Defining First-Time Success 。鲁鲁鲁鲁 Levels of verification Unit- Level verification.……… 8 Block and Core Verification ,,,82 ASIC and FPGA verification.…∴ System-Level verification .......................84 Board- Level verification∴∴…… 85 Verification Strategies ●。鲁 86 Verifying the response∴………………………86 From Specification to Features∴∴∴∴∴87 Block-Level feati 90 System-Level features 91 Writing Testbenches using System Verilog Table of contents Error Types to Look For Prioritize,,,,,,,,,,,,,,,, .92 Design for ver Directed Testbenches Approach∴∴…∴.96 Group into Testcases∴ ,,96 From testcases to Testbenches Verifying Testbench Measuring Progress…∴…∴…………∴……l00 Coverage-Driven Random-Based Approach 101 Measuring progress∴..…∴.……………l01 From Features to Functional Coverage∴……103 From features to Testbench 05 From features to generators ................107 Directed testcases .,,l09 Summary ,,111 CHAPTER 4 High-Level modeling 13 High-Level versus RTL Thinking ...............113 Contrasting the approaches∴∴……∴…∴….Il5 You gotta Have style! ........................117 A Question of discipline∴.∴∴……∴…….I17 Optimize the right Thing ,I18 Good Comments Improve Maintainability ,,Ⅰ21 Structure of High-Level Code ......... 122 Encapsulation Hides Implementation Details ... 122 Encapsulating Useful Subprograms.∴…∴….125 Encapsulating Bus-Functional Models 127 Data abstraction ●鲁鲁··鲁 130 2- state Data types∵… Struct. Class 131 Union Arrays l39 Q teles 1 4I Associative Arrays .............. 143 From High-Level to Physical-Level Object-Oriented Programming ........ 147 l47 Inheritance Writing Testbenches using System Verilog Polymorphisn…………∴…∴……∴……l56 g 15 Connectivity, ime and Concurrency∴.…∴….l60 The Problems with Concurrency ..,l60 Emulating Parallelism on a Sequential Processor .. 162 The simulation Cycle l63 Parallel vs. Sequential 169 ForkJoin Statement 70 The Difference Between Driving and Assigning ... 173 Race Conditions 176 Read write race conditions .............177 Write/Write race Conditions I80 Initialization rac l82 Guidelines for Avoiding Race Conditions l83 Semaphores ,,Ⅰ84 Portability Issues ............. 186 Events from Overwritten Scheduled values .,Ⅰ86 Disabled scheduled values .....................187 Output Arguments on Disabled Tasks∴∴…188 Non-Re-Entrant Tasks 88 Static vs. Automatic variables ..................193 S ummary 196 CHAPTER 5 Stimulus and response 197 Reference Signals..…∴…∴∴,198 Time resolution is 199 Aligning Signals in delta-imne∴.……∴…….201 Asynchronous Reference signal 203 .205 Random generation of Reference Signal Parameters 206 Applying re 208 Simple stimulus ,,,,,,,,,,,,,,,.212 Applying Synchronous Data Values∴∴…∴.2l2 Abstracting Waveform generation 214 Simple output 216 isual Inspection of response∴…∴…… 217 Producing simulation Results .......... 217 Minimizing sampling∴…∴∴ 219 Visual Inspection of Waveforms∴… 220 Writing Testbenches using System Verilog Table of contents Self-Checking Testbenches 221 nput and Output vectors∴∴∴……∴ ,221 Self-Checking Operations ,,,224 Complex stimulus 227 Feedback Between Stimulus and design.…∴228 Recovering from Deadlock 228 Asynchronous Interfaces ..,,,231 Bus-Functional models .,234 CPUT7 ansactions,,,,,,,,,,,,,,,,,,,,234 From Bus-Functional Tasks to Bus-Functional Model 236 Physical Interface .238 Configurable Bus-Functional Models 243 246 Autonomous monitors ,,,,249 Slave generators.,,,,,,,,,,,,,,,,,.,,253 Multiple possible transactions .255 Transaction-Level Interface ,,,,258 Procedural Interface vs Dataflow Interface 259 What is a transaction?............. 263 Blocking transacti 265 Nonblocking transactions 265 Split transactions 267 Exceptions ,270 ummary ,278 CHAPTER 6 Architecting Testbenches 279 Verification ha 280 Design Configurat Abstracting Design Configuration ,,,,,,285 Configuring the design∴……∴……∴…….288 Random Design Configuration 290 Self-Checking Testbenches .......... 292 Hard Coded response∴……∴…… 294 Data Tagging∴∴∴∴…………∴∴……..295 Reference Model ,,,,,,,,,,.297 Transfer Functio 299 Scoreboarding ,,,,,,,300 Integration with the Transaction layer ...........302 Writing Testbenches using System Verilog 【实例截图】
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