实例介绍
【实例简介】
S32K-RM是开发必备手册，芯片所有的资源都有介绍，非常详细。
Contents Section number Title Page Chapter 1 About this manual 1.1 Audience 49 1.2 Organization.… 1.3 Module descriptions 49 1.3.1 Example: chip-specific information that clarifies content in the same chapter 50 1.3.2 Example: chip-specific information that refers to a different chapter 51 1.4 Register descriptions…… 1. 5 Conventions ·······44·+·····:.·.·.·4+····· 1. 5.1 Notes. Cautions 1.5.2 Numbering systems.. 53 1.5.3 Typographic notation 54 1.5.4 Special terms… 54 Chapter 2 Introduction 2.1 Overview 2.2 S32KIxx Series introduction 57 2.2.1S32K14x. 2.2.2S32K11x…. ….59 2.3 Feature summary……………… 60 2. 4 Block diagram 63 2.5 Feature comparison.......................... 64 2.5.1 Differences between s32K14x and S32Kllx .66 26 Applications…… 6 2.7 Module functional categories.... 2.7.1 Arm Cortex-M4F Core modules 2.7.2 Arm Cortex-MO+ Core modules 70 2.7.3 System modules. 70 S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 2.7.4 Memories and memory interfaces 2.7.5 Power Management 2.7.6 Clocking.. 2.7.7 Analog modules 2.7.8 Timer modules 73 2.7.9 Communication interfaces ..…74 2.7.10 Debug modules Chapter 3 Memory Map 3.1 Introduction.… .7 3.2 SRAM memory map.... 3. 2.1 S32K14X: SRAM memory map 3.2.2 S32KIlx: SRAM memory map 77 3.3 Flash memory map...... 78 3.4 Peripheral bridge(AIPS-Lite) memory map……… 78 34.1Read- after- write sequence and required serialization of memory operations.….…...….….….….…...:79 3.5 Private Peripheral Bus(PPB) memory map. .80 3.6 Aliased bit-band regions for CM4 core Chapter 4 Signal Multiplexing and Pin Assignment 4.1 Introduction ····+:·.··········· ················ 4.2 Functional description. 4.3 Pad description 4.4 Default pad state... .85 4.5 Signal multiplexing sheet..........................86 4.5.1 IO Signal Table 86 4.5.2 Input muxing table 88 4.6 Pinout diagrams 89 Chapter 5 Security Overview S32K1xx Series Reference manual. rev 8. 06/2018 NXP Semiconductors Section number Title Page 5.1 Introduction 91 5.2 Device security 91 5.2. 1 Flash memory security. 5.2.2 Cryptographic Services Engine(CSEc) security features 92 5.2. 3 Device boot modes ··…······ 93 5.3 Security use case examples 5.3.1 Secure boot: check bootloader for integrity and authenticity 5.3.2 Chain of trust: check flash memory for integrity and authenticity 94 5.3.3 Secure communication ···············“““·········*·“+·“+*···…·····;····‘··“ ∴95 5.3.4 mponent protection .96 5.35 Message-authentication example…… 5.4 Steps required before failure analysis 98 5.5 Security programming flow example(Secure Boot)..... Chapter 6 Safety Overview 6.1 Introduction.… 101 6.2 S32K lxx safety concept 102 6.2.1 Cortex- M4/M0+ Structural Core Self Test (SCST) 103 6.2.2 ECC on RaM and flash memory 104 6.2.3 Power supply monitoring 6. 2. 4 Clock monitoring 6.2.5 Temporal protection 105 6.2.6 Operational interference protection 105 6.2.7CRC..........107 6.2.8 Diversity of system resources ·“++“+“ 107 Chapter 7 CM4 Overview 7. 1 Arm Cortex-M4F core configuration 109 7.1.1 Buses. interconnects. and interfaces...... 110 S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 7.1.2 System Tick Timer..... 110 71.3 Debug facilities… 110 7. 1. 4 Cache 7,1.5 Core privilege levels……… 7.2 Nested Vectored Interrupt Controller( NVIC) Configuration......….….….….….….….……….….12 7.2. 1 Interrupt priority levels 112 7.2.2 Non-maskable interrupt. 113 7.2.3 Determining the bitfield and register location for configuring a particular interrupt 113 7.3 Asynchronous Wake-up Interrupt Controller( 7.3.1 Wake-up sources........ 14 7.4 FPU configuration........ 115 7. 5 JTAG controller configuration 116 Chapter 8 CMO+ Overview 8.1 Arm Cortex-MO+ core introduction 117 8.1.1 Buses. interconnects. and interfaces 118 8. 1. 2 System tick timer 118 8.1.3 Debug facilities 118 8. 1. 4 Core privilege levels 118 8.2 Nested vectored interrupt controller(NVIC)…….........… 119 8.2.1 terrupt priority levels 垂. 119 8.2.2 Non-maskable interrupt …119 8.2.3 Determining the bitfield and register location for configuring a particular interrupt 119 8.3 AwiC introduction .120 8.3.1 Wake-up sources 120 Chapter 9 Micro Trace Buffer(MTB) 9.1 Introduction 9.1.1 Overview ·············::+:·······:4····· 123 S32K1xx Series Reference manual. rev 8. 06/2018 6 NXP Semiconductors Section number Title Page 9. 1. 2 Features 125 9. 1. 3 Modes of operation 126 9.2 Memory map and register definition 126 9.2.1 MTB_DWT Memory Map 127 Chapter 10 Miscellaneous Control Module(MCM) 10.1 Chip-specific MCM information 137 10.2 Introduction .138 10.2.1 Features .138 10.3 Memory map/register descriptions.………….…….….138 10.3. 1 Crossbar Switch(AXBS) Slave Configuration(MCM_ PLASC)...... 139 10.3.2 Crossbar Switch(AXBS) Master Configuration (MCM_PLAMC) 140 10.3.3 Core Platform Control Register(MCM_CPCR) 141 10.3.4 Interrupt Status and Control Register ( 10.3.5 Process ID Register (MCM_PID)...........147 10.3.6 Compute Operation Control Register (MCM_CPO) 10.3.7 Local Memory Descriptor Register (MCM_ LMDRn) 中···“·+“······:········:·;··中·· 149 10.3.8 Local Memory Descriptor Register 2(MCM_LMDR2 152 10.3.9 LMEM Parity and ECC Control Register(MCM_LMPECR) 156 10.3.10 LMEM Parity and ECC Interrupt Register(MCM_LMPEIR)......157 10.3.11 LMEM Fault address register( MCM LMFAR)…,………,…………158 10.3. 12 LMEM Fault ALribute Register(MCM_LMFATR)...............159 10.3. 13 LMEM Fault Data High Register (MCM_LMFDHR). .……4160 10.3. 14 LMEM Fault Data Low Register (MCM_LMFDLR).. ……………160 10.4 Functional description 161 0.4.1 Interrupts....... 161 Chapter 11 System Integration Module( sIM) 11.1 Chip-specific 163 S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 11. 1.1 SIM register bitfield implementation ………163 11.2 Introduction.… 163 11. 2.1 Features 163 11.3 Memory map and register definition 1.3.1 SIM register descriptions....….……… 164 Chapter 12 Port Control and Interrupts(PORT) 12.1 Chip-specific PORT information 191 12.1.1 Number of pcrs .191 12.1.2 1O configuration sequence .…192 12.1.3 Digital input filter configuration sequence 12.2 Introduction .193 12.3 Overview “++ ………193 12.3.1 Features.......194 12.3.2 Modes of operation 194 12.4 External signal description 12.5 Detailed signal description. 12.6 Memory map and register definition... …196 12.6.1 Pin Control Register n(PORT_PCRn) ..198 126.2 Global Pin Control Low register( PORT GPCLR)………… 201 12.6. 3 Global Pin Control High Register(PORT_ GPCHR) ∴201 12.6.4 Global Interrupt Control Low Register (PORT 12.6.5 Global Interrupt Control High Register(PORT_GICHR) 202 12.6.6 nterrupt Status Flag Register( PORT-ISFR)……… 203 12.6.7 Digital Filter Enable Register (PORT_DFER) 12.6.8 Digital Filter Clock Register(PORT DFCR) .204 12.6.9 Digital Filter Width Register PORT 12.7 Functional description 12.7.1 Pin control ······*··*·····:········ 205 S32K1xx Series Reference manual. rev 8. 06/2018 8 NXP Semiconductors Section number Title Page 12.7.2 Global pin control... 12.7.3 Global interrupt control 207 12.7.4 External interrupts 207 12.7.5 Digital filter 08 Chapter 13 General-Purpose Input/Output (GPIO) 13. 1 Chip-specific GPIO information 09 13.1.1 Instantiation information 13.1.2 GPIO ports memory map.………… 209 13.1.3 GPIO register reset values....….…..….….210 13. 2 Introduction 13.2.1 Features 13.2.2 Modes of operation 13.2.3 GPIO Signal descriptions..... ·‘······…“··········‘ 13.3 Memory map and register definition…… 212 13.3.1 GPIO register descriptions……… 212 13. 4 Functional description ···.···( 220 13. 4.1 General-purpose input 220 13.4.2 General-purpose output 220 Chapter 14 Crossbar Switch Lite(AXBS-Lite) 14.1 Chip-specific 14.1.1 Crossbar Switch master assignments 223 14.1.2 Crossbar Switch slave assignments... 223 14.2 Introduction 224 14.2.1 Features 224 14.3 Functional Description……………… 225 14.3.1 General operation.. 225 14.3.2 Arbitration S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 14.4 Initialization/application information 227 Chapter 15 Memory Protection Unit(MPU) 15.1 Chip-specific MPU information 29 15.1.1MPUSlavePortAssignments................. 229 15.1.2 MPU Logical Bus Master Assignments .230 15.13 Current pid 15.1.4 Region descriptors and slave port configuration 15.2 Introduction “ 中·················;···· ∴…∴231 15.3 Overview 231 15.3.1 Block diagram 15.3.2 Features 232 15.4 MPU register descriptions 233 154.1 MPU Memory map.………………… 233 15.4.2 Control/Error Status Register (CESR).. 236 15.4.3 Error Address Register, slave port n(EARO-EAR4) 238 15.4.4 Error Detail Register, slave port n(EDRO-EDR4 ). ……239 15.4.5 Region Descriptor n, Word O(RGDO WORDO-RGDI5WORDO) 241 15.4.6 Region Descriptor 0, Word 1(RGDO- WORDI) 242 15.4.7 Region Descriptor 0, Word 2(RGDO-- WORD2 43 15.4.8 Region Descriptor 0, Word 3(RGDO- WORD3) 246 15.4.9 Region Descriptor n,word1( RGDI WORD1-RGD15WORD1).……,……………………247 15.4.10 Region Descriptor n, Word 2(RGDIWORD2-RGDI5WORD2) 15.4.llRegionDescriptorn,Word3(RGDl_WORD3-RGD15WORD3).251 15.4.12 Region Descriptor Alternate Access Control O (RGDAACO) “““+*““+““““+““+“++“ 15.4.13 Region Descriptor Alternate Access Control n(RGDAACI-RGDAAC15) 256 15.5 Functional description.……… 259 15.5.1 Access evaluation macro 259 15.5.2 Putting it all together and error terminations .261 S32K1xx Series Reference manual. rev 8. 06/2018 10 NXP Semiconductors 【实例截图】
【核心代码】
S32K-RM是开发必备手册，芯片所有的资源都有介绍，非常详细。
Contents Section number Title Page Chapter 1 About this manual 1.1 Audience 49 1.2 Organization.… 1.3 Module descriptions 49 1.3.1 Example: chip-specific information that clarifies content in the same chapter 50 1.3.2 Example: chip-specific information that refers to a different chapter 51 1.4 Register descriptions…… 1. 5 Conventions ·······44·+·····:.·.·.·4+····· 1. 5.1 Notes. Cautions 1.5.2 Numbering systems.. 53 1.5.3 Typographic notation 54 1.5.4 Special terms… 54 Chapter 2 Introduction 2.1 Overview 2.2 S32KIxx Series introduction 57 2.2.1S32K14x. 2.2.2S32K11x…. ….59 2.3 Feature summary……………… 60 2. 4 Block diagram 63 2.5 Feature comparison.......................... 64 2.5.1 Differences between s32K14x and S32Kllx .66 26 Applications…… 6 2.7 Module functional categories.... 2.7.1 Arm Cortex-M4F Core modules 2.7.2 Arm Cortex-MO+ Core modules 70 2.7.3 System modules. 70 S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 2.7.4 Memories and memory interfaces 2.7.5 Power Management 2.7.6 Clocking.. 2.7.7 Analog modules 2.7.8 Timer modules 73 2.7.9 Communication interfaces ..…74 2.7.10 Debug modules Chapter 3 Memory Map 3.1 Introduction.… .7 3.2 SRAM memory map.... 3. 2.1 S32K14X: SRAM memory map 3.2.2 S32KIlx: SRAM memory map 77 3.3 Flash memory map...... 78 3.4 Peripheral bridge(AIPS-Lite) memory map……… 78 34.1Read- after- write sequence and required serialization of memory operations.….…...….….….….…...:79 3.5 Private Peripheral Bus(PPB) memory map. .80 3.6 Aliased bit-band regions for CM4 core Chapter 4 Signal Multiplexing and Pin Assignment 4.1 Introduction ····+:·.··········· ················ 4.2 Functional description. 4.3 Pad description 4.4 Default pad state... .85 4.5 Signal multiplexing sheet..........................86 4.5.1 IO Signal Table 86 4.5.2 Input muxing table 88 4.6 Pinout diagrams 89 Chapter 5 Security Overview S32K1xx Series Reference manual. rev 8. 06/2018 NXP Semiconductors Section number Title Page 5.1 Introduction 91 5.2 Device security 91 5.2. 1 Flash memory security. 5.2.2 Cryptographic Services Engine(CSEc) security features 92 5.2. 3 Device boot modes ··…······ 93 5.3 Security use case examples 5.3.1 Secure boot: check bootloader for integrity and authenticity 5.3.2 Chain of trust: check flash memory for integrity and authenticity 94 5.3.3 Secure communication ···············“““·········*·“+·“+*···…·····;····‘··“ ∴95 5.3.4 mponent protection .96 5.35 Message-authentication example…… 5.4 Steps required before failure analysis 98 5.5 Security programming flow example(Secure Boot)..... Chapter 6 Safety Overview 6.1 Introduction.… 101 6.2 S32K lxx safety concept 102 6.2.1 Cortex- M4/M0+ Structural Core Self Test (SCST) 103 6.2.2 ECC on RaM and flash memory 104 6.2.3 Power supply monitoring 6. 2. 4 Clock monitoring 6.2.5 Temporal protection 105 6.2.6 Operational interference protection 105 6.2.7CRC..........107 6.2.8 Diversity of system resources ·“++“+“ 107 Chapter 7 CM4 Overview 7. 1 Arm Cortex-M4F core configuration 109 7.1.1 Buses. interconnects. and interfaces...... 110 S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 7.1.2 System Tick Timer..... 110 71.3 Debug facilities… 110 7. 1. 4 Cache 7,1.5 Core privilege levels……… 7.2 Nested Vectored Interrupt Controller( NVIC) Configuration......….….….….….….….……….….12 7.2. 1 Interrupt priority levels 112 7.2.2 Non-maskable interrupt. 113 7.2.3 Determining the bitfield and register location for configuring a particular interrupt 113 7.3 Asynchronous Wake-up Interrupt Controller( 7.3.1 Wake-up sources........ 14 7.4 FPU configuration........ 115 7. 5 JTAG controller configuration 116 Chapter 8 CMO+ Overview 8.1 Arm Cortex-MO+ core introduction 117 8.1.1 Buses. interconnects. and interfaces 118 8. 1. 2 System tick timer 118 8.1.3 Debug facilities 118 8. 1. 4 Core privilege levels 118 8.2 Nested vectored interrupt controller(NVIC)…….........… 119 8.2.1 terrupt priority levels 垂. 119 8.2.2 Non-maskable interrupt …119 8.2.3 Determining the bitfield and register location for configuring a particular interrupt 119 8.3 AwiC introduction .120 8.3.1 Wake-up sources 120 Chapter 9 Micro Trace Buffer(MTB) 9.1 Introduction 9.1.1 Overview ·············::+:·······:4····· 123 S32K1xx Series Reference manual. rev 8. 06/2018 6 NXP Semiconductors Section number Title Page 9. 1. 2 Features 125 9. 1. 3 Modes of operation 126 9.2 Memory map and register definition 126 9.2.1 MTB_DWT Memory Map 127 Chapter 10 Miscellaneous Control Module(MCM) 10.1 Chip-specific MCM information 137 10.2 Introduction .138 10.2.1 Features .138 10.3 Memory map/register descriptions.………….…….….138 10.3. 1 Crossbar Switch(AXBS) Slave Configuration(MCM_ PLASC)...... 139 10.3.2 Crossbar Switch(AXBS) Master Configuration (MCM_PLAMC) 140 10.3.3 Core Platform Control Register(MCM_CPCR) 141 10.3.4 Interrupt Status and Control Register ( 10.3.5 Process ID Register (MCM_PID)...........147 10.3.6 Compute Operation Control Register (MCM_CPO) 10.3.7 Local Memory Descriptor Register (MCM_ LMDRn) 中···“·+“······:········:·;··中·· 149 10.3.8 Local Memory Descriptor Register 2(MCM_LMDR2 152 10.3.9 LMEM Parity and ECC Control Register(MCM_LMPECR) 156 10.3.10 LMEM Parity and ECC Interrupt Register(MCM_LMPEIR)......157 10.3.11 LMEM Fault address register( MCM LMFAR)…,………,…………158 10.3. 12 LMEM Fault ALribute Register(MCM_LMFATR)...............159 10.3. 13 LMEM Fault Data High Register (MCM_LMFDHR). .……4160 10.3. 14 LMEM Fault Data Low Register (MCM_LMFDLR).. ……………160 10.4 Functional description 161 0.4.1 Interrupts....... 161 Chapter 11 System Integration Module( sIM) 11.1 Chip-specific 163 S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 11. 1.1 SIM register bitfield implementation ………163 11.2 Introduction.… 163 11. 2.1 Features 163 11.3 Memory map and register definition 1.3.1 SIM register descriptions....….……… 164 Chapter 12 Port Control and Interrupts(PORT) 12.1 Chip-specific PORT information 191 12.1.1 Number of pcrs .191 12.1.2 1O configuration sequence .…192 12.1.3 Digital input filter configuration sequence 12.2 Introduction .193 12.3 Overview “++ ………193 12.3.1 Features.......194 12.3.2 Modes of operation 194 12.4 External signal description 12.5 Detailed signal description. 12.6 Memory map and register definition... …196 12.6.1 Pin Control Register n(PORT_PCRn) ..198 126.2 Global Pin Control Low register( PORT GPCLR)………… 201 12.6. 3 Global Pin Control High Register(PORT_ GPCHR) ∴201 12.6.4 Global Interrupt Control Low Register (PORT 12.6.5 Global Interrupt Control High Register(PORT_GICHR) 202 12.6.6 nterrupt Status Flag Register( PORT-ISFR)……… 203 12.6.7 Digital Filter Enable Register (PORT_DFER) 12.6.8 Digital Filter Clock Register(PORT DFCR) .204 12.6.9 Digital Filter Width Register PORT 12.7 Functional description 12.7.1 Pin control ······*··*·····:········ 205 S32K1xx Series Reference manual. rev 8. 06/2018 8 NXP Semiconductors Section number Title Page 12.7.2 Global pin control... 12.7.3 Global interrupt control 207 12.7.4 External interrupts 207 12.7.5 Digital filter 08 Chapter 13 General-Purpose Input/Output (GPIO) 13. 1 Chip-specific GPIO information 09 13.1.1 Instantiation information 13.1.2 GPIO ports memory map.………… 209 13.1.3 GPIO register reset values....….…..….….210 13. 2 Introduction 13.2.1 Features 13.2.2 Modes of operation 13.2.3 GPIO Signal descriptions..... ·‘······…“··········‘ 13.3 Memory map and register definition…… 212 13.3.1 GPIO register descriptions……… 212 13. 4 Functional description ···.···( 220 13. 4.1 General-purpose input 220 13.4.2 General-purpose output 220 Chapter 14 Crossbar Switch Lite(AXBS-Lite) 14.1 Chip-specific 14.1.1 Crossbar Switch master assignments 223 14.1.2 Crossbar Switch slave assignments... 223 14.2 Introduction 224 14.2.1 Features 224 14.3 Functional Description……………… 225 14.3.1 General operation.. 225 14.3.2 Arbitration S32K1xx Series Reference manual. rev 8. 06/2018 NⅩ P Semiconductors Section number Title Page 14.4 Initialization/application information 227 Chapter 15 Memory Protection Unit(MPU) 15.1 Chip-specific MPU information 29 15.1.1MPUSlavePortAssignments................. 229 15.1.2 MPU Logical Bus Master Assignments .230 15.13 Current pid 15.1.4 Region descriptors and slave port configuration 15.2 Introduction “ 中·················;···· ∴…∴231 15.3 Overview 231 15.3.1 Block diagram 15.3.2 Features 232 15.4 MPU register descriptions 233 154.1 MPU Memory map.………………… 233 15.4.2 Control/Error Status Register (CESR).. 236 15.4.3 Error Address Register, slave port n(EARO-EAR4) 238 15.4.4 Error Detail Register, slave port n(EDRO-EDR4 ). ……239 15.4.5 Region Descriptor n, Word O(RGDO WORDO-RGDI5WORDO) 241 15.4.6 Region Descriptor 0, Word 1(RGDO- WORDI) 242 15.4.7 Region Descriptor 0, Word 2(RGDO-- WORD2 43 15.4.8 Region Descriptor 0, Word 3(RGDO- WORD3) 246 15.4.9 Region Descriptor n,word1( RGDI WORD1-RGD15WORD1).……,……………………247 15.4.10 Region Descriptor n, Word 2(RGDIWORD2-RGDI5WORD2) 15.4.llRegionDescriptorn,Word3(RGDl_WORD3-RGD15WORD3).251 15.4.12 Region Descriptor Alternate Access Control O (RGDAACO) “““+*““+““““+““+“++“ 15.4.13 Region Descriptor Alternate Access Control n(RGDAACI-RGDAAC15) 256 15.5 Functional description.……… 259 15.5.1 Access evaluation macro 259 15.5.2 Putting it all together and error terminations .261 S32K1xx Series Reference manual. rev 8. 06/2018 10 NXP Semiconductors 【实例截图】
【核心代码】
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