DDR4接口标准

【实例简介】
这是一份DDR4标准，硬件工程师可能会用到，谢谢
PLEASEL DONT VIOLATE THE LAW This document is copyrighted by JEDE Cand may not be reproduced without permission For information contact JEDEC Solid State Technology Association 3103 North 10th Street. Suite 240 South Arlington, Virginia 22201-2107 or call(703)907-7559 JEDEC Standard No. 79-4A (From JEDEC Board Ballot JCB-12-40, formulated under the cognizance of the JC-42 3 Subcommittee on DRAM Memories.) 1. Scope. 2. DDR4 SDRAM Package Pinout and Addressing 2.1DDR4 SDRAM Row for×4,X8and×16. 2.2 DDR4 SDRAM Ball Pitch 2.3 DDR4 SDRAM Columns for x4x8 and x16 2.4 DDR4 SDRAM X4/8 Ballout using Mo-207 2.5DDR4 SDRAM×16 Ballout using MO-207… 2.6 Pinout Description 2.7DDR4 SDRAM Addressing.. “=a 3. Functional Description 3.1 Simplified State Diagram 3.2 Basic Functionality 3. 3 RESET and initialization procedure 22357889991 3.3. 1 Power-up Initialization Sequence 3.3.2 Reset Initialization with stable power 3.4 Register Definition 12 3.4. 1 Programming the mode registers 12 3.5 Mode Register 13 4. DDR4 SDRAM Command Description and operation 24 4.1 Command truth table 24 4.2 CKE Truth ta 25 4.3 Burst Length, Type and Order...... 26 4.3.1 bl8 Burst order with crc enabled 26 4.4 DLL-off Mode dll on/off Switching procedure 4.4.1 DLL on/off switching procedure 4.4.2DLL“ on"to dll“ off procedure 27 4.4.3DLL“ofP" to dll“on" Procedure .28 4.5 DLL-off Mode 29 4.6 Input Clock Frequency Change 30 4.7 Write Leveling 31 4.7.1 DRAM setting for write leveling dRAM termination function in that mode 32 4.7.2 Procedure Description 33 4.7.3 Write Leveling Mode Exit 4.8 Temperature controlled Refresh modes........ 34 4.8. 1 Normal temperature mode 4 4.8.2 EXtended temperature mode 4.9 Fine granularity refresh Mode 35 4.9. 1 Mode Register and Command Truth Table 35 4.9.2 tREFI and tRFC parameters 35 4.9.3 Changing Refresh Rate 4.9.4 Usage with Temperature Controlled Refresh mode 4.9.5 Self Refresh entry and exit 37 4.10 Multi Purpose Register 37 4.10.1 DQ Training with MPR…… 37 4.10.2 MR3 definition 37 4.10.3 MPR Reads 38 4.10. 4 MPR Writes 40 4.10.5 MPR Read Data format “ 43 4.11 Data Mask (DM), Data Bus Inversion(DB)and TDQs 48 4.12 ZQ Calibration Commands 50 JEDEC Standard no, 79-4A 4.12.1 ZQ Calibration Description “ 50 4.13 DQ Vref Training 51 4. 14 Per DRAM Addressability... 4. 15 CAL Mode(Cs_n to Command Address Latency) 59 4.15.1 CAL Mode Description 4.16 CRC 61 4.16.1 CRC Polynomial and logic equation…… 1自“ 61 4. 16.2 CRC data bit mapping for x8 devices .63 4. 16.3 CRC data bit mapping for x 4 devices 。 aaaaaa;aa;aa 63 4.16. 4 CRC data bit mapping for x 16 devices 416.5 Write crc for x4 x8 and x16 devices .64 4.16.6 CRC Error Handling 64 4.16.7 CRC Frame format with bc4 65 4.16. 8 Simultaneous DM and CRC Functionality 4.17 Command Address Parity(CA Parity) 68 4.17.1 CA Parity Error Log Readout 4.18 Control gear down mode 4.19 DDR4 Key Core Timing 77 4.20 Programmable Preamble .....B 80 4.20.1 Write Preamble 80 420.2 Read Preamble .81 4.20.3 Read Preamble Training 82 4.21 Postamble 82 4.21.1 Read Postamble ·.:.:::::. 82 4.212 Write Postamble 82 4.22 ACTIVATE Command 82 4.23 Precharge Command 83 4.24 Read operation 83 4.24.1 READ Timing Definitions 83 4.24.1.1 READ Timing; Clock to Data Strobe relationship ...... 85 4. 24.1.2 READ Timing; Data Strobe to Data relationship.... 4.24.1.3 tLZ(DQS), tLZ(DQ), thz(DQS), tHZ(DQ)Calculation 87 4.24.1. 4 tRPRE Calculation 4.24.1.5 tRPST Calculation 89 4.24.2 READ Burst Operation 90 4.24. 3 Burst Read Operation followed by a Precharge 101 4. 24. 4 Burst Read Operation with Read DBI(Data Bus Inversion 103 4.24. 5 Burst Read Operation with Command/Address Parity 104 4.24 6 Read to write with write crc .105 4.24.7 Read to Read with CS to CA Latency…… 4.25 Write Operation .107 4.25.1 Write Burst Operation 107 4.26 Refresh command 123 4.27 Self refresh Operation .124 4.27. 1 Low Power auto self Refresh 126 4.28 Power down mode 127 4.28. 1 Power-Down Entry and Exit... 127 428.2 Power-Down clarifications 132 4.29 Maximum Power Saving Mode 132 4.29. 1 Maximum power saving mode 132 4.29.2 Mode entry……… .132 4.29.3 CKE transition during the mode 133 4.29.4 Mode exit 4.29.5 Timing parameter bin of maximum Power saving Mode for DDR4-1600/1866/2133/2400/2666/3200 134 4.30 Connectivity Test Mode 135 4.30.1 Introduction 135 4.302 Pin Mapping…… 135 4.30.3 Logic Equations 136 4.30.3. 1 Min Term Equations ……136 JEDEC Standard No. 79-4A 4.30.3. 2 Output equations for x16 devices .... 136 4.30.3. 3 Output equations for x8 devices 136 4.30. 3 4 Output equations for x4 devices 4.30. 4 T iming Requirement 137 4.31 CLK to Read DQs timing parameters “. 137 5. On-Die Termination 139 5. 1 ODT Mode Register and odt state table 139 5.2 Synchronous ODT Mode 141 5.2. 1 ODT Latency and Posted ODT 142 5.2.2 Timing Parameters 142 5.2.3 ODT during Reads 143 5.3 Dynamic ODT 144 5.3.1 Functional Description .144 5.3.2 ODT Timing Diagrams 145 5.4 Asynchronous ODT mode 146 5.5 odt buffer disabled mode for power down 147 5.6 ODT Timing Definitions 148 5.6.1 Test Load for odT Timings .148 5.6.2 ODT Timing Definitions 148 6. Absolute Maximum Ratings 150 7. AC& DC Operating Conditions 151 7.1 AC and Dc Input Measurement Levels: VREF Tolerances............ .151 7.2 AC and DC Logic Input Levels for Differential Signals 152 7.2.1 Differential signal definition :: 152 7.2.2 Differential swing requirements for clock(CK t-CK c 152 7.2.3 Single-ended requirements for differential signals 153 7.2.4 Address and control Overshoot and Undershoot specifications 153 7.2.5 Clock Overshoot and Undershoot Specifications 154 7.2.6 Data, Strobe and mask Overshoot and Undershoot Specifications 7.3 Slew Rate Definitions for Differential Input Signals(CK) 156 7.4 Differential Input Cross Point Voltage 157 7.5 CMOS rail to rail Input Levels…… 159 7.5.1 CMOS rail to rail Input Levels for RESEt n IL 159 7.6 aC dc logic input levels for single-ended signals ..159 8. AC and DC output Measurement levels 160 8. 1 Output Driver DC Electrical Characteristics 160 8.1.1 Alert n output Drive Characteristic .161 8.2 Single-ended AC& DC Output Levels 162 8.3 Differential AC DC Output Levels 162 8. 4 Single-ended Output Slew Rate ..162 8.5 Differential Output Slew Rate “ 163 9. Speed Bin naaaaaa000008ii0i0 164 9. 1 Speed Bin Table Note 168 10. IDD and iddQ Specification Parameters and Test conditions 169 10.1 IDD. IPP and IDDQ Measurement Conditions .169 10.2 IDD Specifications 184 1. Input/Output Capacitance 186 12. Electrical Characteristics AC T iming 188 12.1 Reference Load for AC Timing and Output Slew Rate 188 12.2 tREFI 188 12.3 Timing Parameters by Speed Grade 189 12. 4 The DQ input receiver compliance mask for voltage and timing is shown in the figure below.....199 12.5 DDR4 Function matrix 204 Annex a Differences between JESD79-4A and JESD79-4 207 JEDEC Standard no, 79-4A JEDEC Standard No. 79-4A Page 1 This document defines the DDR4 SDRAM specification, including features, functionalities, AC and Dc characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3)and some aspects of the DDR and DDR2 standards(JESD79, JESD79-2 Each aspect of the changes for DDR4 SDRAM operation were considered and approved by committee ballot(s). the accumulation of these ballots were then incorporated to prepare this JESD79-4 specifications, replacing whole sections and incorporating the changes into Functional Description and Operation JEDEC Standard No, 79-4A Page 2 The DDR4 SDRAM X4/X8 component will have 13 electrical rows of balls. Electrical is define power/ground balls. There may be additional rows of inactive balls for mechanical suppor ed as rows that contain signal ball or The ddR4 SdRAM x16 component will have 16 electrical rows of balls there may be additional rows of inactive balls for mechanical support The DDR4 SDRAM component will use a ball pitch of 0. 8 mm by 0.8 mm The number of depopulated columns is 3 The DDR4 SDRAM X4/x8 and x 16 component will have 6 electrical columns of balls in 2 sets of 3 columns There will be columns between the electrical columns where there are no balls populated. The number of these columns is 3 Electrical is defined as columns that contain signal ball or power/ground balls. There may be additional columns of inactive balls for mechanical suppor NotE 1 These pins are not connected for the X4 configuration NOTE2 TDQs t is not valid for the x4 configuration NoTE 3 TDQs C is not valid for the x4 configuration NOTE 4 A17 is only defined for the x4 configuration NoTE 5 These pins are for stacked component such as 3DS For mono package, these pins are NC NOTE 6 ODT1 /CKE1 /CS1 n are used together only for DDP. NOTE 7 TEN is optional for 8Gb and above. This pin is not connected if TEN is not supported 【实例截图】
【核心代码】