实例介绍
【实例简介】
一个xilinx官方出品的demo：xapp1052。全称是Bus Master DMA Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express® Solutions。
Components of a Design for PCI Express R XILINX Components of A typical design for PCI Express includes the following main components a design for Pcl · Hardware HDL Design Express Driver Design · Software Application The hardware design refers to the Verilog or vhdl application residing on the Xilinx FPga. In this case, it is the bus master dma design or BMD. This design contains control engines for the receive and transmit data path along with various registers and memory interfaces to store and retrieve data. The BMD is explained in more detail in "Exploring the Bus Master Design page 8 The driver design is normally written in C and is the link between the higher level software application and the hardware application. The driver contains various routines that are called by the software application and are used to communicate with the hardware via the Pci Express link. The driver resides in the kernel memory on the system The software application is most apparent to the user, and can be written in any programming language. It can be as simple as a small c program or as complex as a gUl-based application The user interfaces with the software application, which invokes routines in the driver to perform the necessary data movements. Once completed, the hardware issues an interrupt nforming the driver that the data movement is finished. Then the driver can invoke routines in the software application to inform you that the request is completed Exploring the The BMd Performance Demonstration Design is used by Xilinx to test core functionality and DMA gather performance information. Customers can use this design to measure performance on Performance their own system. To test performance, the bMd design fabricates the data payload using a pre-determined data pattern defined in a backend control register. Counters and registers are Demo Hierarchy also implemented to measure link performance EXtract the xapp1052. zip file to the same level as the core netlist. The top-level directory is named dma_performance_ demo and subdirectories are defined in the following sections o dma_performance_demo Top-level directory for the dMa reference design tpg ga BMD Bus master design rtl source code r common Bus master rtl files common to all interfaces implement Implementation script to build Bus Master Design Xilinx Development board UCF files xst SCR/XST build files for each configuration o win32_sy drit Driver install files pcie_demo. sys and oemsetup XP inf files source Driver source files to compile and build driver XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the DMA Performance Demo Hierarchy R XILINX c win32_application DMA Windows application install executable source Windows 32-bit application source files linux sw a bmd Application and Driver source files with scripts to compile and run application dma_performance_ demo/fpga/BMD/ The rtl directory contains the Bus Master Application source code Table 1: BMD Directory Name Description dma_performance_ demo/fpga/bmd BMD 32 RX ENGINEV Interface specitic Bus Master Design source files BMD 32 TX ENGINE V These are the rx and tx control state machines BMD 64 RX ENGINEV and application wrapper files for each Xilinx endpoint solution BMD 64 TX ENGINEV BMD 128 RX ENGINEV BMD 128 TX ENGINE V pipe 1 lane pci exp 32b app.v s6_pci_exp_32b_app v5 blk_plus_pci_exp_64b_app.v v6_pci_exp_ 64b_app.V v6_pciexp_ 128b_app.V dma_ performance_ demo/fpga/BMD/common The common directory contains the Bus Master Application source code able 2: RTL Directory Name Description dma performance demo/fpga/bmd/common BMD. V Bus Master Design files common for any BMD CFG CTRLV interface width BMD EPV BMD EP MEM.V BMD EP MEM ACCESS.V BMD GeN2.V BMD PCIE 20, V BMD NTR CTRL.V BMD INTR CTRL DELAY.V BMD RD THROTTLE.V BMD TO CTRLV XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the DMA Performance Demo Hierarchy R XILINX dma_performance_ demo/fpga/implement The implement directory contains the design implementation scripts able 3: Implement Directory Name Description dma performance demo/fpga/implement implement_ dma. pl Implementation PERL script dma_performance_ demo/fpgaimplement/ucf The ucf directory contains the User Constraints Files(. ucf) Table 4: UCF Directory Name Description dma_performance_demo/fpga/implement/uct xilinx_pci_exp blk_plus_1_lane_ep Virtex-5 Block Plus 1-ane Hi-Tech global board UCF XC5vlx50t-ff1136-1_htg.ucf file x_pci_exp_blk_plus_4_lane_ep Virtex-5 Block Plus 4-lane Hi-Tech Global board UCF xc5vlx50t-ff1136-1 htg. ucf fil xilinx_pci_exp_blk_plus_1_lane_ep Virtex-5 Block Plus 1-Iane ml555 board ucF file Xc5vlx50t-ff1136-1 ml555 ucf Xc5vx50t1136-1m55507ep xilinx_pci_exp blk_plus_ 4_ lane_ep Virtex-5 Block Plus 4-lane ml555 board UCF file xilinx_pci_exp_blk_plus_8_lane_ep Virtex-5 Block Plus 8-lane ml555 board ucf file xc5vlx5Ot-ff1136-1 m555 ucf xilinx_pci_exp_v6_1_lane_ep Virtex-6 Integrated Endpoint 1-lane Gen 1 ML605 ml605 gen1ucf board ucf file xilinx_pci_exp_v6_4_lane_ep Virtex-6 Integrated Endpoint 4-lane Gen 1 ML605 ml605 gen1ucf board ucf file xilinx_pci_exp_v6_8_lane_ep Virtex-6 Integrated Endpoint 8-lane Gen 1 ML605 ml605 gen1ucf board ucf file xilinx_pci_ exp v61 lane _ ep Virtex-6 Integrated Endpoint 1-lane Gen 2 ML605 ml605_ gen2. ucf board ucf file linx_pci_exp_v6_4_lane_ep tex-6 Integrated Endpoint 4-lane Gen 2 ML605 ml605_gen2.ucf board UCF file xilinx_pci_exp_v6_8_lane_ep irtex-6 Integrated Endpoint 8-lane Gen 2 ML605 nl605 gen2 ucf board ucF file xilinx_pci_exp_s6_1_lane_ep__sp605ucf Spartan-6 Integrated Endpoint SP605 board UCF file xilinx_pci_exp_pipe_1_lane_ep_skit. ucf Spartan-3 Endpoint PIPE 1-lane PCI Express Starter Kit board UCF file XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the DMA Performance Demo Hierarchy R XILINX dma_performance_demofpga/implement/xst The xst directory contains the synthesis files able 5: XsT Directory Name Description dma_performance_demo/fpga/implement/xst xst XsT file taken in by synthesis tool pointing to core and bus master backend scr SCR file provides synthesis options dma_performance_demo/win 32_sw/win32_driver The driver directory contains the driver installation files Table 6: Driver Directory Name Description dma performance demo/win32 sw/win 32 driver oemsetupXPinf Windows setup information file pcie_demo. sys Windows device driver dma_performance_demo/win32_sw/win32_driver/source The source directory contains the Windows dMa driver source files Table 7: Source Directory Name Description dma performance demo/win32 sw/win 32 driver/source build. cmd DOS build scripts sources Makefile. inc pnp Driver source implementing Plug and Play functionality s31000c Device specific driver source code s31000.h s31000.rc ioctl h msglog h Windows event logging source code Msglog mc MSG0001bin dma_performance_demo/win 32_sw/win32driver/source/GUI The win32_application directory contains Windows gUI source files built with Microsoft Visual Studio XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com 6 Exploring the DMA Performance Demo Hierarchy R XILINX dma_performance_demo/win32_sw/win 32_application The win32_application directory contains Windows application installer files able 8: Implement Directory Name Description dma_performance_demo/win 32_sw/win 32_application setup. exe Installer executable PCle perf. caB Contains application library files SETUPLST Packing list file dma_performance_demo/win32_ sw/win32_application/source/ DriverMar The win32_application directory containing Windows application user mode driver files dma_performance_demo/linux_ sw/bmd The bmd directory contains all Linux application and driver source files along with scripts to build the application and install the kernel driver Table 9: mbd Directory Name Description dma performance demo/linux sw/bmd bmd. cpp Source file for bmd t class which exercises xbmd bma. h Header file for bmd t class type ctg. cpp Source file for cfgt class which handles all access to Endpoint configuration space cfg. h Header file for ctg_t class type bmd_ main. cpp Source file containing main gui functionality including handlers bmd main h Header file for bmd_main cpp Bmd_ep. cpp Class file for bmd_ep_t class bmd ep. h Header file for bmd_ep_ t class xcmd. c Kernel mode driver source file bmd. h Header file for kernel driver Mersenne Twister h Header file for random number generator bmd_app.glade GUI content file bmd_app. xml XML file used to define gul layout xilinx. png Xilinx logo image load driver Script to load kernel dri run bmd. csh Script to compile driver, application, and calls load driver to insert driver into kernel XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the Bus Master Design R XILINX Exploring the The BMD architecture is shown in Figure 2 and consists of initiator logic, target logic, Bus Master status/control registers, interface logic, and the endpoint core for PCl Express Desig PCle Endpoint cor Interface 0L=z Initiator Logic R Control/ Status Registers Figure 2: Bus Master validation Design Architecture arget Logic Target logic is responsible for capturing single Dword Memory Write(MWr) and Memory Read (MRd) TLPs presented on the interface. MWr and mRd TLPs are sent to the endpoint via Programmed Input/output and are used to monitor and control the dma hardware. The function of the target logic is to update the status and control registers during MWrs and return Completions with Data for all incoming MRds. All incoming MWr packets are 32-bit and contain a one dword(32-bits) payload. Incoming MRd packets should only request 1 Dword of data at a time resulting in Completions with Data of a single Dword Control and Status Registers The control and status registers contain operational information for the dma controller It is mportant to note that the example bmd design provided is primarily used to measure performance of data transfers and, consequently, contains status registers that may not be needed in typical designs. You can choose to remove these and their associated logic if needed. All registers are defined in"Appendix A: Design Descriptor Registers nitiator Logic The function of the initiator block is to generate memory write or Memory Read TLPs depending on whether an upstream or downstream transfer is selected. The Bus Master Design only supports generating one type of a data flow at a single time. The Bus master Enable bit (Bit 2 of PCI Command Register) must be set to initiate tLP traffic upstream. no transactions are allowed to cross the 4K boundary The initiator logic generates Memory Write TLPs when transferring data from the endpoint to system memory. The Write DMa control and status registers specify the address, size, payload content. and number of tlps to be sent XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the Bus Master Design R XILINX The first TLP contains the start address, which is specified in the Write DMA TLP Address(see Write DMA TLP Address(WDMATLPA)(008H, R/), page 30) register. Subsequent TLPs contain an address that is a function of the address stored in WDmatLpa plus the TLP size defined in the Write dMA TLP Size register(see Write dMA TLP Size(WDMATLPS)(OOCH R/), page 31). The initiator sends Memory Writes with a specific data pattern. Each DWORD in the payload contains the contents of the Write DMA Data Pattern register(see "Write DMA Data Pattern(WDMATLPP)(014H, R/), page 31). Note that in a normal application the data would consist of information in the device being moved to the host memory; however, for the example reference design it is a set pattern found in the Wdmatlpp register An interrupt is generated upstream once the number of MWr TLPs sent onto the link matches the value inside the Write DMA TLP Count(see"Write DMA TLP Count(WDMATLPC)(0010H R/), page 31)register. Figure 3 shows an example sequence of events for a DMA Write operation Step operation Register Operation value Assert initiator reset PIO WIte DCR1 0x00000001 2 De-assert Initiator Reset PIO WrIte DCR1 0x00000 Write DMA H/w address PIO WIte WDMAtLPA H/W Address Write dMA TLP size PIO Write WDMATLPS Write TLP size Write dma tlp count PIO WrIte WdMatlPo Write TLp count 6 TLP Payload Pattern PIO WrIte WdmAtLpp Data pattern Write dMA start PIO Write DCR2 0x00000001 8 Wait for Interrupt TLP 9 Write dMa Performance PIO Read WDMAPERF Figure 3: Write DMA Sequence of Events The initiator generates Memory Read TLPs when transferring data from system memory to the endpoint. The Read dMa registers specify the address, size, payload content, and number of TLPs to be sent The first TLP address is specified by the read dMA TLP Address(see Read DMA TLP Address(RDMATLPA)(01 CH, R/): page 32)register. Each additional TLP in the transfer contains an address that is a function of Wdmatlpa plus the tlp size defined in the read DMA TLP Size(see"Read DMA TLP Size(RDMATLPS)(020H, R/), page 33 )register. The TLP tag number starts at zero and is incremented by one for each additional tlp, guaranteeing a unique number for each packet Completions with Data are expected to be received in response to the Memory Read Request packets Initiator logic tracks incoming completions and calculates a running total of the amount of data received once the requested data size has been received, the endpoint generates an interrupt tLP upstream to indicate the end of the DMA transfer. Additional error checking is performed inside the initiator Each dWord inside a Completion payload must match the value in the read dma tlp pattern(RDmATLPP register. The total payload returned must also equal Read DMA TLP Count times Read DMA TLP Size(see " Read DMA TLP Count(RDMATLPC)(024H, R/), "page 33 and"Read DMA TLP Size(RDMATLPS)(020H, R/), page 33, respectively). Figure 4 shows an example sequence of events for a DMA Read operation Step operation Register operation Value Assert initiator reset PIO WrIte dCR1 0x00000001 12345678 De-assert Initiator Reset PIO WIte dcr1 0x00000000 Read DMA H/W Address I PIO WrIte RDMATLPA H/W Address Read DMA TLP Size PIO WIte rdmatlp TLP Read Size 5 Read DMA TLP Count PIO Write RDMATLPC Read TLP count Read DMA Start PIO Write DcR2 0x000 Wait for Interrupt TLP Read DMA Performance PIO Read RDMAPERF Figure 4: Read DMA Sequence of Events The type of interrupt tLP generated in both cases is controllable via the PCI Command Register's interrupt Disable bit and/or the MsI Enable bit within the MsI capability structure XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Setting Up the BMD Design R XILINX When the MsI Enable bit is set, the endpoint core generates a MsI request by sending a MWi TLP. If disabled, the endpoint core generates a legacy interrupt as long as Bit 10 of the PCI Command register has interrupts enabled The data returned for the Memory Read request is discarded by the BMd application since the application is only concerned with the data movement process. Normally, this data would need to be checked for correct order and then loaded into some type of storage element such as a Block ram or fiFo Setting Up the The Bus Master Design connects up to the transaction(TRN)interface of the Endpoint for PCI BMD Design Express. The trN interface is described in detail in the appropriate user guide for the core targeted. The user guides are located in the IP Documentation Center at www.xilinx.com/support/documentation/index.htm Generating the core To generate the core, follow these steps 1. Ensure the latest Xilinx isE design Suite software is installed. The latest software updates arelocatedatwww.xilinx.com/support/download/index.htm 2. Start the core Generator TM software and create a new project 3. Target the appropriate device and generate the core in Verilog 4. In the taxonomy tree, select Standard Bus Interface> PCI Express 5. Select the appropriate endpoint solution for the targeted device and select Customize 6. In the customization gUl, name the core to be generated bmd design 7. Select the correct reference clock frequency for the board targeted. See the board user guide for information on reference clock frequencies available on the board For example the Hi-tech Global board requires a 250 MHz reference clock, and the Ml555 requires a 100 MHz reference clock 8. Depending on the core targeted, the order of customization pages may differ. Ensure the following two changes are made Set the subclass to 0x80 specifying Other Memory Controller Configure baRo to be a 32-bit memory BAR with a 1KB aperture. BAR1 through BAR5 should be disabled 9. Leave all other settings at their defaults and click finish to generate the core Implementing the Bus Master Design To implement the design follow these steps Extract the xapp 1052. zip file to the same level as the example_design directory. A directory called dma_performance demo will be added to the core hierarchy as shown in Figure 5 ame Size Type▲ Odma peformance demo File Folder Odoc File Folder Example design File Folder o implement File Folder asimulation File Folder source File Folder 目v6 pcie readme. tx 7 KB Text Document Figure 5: Design Top Level Hierarchy XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com 10 【实例截图】
【核心代码】
一个xilinx官方出品的demo：xapp1052。全称是Bus Master DMA Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express® Solutions。
Components of a Design for PCI Express R XILINX Components of A typical design for PCI Express includes the following main components a design for Pcl · Hardware HDL Design Express Driver Design · Software Application The hardware design refers to the Verilog or vhdl application residing on the Xilinx FPga. In this case, it is the bus master dma design or BMD. This design contains control engines for the receive and transmit data path along with various registers and memory interfaces to store and retrieve data. The BMD is explained in more detail in "Exploring the Bus Master Design page 8 The driver design is normally written in C and is the link between the higher level software application and the hardware application. The driver contains various routines that are called by the software application and are used to communicate with the hardware via the Pci Express link. The driver resides in the kernel memory on the system The software application is most apparent to the user, and can be written in any programming language. It can be as simple as a small c program or as complex as a gUl-based application The user interfaces with the software application, which invokes routines in the driver to perform the necessary data movements. Once completed, the hardware issues an interrupt nforming the driver that the data movement is finished. Then the driver can invoke routines in the software application to inform you that the request is completed Exploring the The BMd Performance Demonstration Design is used by Xilinx to test core functionality and DMA gather performance information. Customers can use this design to measure performance on Performance their own system. To test performance, the bMd design fabricates the data payload using a pre-determined data pattern defined in a backend control register. Counters and registers are Demo Hierarchy also implemented to measure link performance EXtract the xapp1052. zip file to the same level as the core netlist. The top-level directory is named dma_performance_ demo and subdirectories are defined in the following sections o dma_performance_demo Top-level directory for the dMa reference design tpg ga BMD Bus master design rtl source code r common Bus master rtl files common to all interfaces implement Implementation script to build Bus Master Design Xilinx Development board UCF files xst SCR/XST build files for each configuration o win32_sy drit Driver install files pcie_demo. sys and oemsetup XP inf files source Driver source files to compile and build driver XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the DMA Performance Demo Hierarchy R XILINX c win32_application DMA Windows application install executable source Windows 32-bit application source files linux sw a bmd Application and Driver source files with scripts to compile and run application dma_performance_ demo/fpga/BMD/ The rtl directory contains the Bus Master Application source code Table 1: BMD Directory Name Description dma_performance_ demo/fpga/bmd BMD 32 RX ENGINEV Interface specitic Bus Master Design source files BMD 32 TX ENGINE V These are the rx and tx control state machines BMD 64 RX ENGINEV and application wrapper files for each Xilinx endpoint solution BMD 64 TX ENGINEV BMD 128 RX ENGINEV BMD 128 TX ENGINE V pipe 1 lane pci exp 32b app.v s6_pci_exp_32b_app v5 blk_plus_pci_exp_64b_app.v v6_pci_exp_ 64b_app.V v6_pciexp_ 128b_app.V dma_ performance_ demo/fpga/BMD/common The common directory contains the Bus Master Application source code able 2: RTL Directory Name Description dma performance demo/fpga/bmd/common BMD. V Bus Master Design files common for any BMD CFG CTRLV interface width BMD EPV BMD EP MEM.V BMD EP MEM ACCESS.V BMD GeN2.V BMD PCIE 20, V BMD NTR CTRL.V BMD INTR CTRL DELAY.V BMD RD THROTTLE.V BMD TO CTRLV XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the DMA Performance Demo Hierarchy R XILINX dma_performance_ demo/fpga/implement The implement directory contains the design implementation scripts able 3: Implement Directory Name Description dma performance demo/fpga/implement implement_ dma. pl Implementation PERL script dma_performance_ demo/fpgaimplement/ucf The ucf directory contains the User Constraints Files(. ucf) Table 4: UCF Directory Name Description dma_performance_demo/fpga/implement/uct xilinx_pci_exp blk_plus_1_lane_ep Virtex-5 Block Plus 1-ane Hi-Tech global board UCF XC5vlx50t-ff1136-1_htg.ucf file x_pci_exp_blk_plus_4_lane_ep Virtex-5 Block Plus 4-lane Hi-Tech Global board UCF xc5vlx50t-ff1136-1 htg. ucf fil xilinx_pci_exp_blk_plus_1_lane_ep Virtex-5 Block Plus 1-Iane ml555 board ucF file Xc5vlx50t-ff1136-1 ml555 ucf Xc5vx50t1136-1m55507ep xilinx_pci_exp blk_plus_ 4_ lane_ep Virtex-5 Block Plus 4-lane ml555 board UCF file xilinx_pci_exp_blk_plus_8_lane_ep Virtex-5 Block Plus 8-lane ml555 board ucf file xc5vlx5Ot-ff1136-1 m555 ucf xilinx_pci_exp_v6_1_lane_ep Virtex-6 Integrated Endpoint 1-lane Gen 1 ML605 ml605 gen1ucf board ucf file xilinx_pci_exp_v6_4_lane_ep Virtex-6 Integrated Endpoint 4-lane Gen 1 ML605 ml605 gen1ucf board ucf file xilinx_pci_exp_v6_8_lane_ep Virtex-6 Integrated Endpoint 8-lane Gen 1 ML605 ml605 gen1ucf board ucf file xilinx_pci_ exp v61 lane _ ep Virtex-6 Integrated Endpoint 1-lane Gen 2 ML605 ml605_ gen2. ucf board ucf file linx_pci_exp_v6_4_lane_ep tex-6 Integrated Endpoint 4-lane Gen 2 ML605 ml605_gen2.ucf board UCF file xilinx_pci_exp_v6_8_lane_ep irtex-6 Integrated Endpoint 8-lane Gen 2 ML605 nl605 gen2 ucf board ucF file xilinx_pci_exp_s6_1_lane_ep__sp605ucf Spartan-6 Integrated Endpoint SP605 board UCF file xilinx_pci_exp_pipe_1_lane_ep_skit. ucf Spartan-3 Endpoint PIPE 1-lane PCI Express Starter Kit board UCF file XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the DMA Performance Demo Hierarchy R XILINX dma_performance_demofpga/implement/xst The xst directory contains the synthesis files able 5: XsT Directory Name Description dma_performance_demo/fpga/implement/xst xst XsT file taken in by synthesis tool pointing to core and bus master backend scr SCR file provides synthesis options dma_performance_demo/win 32_sw/win32_driver The driver directory contains the driver installation files Table 6: Driver Directory Name Description dma performance demo/win32 sw/win 32 driver oemsetupXPinf Windows setup information file pcie_demo. sys Windows device driver dma_performance_demo/win32_sw/win32_driver/source The source directory contains the Windows dMa driver source files Table 7: Source Directory Name Description dma performance demo/win32 sw/win 32 driver/source build. cmd DOS build scripts sources Makefile. inc pnp Driver source implementing Plug and Play functionality s31000c Device specific driver source code s31000.h s31000.rc ioctl h msglog h Windows event logging source code Msglog mc MSG0001bin dma_performance_demo/win 32_sw/win32driver/source/GUI The win32_application directory contains Windows gUI source files built with Microsoft Visual Studio XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com 6 Exploring the DMA Performance Demo Hierarchy R XILINX dma_performance_demo/win32_sw/win 32_application The win32_application directory contains Windows application installer files able 8: Implement Directory Name Description dma_performance_demo/win 32_sw/win 32_application setup. exe Installer executable PCle perf. caB Contains application library files SETUPLST Packing list file dma_performance_demo/win32_ sw/win32_application/source/ DriverMar The win32_application directory containing Windows application user mode driver files dma_performance_demo/linux_ sw/bmd The bmd directory contains all Linux application and driver source files along with scripts to build the application and install the kernel driver Table 9: mbd Directory Name Description dma performance demo/linux sw/bmd bmd. cpp Source file for bmd t class which exercises xbmd bma. h Header file for bmd t class type ctg. cpp Source file for cfgt class which handles all access to Endpoint configuration space cfg. h Header file for ctg_t class type bmd_ main. cpp Source file containing main gui functionality including handlers bmd main h Header file for bmd_main cpp Bmd_ep. cpp Class file for bmd_ep_t class bmd ep. h Header file for bmd_ep_ t class xcmd. c Kernel mode driver source file bmd. h Header file for kernel driver Mersenne Twister h Header file for random number generator bmd_app.glade GUI content file bmd_app. xml XML file used to define gul layout xilinx. png Xilinx logo image load driver Script to load kernel dri run bmd. csh Script to compile driver, application, and calls load driver to insert driver into kernel XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the Bus Master Design R XILINX Exploring the The BMD architecture is shown in Figure 2 and consists of initiator logic, target logic, Bus Master status/control registers, interface logic, and the endpoint core for PCl Express Desig PCle Endpoint cor Interface 0L=z Initiator Logic R Control/ Status Registers Figure 2: Bus Master validation Design Architecture arget Logic Target logic is responsible for capturing single Dword Memory Write(MWr) and Memory Read (MRd) TLPs presented on the interface. MWr and mRd TLPs are sent to the endpoint via Programmed Input/output and are used to monitor and control the dma hardware. The function of the target logic is to update the status and control registers during MWrs and return Completions with Data for all incoming MRds. All incoming MWr packets are 32-bit and contain a one dword(32-bits) payload. Incoming MRd packets should only request 1 Dword of data at a time resulting in Completions with Data of a single Dword Control and Status Registers The control and status registers contain operational information for the dma controller It is mportant to note that the example bmd design provided is primarily used to measure performance of data transfers and, consequently, contains status registers that may not be needed in typical designs. You can choose to remove these and their associated logic if needed. All registers are defined in"Appendix A: Design Descriptor Registers nitiator Logic The function of the initiator block is to generate memory write or Memory Read TLPs depending on whether an upstream or downstream transfer is selected. The Bus Master Design only supports generating one type of a data flow at a single time. The Bus master Enable bit (Bit 2 of PCI Command Register) must be set to initiate tLP traffic upstream. no transactions are allowed to cross the 4K boundary The initiator logic generates Memory Write TLPs when transferring data from the endpoint to system memory. The Write DMa control and status registers specify the address, size, payload content. and number of tlps to be sent XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Exploring the Bus Master Design R XILINX The first TLP contains the start address, which is specified in the Write DMA TLP Address(see Write DMA TLP Address(WDMATLPA)(008H, R/), page 30) register. Subsequent TLPs contain an address that is a function of the address stored in WDmatLpa plus the TLP size defined in the Write dMA TLP Size register(see Write dMA TLP Size(WDMATLPS)(OOCH R/), page 31). The initiator sends Memory Writes with a specific data pattern. Each DWORD in the payload contains the contents of the Write DMA Data Pattern register(see "Write DMA Data Pattern(WDMATLPP)(014H, R/), page 31). Note that in a normal application the data would consist of information in the device being moved to the host memory; however, for the example reference design it is a set pattern found in the Wdmatlpp register An interrupt is generated upstream once the number of MWr TLPs sent onto the link matches the value inside the Write DMA TLP Count(see"Write DMA TLP Count(WDMATLPC)(0010H R/), page 31)register. Figure 3 shows an example sequence of events for a DMA Write operation Step operation Register Operation value Assert initiator reset PIO WIte DCR1 0x00000001 2 De-assert Initiator Reset PIO WrIte DCR1 0x00000 Write DMA H/w address PIO WIte WDMAtLPA H/W Address Write dMA TLP size PIO Write WDMATLPS Write TLP size Write dma tlp count PIO WrIte WdMatlPo Write TLp count 6 TLP Payload Pattern PIO WrIte WdmAtLpp Data pattern Write dMA start PIO Write DCR2 0x00000001 8 Wait for Interrupt TLP 9 Write dMa Performance PIO Read WDMAPERF Figure 3: Write DMA Sequence of Events The initiator generates Memory Read TLPs when transferring data from system memory to the endpoint. The Read dMa registers specify the address, size, payload content, and number of TLPs to be sent The first TLP address is specified by the read dMA TLP Address(see Read DMA TLP Address(RDMATLPA)(01 CH, R/): page 32)register. Each additional TLP in the transfer contains an address that is a function of Wdmatlpa plus the tlp size defined in the read DMA TLP Size(see"Read DMA TLP Size(RDMATLPS)(020H, R/), page 33 )register. The TLP tag number starts at zero and is incremented by one for each additional tlp, guaranteeing a unique number for each packet Completions with Data are expected to be received in response to the Memory Read Request packets Initiator logic tracks incoming completions and calculates a running total of the amount of data received once the requested data size has been received, the endpoint generates an interrupt tLP upstream to indicate the end of the DMA transfer. Additional error checking is performed inside the initiator Each dWord inside a Completion payload must match the value in the read dma tlp pattern(RDmATLPP register. The total payload returned must also equal Read DMA TLP Count times Read DMA TLP Size(see " Read DMA TLP Count(RDMATLPC)(024H, R/), "page 33 and"Read DMA TLP Size(RDMATLPS)(020H, R/), page 33, respectively). Figure 4 shows an example sequence of events for a DMA Read operation Step operation Register operation Value Assert initiator reset PIO WrIte dCR1 0x00000001 12345678 De-assert Initiator Reset PIO WIte dcr1 0x00000000 Read DMA H/W Address I PIO WrIte RDMATLPA H/W Address Read DMA TLP Size PIO WIte rdmatlp TLP Read Size 5 Read DMA TLP Count PIO Write RDMATLPC Read TLP count Read DMA Start PIO Write DcR2 0x000 Wait for Interrupt TLP Read DMA Performance PIO Read RDMAPERF Figure 4: Read DMA Sequence of Events The type of interrupt tLP generated in both cases is controllable via the PCI Command Register's interrupt Disable bit and/or the MsI Enable bit within the MsI capability structure XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com Setting Up the BMD Design R XILINX When the MsI Enable bit is set, the endpoint core generates a MsI request by sending a MWi TLP. If disabled, the endpoint core generates a legacy interrupt as long as Bit 10 of the PCI Command register has interrupts enabled The data returned for the Memory Read request is discarded by the BMd application since the application is only concerned with the data movement process. Normally, this data would need to be checked for correct order and then loaded into some type of storage element such as a Block ram or fiFo Setting Up the The Bus Master Design connects up to the transaction(TRN)interface of the Endpoint for PCI BMD Design Express. The trN interface is described in detail in the appropriate user guide for the core targeted. The user guides are located in the IP Documentation Center at www.xilinx.com/support/documentation/index.htm Generating the core To generate the core, follow these steps 1. Ensure the latest Xilinx isE design Suite software is installed. The latest software updates arelocatedatwww.xilinx.com/support/download/index.htm 2. Start the core Generator TM software and create a new project 3. Target the appropriate device and generate the core in Verilog 4. In the taxonomy tree, select Standard Bus Interface> PCI Express 5. Select the appropriate endpoint solution for the targeted device and select Customize 6. In the customization gUl, name the core to be generated bmd design 7. Select the correct reference clock frequency for the board targeted. See the board user guide for information on reference clock frequencies available on the board For example the Hi-tech Global board requires a 250 MHz reference clock, and the Ml555 requires a 100 MHz reference clock 8. Depending on the core targeted, the order of customization pages may differ. Ensure the following two changes are made Set the subclass to 0x80 specifying Other Memory Controller Configure baRo to be a 32-bit memory BAR with a 1KB aperture. BAR1 through BAR5 should be disabled 9. Leave all other settings at their defaults and click finish to generate the core Implementing the Bus Master Design To implement the design follow these steps Extract the xapp 1052. zip file to the same level as the example_design directory. A directory called dma_performance demo will be added to the core hierarchy as shown in Figure 5 ame Size Type▲ Odma peformance demo File Folder Odoc File Folder Example design File Folder o implement File Folder asimulation File Folder source File Folder 目v6 pcie readme. tx 7 KB Text Document Figure 5: Design Top Level Hierarchy XAPP1052 (V3.2 )September 29, 201 1 www.xiInx.com 10 【实例截图】
【核心代码】
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