verilog 2001 语法标准

【实例简介】
IEEE verilog 2001 语法标准
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Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through the Copyright Clearance Center About ieee std 1364-2001 version c and the errata During the past two years, the ieee 1364 Working group's Errata Task Force has thoroughly reviewed the Standard and has identified and corrected a number of production and editorial errors that crept in between balloting and printing of the standard IEeE Std 1364-2001 Version c incorporates all of these corrections In addition, during the ieee 1364 Working Groups review of the Standard, the Working group and its Errata Task Force identified other areas where the standard had logical inconsistencies which were not the result of production problems. The Working Group developed an Errata document that identifies these and specifies the Working group's statement as to the correct interpretation of the Standard Copyright 2001 IEEE. All rights reserved Participants-Version C and Errata At the time IEEE Std 1364-2001 Version C and the errata were completed, the IEEe 1364 Working group had the following membership: Michael T. Y (Mac) McNamara, chair Shalom bresticker editor Stefen boyd, Web master Kurt bat Richard ho Anders nordstrom Dennis Brophy Atsushi Kasuya Karen Pieper Clifford e. cummings Jay li Brad Pierce Charles dawson Andrew lynch Steven Sharp Tom Fitzpatrick James a, markevitch Alec stanculescu Krishna garlapat Dennis marsa Stuart Sutherland Keith gover Francoise martinolle Chong Guan Tan Ennis hawk Mehdi mohtashemi Gordon vreugdenhil The Errata Task Force had the following membership Karen Pieper, chair Stefen Boyd, vice chair Kurt batv Andrew lynch Mehdi mohtashemi Shalom bresticke James a markevitch Anders nordstrom Dennis brophy Dennis marsa Brad pierce Clifford E. Cummings Francoise martino David roberts Charles dawson Michael T.Y.( Mac) McNamara Steven Sharp Ted elkind Elliot mednick David smith Tom Fitzpatrick Don mill Stuart Sutherland Jay lawrence Gordon vreugdenhil The Behavioral Task Force had the following membership Steven Sharp Chair Kurt bat Atsushi kasuya Mehdi mohtashemi Stefen boyd Jay Lawrence Karen Pieper Dennis Brophy francoise martinolle Brad pierce Clifford E cummins Michael T. Y (Mac)McNamara Alec stanculescu Tom Fitzpatrick Don mills Stuart sutherland Ennis hawk Gordon vreugdenhil The PLI Task Force had the following membership Charles dawson. Co-Chair Stuart Sutherland. Co-chair Steven dovich Francoise martinolle Nisa parikh Dennis ma David roberts Copyright o 2001 IEEE. All rights reserved Introduction (This introduction is not part of ieEE Std 1364-2001, IEEE Standard Verilog Hardwarc Description Languagc The verilog Hardware Description Language(Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that verilog has been accepted to be the language of choice by an overwhelming number of IC designers Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in which expressions of both variables and nets can continuously drive values onto nets, provide the basic structural construct. Procedural assignments, in which the results of calculations involving variable and net values can be stored into variables, provide the basic behavioral construct a design consists of a set of mod- ules, each of which has an I/O interface, and a description of its function, which can be structural, behav ioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets The Verilog language is extensible via the Programming Language Interface(PLi)and the verilog proce- dural Interface (VPD routines. The Pli/VPi is a collection of routines that allows foreign functions to access information contained in a Verilog hdl description of the design and facilitates dynamic interaction with simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation and CAD systems, customized debugging tasks, delay calculators, and annotators The language that influenced Verilog hdl the most was HILo-2, which was developed at Brunel University in England under a contract to produce a test generation system for the british ministry of Defense HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification simula- tion, timing analysis, fault simulation, and test generation In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open Verilog International(ovi)was formed to manage and promote Verilog HDL In 1992, the board of direc- tors of ovi began an effort to establish Verilog hdl as an Ieee standard. In 1993, the first IEEE Working Group was formed and after 18 months of focused efforts verilog became an Ieee standard as ieee Std 1364-1995 After the standardization process was complete the 1364 Working Group started looking for feedback from 1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five year effort to get a much better Verilog standard in IEEE Std 1364-2001 Objective of the IEEE Std 1364-2001 effort The starting point for the Ieee 13 64 Working Group for this standard was the feedback received from the IEEE Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in all aspects of the language. Users at the higher levels wanted to expand and improve the language at the rtl and behavioral levels, while users at the lower levels wanted improved capability for asiC designs and signoff. It was for this reason that the 1364 Working Group was organized into three task forces: Behavioral ASIC. and Pli Copyright 2001 IEEE. All rights reserved The clear directive from the users for these three task forces was to start by solving some of the following problems Consolidate existing IeeE Std 1364-1995 Verilog generate statement Multi-dimensional arrays EnhancedⅤ erilog file I/c Re-entrant tasks Standardize verilog configurations Enhance timing representation Enhance the vpi routines Achievements Over a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrm The three task forces went through the IEEE Std 1364-1995 LRM very thoroughly and in the process of con solidating the existing lrm have been able to provide nearly three hundred clarifications and errata for the Behavioral, ASIC, and PLI sections. In addition, the vSG has also been able to agree on all the enhance ments that were requested (including the ones stated above) Three new sections have been added. Clause 13, Configuring the contents of a design, deals with configu- ration management and has been added to facilitate both the sharing of verilog designs between designers and/or design groups and the repeatability of the exact contents of a given simulation session. Clause 15 4 Timing checks has been broken out of clause 17, system tasks and functions and details more fully how timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format (SDF), addresses using back annotation (IEEE Std 1497-1999)within IEEE Std 1364-2001 Extreme care has been taken to enhance the vPi routines to handle all the enhancements in the behavioral and other areas of the lrm. minimum work has been done on the pli routines and most of the work has been concentrated on the vpi routines some of the enhancements in the vpi are the save and restart simu lation control, work area access, error handling, assign/deassign and support for array of instances, generate and file 1/o Work on this standard would not have been possible without funding from the Cas society of the IEee and Open verilog International The IEEE Std 1364-2001 Verilog Standards Group organization Many individuals from many different organizations participated directly or indirectly in the standardization process. The main body of the IEEE Std 1364-2001 working group is located in the United States, with a subgroup in Japan(ElAJ/1364HDL) The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to be approved by this group to be implemented. The three task forces focused on their specific areas and their recommendations were eventually voted on by the IEEE Std 1364-2001 working group Copyright o 2001 IEEE. All rights reserved At the time this document was approved, the IEEE Std 1364-2001 working group had the following members Magsoodul aq) mannan, Chair Kasumi Hamaguchi, Vice Chair apan) Alec G. Stanculescu, vice Chair (usa) Lynn A. horobin, secretary Yatin Trivedi. Technical editor The behavioral Task force consisted of the following members Clifford E. Cummings. Leader Kurt Baty Adam Krolnik Karen Pieper Stefen boyd James a, markevitch Steven Sharp Shalom bresticker Michael mcnamara Chris spear Tom Fitzpatrick Anders nordstrom Stuart sutherland The asIC Task Force consisted of the following members Steve Wadsworth. Leader Leigh Brady Tcd elkind ck ry Paul colwill Naveen Gupta Lukasz senator Tom Dewey Prabhakaran Krishnamurthy The PLI Task Force consisted of the following members Andrew T Lynch, Leader Stuart Sutherland. co-Leader and editor Deborah ]. dalio Steve meyer Girish s rao Charles dawson David roberts The IEEE 1364 Japan subgroup(elAj/1364HDL) consisted of the following members Kasumi Hamaguchi, Vice Chair apan) Yokozeki atsushi Makoto makino Hiroaki nishi Yasuaki hatta Takashima mitsuya Tsutomu Someya Tatsuro nakamura Copyright 2001 IEEE. All rights reserved The following members of the balloting committee voted on this standar Masato ikeda Shigehiro asano Mitsuaki ishikawa Yoichi onishi Peter ashenden Neil g. Jacobson Uma P Parvathy Victor berman Richard O. Jones William. paulsen J Bask Osamu Karatsu Karen L Pieper Stefan Boyd Jake Karrfalt Girish s rao Dennis B. brophy Masayuki Katakura Jaideep re Keith Chow Kaoru Kawamura Francesco sforza Clifford E. Cummings Masamichi kawarabayashi Charles f Shelor Brian a. dali Satoshi Kojima Chris spear Timothy. davis Masuyoshi kurokawa Alec G. stanculesct Charles dawson Gunther lehmann Steve start Douglas D). Dunlop Andrew lynch Stuart sutherland Ted elkind Serge maginot Masahiko Toyonaga Joerg- Oliver Fischer-Binder Magsoodul mannan Yatin K. trivedi Peter Flake James a, markevitch Cary usser Robert a. flatt Francoise martinoll Steven d. wadsworth Masahiro fuku Yoshio masubuch Sui-Ki W Kenji Goto Paul j menchini Ronald waxman Navccn Gupta Hiroshi mizuno John m. william Andrew guyler Egbert molenkamp John Willi Yoshiaki hagiwara John T Montague Takashi yamada Anne c. harris Akira motohara obin Hiroaki nishi Hirokazu yonezawa Chilai huang Anders nordstrom Tetsuo yutani Takahiro Ichinomiya Mark zwolinski When the IEEE-Sa Standards board approved this standard on 17 March 2001, it had the following membership Donald n. heiman chair James t, carlo. Vice chair Judith Gorman, Secretary Satish K. Aggarwal James h. gurney James moore Mark d. bowman Richard holleman Robert f munzner Gary R Engmann Lowell G. johnson Ronald c. petersen Harold e. epstein Robert. Kennelly Gerald. peterson H. Landis floyd oseph L. Koepfingerx John B. posey Jay forster Peter H. lips Gary S. Robinson Howard m. frazier L. Bruce McClung Akio Tojo Ruben d.Gar∠On Daleep c mohla Donald w. Zipse *Member emeritus Also included is the following nonvoting ieee-sa Standards board liaison Alan Cookson, NIST Representative Donald R. Volzka, TAB Representative Andrew ickowicz TEEE Standards project editor Verilog is a registered trademark of cadence design Systems, Inc 111 Copyright o 2001 IEEE. All rights reserved Contents 1. 1 Objectives of this standard 1. 2 Conventions used in this standard 1.3 Syntactic description ……… 1. 4 Contents of this standard 1.5 Header file listings 1.6 Examples… 1.7 Prerequisites...... Lexical conventions 2.1 Lexical tokens 22 White space………… 2.3 Comments 455666666 24 Operators………… 2.5 Numbers 2.5.1 Integer constants 2.5.2 Real constants… 2.5.3 Conversion 2.6 Stril 2.6.1 String variable declaration..... 11 26.2 String manipulation……… 11 26.3 Special characters in strings.…… 2.7 Identifiers, keywords, and system names 12 2.7. 1 Escaped identifiers 2.7.2 Generated identifiers 13 2.7.3 Keywords.. 13 2.7.4 System tasks and functions 13 2.7.5 Compiler direct 14 2.8 Attribut 14 2.8.1 Examples 2.8.2 Syntax 3. Data types 20 3.1 Value set 3.2 Nets and variables 3. 2. 1 Net declarations 3.2.2 Variable declarations 3. 3 Vect 3.3. 1 Specifying v 3.3.2 Vector net accessibility 24 3. 4 Strengths 3.4.1 Charge strength 24 3.4.2 Drive strength 3.5 Implicit declarations 3.6 Net initialization 3.7 Net types………… 3.7.1Wi 3.7.2 Wired ne 26 Copyright C 2001 IEEE. All rights reserved 【实例截图】
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