Design Compiler User Guide

【实例简介】
Design Compiler User Guide 官方用户手册完整版2011版本
Copyright Statement for the Command-Line Editing Feature Copyright o 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software contributed to berkeley by christos zoulas of cornell University Redistribution and use in source and binary forms, with or without modification are permitted provided that the following conditions are met Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution 3. All advertising materials mentioning features or use of this software must display the following acknowledgement This product includes software developed by the University of California, Berkeley and its contributors 4. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS " AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED, N NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OI SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY. WHETHER IN CONTRACT. STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Copyright Statement for the Line-Editing Library Copyright@ 1992 Simmule Turner and Rich Salz. All rights reserved This software is not subject to any license of the american Telephone and Telegraph Company or of the Regents of the University of California Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and redistribute it freely, subject to the following restrictions 1. The authors are not responsible for the consequences of use of this software no matter how awful even if they arise from flaws in it 2. The origin of this software must not be misrepresented, either by explicit claim or by omission Since few users ever ead sources, credits must appear in the documentation 3. Altered versions must be plainly marked as such, and must not be misrepresented as being the original software Since few users ever read sources, credits must appear in the documentation 4. This notice may not be removed or altered Design Compiler User Guide, version F-2011.09-SP2 Design Compiler User Guide, version F-2011.09-SP2 Contents What's new in this release about this manual ■■■■■■m XXI Customer Support 1■■■■口■口 1D面 1. Introduction to Design Compiler Design Compiler and the Design Flow 1 1重 1-2 Design Compiler family 1-3 DC Expert 1-4 DC Ultra.,,,,,,,,,,, HDL Compiler Tools DesignWare Library 15 DE T Compiler 15 ower compiler 15 Design visi 1-5 2. Design Compiler basics The High-Level design Flow 2-2 Running Design Compiler 2-4 Design Compiler Interfaces 2-5 Setup files 2-5 Starting Design Compiler. 27 Exiting Design Comp 2-8 pening and Closing the gUI in dc_shell 2-8 Design Compiler User guide Version F-2011. 09-SP2 Getting Command Help 29 Using Command Log Files 2-10 Using the Filename Log File 2-10 Ising Script Files 2-10 Support for multicore Technology 1重■1 2-11 Using Multicore Functionality 2-11 Measuring Runtime 2-11 Support for Multicorner-Multimode Designs 2-12 Forking With Licenses 2-13 Listing the Licenses in Use 2-13 Getting Licenses 2-13 Enabling License Queuing 2-14 Releasing licenses 2-15 Following the basic synthesis flow 2-15 A Design Compiler session Example 2-20 3. Preparing Design Files for Synthesis Managing the Design Data _· 3-2 Controlling the Design Data Organizing the design data 3-2 Partitioning for Synthesis Partitioning for design Reuse eeping Related Combinational Logic Together 35 Registering Block Outputs 36 Partitioning by Design Goal 3-7 Partitioning by Compile Technique Keeping Sharable Resources Together 38 Keeping User-Defined Resources With the Logic They Drive 38 Isolating Special Functions 3-9 HDL Coding for Synthesis. 3-10 Writing Technology-Independent HDL 3-11 Interring Components 3-11 Designing State Machines 3-14 Using HDL Constructs 3-15 Contents Design Compiler User guide Version F-201 1. 09-SP2 General HDL Constructs 3-15 Using Verilog Macro Definitions 3-18 Using VHDL Port Definitions 3-19 Writing Effective Code 3-19 Guidelines for Identifiers 3-19 Guidelines for Expressions 3-21 Guidelines for functions 3-21 Guidelines for modules.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 3-23 Working with Libraries Selecting a Semiconductor Vendor 4-2 Understanding the Library Requirements 4-2 Technology Libraries ■■■ 4-3 Symbol Libraries∴.. 4-4 DesignWare Librarie 4-4 Specifying Libraries 4-5 Specifying Technology Libraries............. 4-5 Target Library 4-5 Link library 4-5 Specifying Design Ware Libraries 4-7 Specifying a Library search Path 4-8 Loading Libraries 4-8 Listing Libraries 4-9 Reporting Library Contents 49 Specifying Library Objects 4-9 Directing Library Cell Usage 4-10 Excluding Cells From the Target Library 4-10 Specifying Cell Preferences ■口■ 4-11 Library-Aware Mapping and Synthesis 4-12 Generating the ALIB file 4-12 Using the ALiB library 4-12 Removing Libraries From Memory 4-13 Saving libraries 4-14 Contents Design Compiler User guide Version F-201 1. 09-SP2 5. Working With Designs in Memory Design Terminology ■■■ 5-2 About Designs 5-2 Flat Designs 5-2 Hierarchical Designs 5-2 Design objects 5-3 Relationship Between Designs, Instances, and References 5-5 Reporting References Using Reference Objects 55 Reading Designs 5-6 Commands for Reading Design Files 5-6 Using the analyze and elaborate Commands 5-7 Using the read_file Command 58 Reading HDl designs 5-10 Reading ddc Files. 5-11 Reading. db Files 5-11 Listing Designs in Memory 5-11 Setting the Current Design 5-12 Using the current_design Command 5-13 Inking Designs 5-13 Locating Designs by Using a Search Path 5-15 Changing Design References 5-15 Listing Design Objects 5-16 Specifying Design Objects 5-17 Using a relative Path 5-17 Using an Absolute Path 5-18 Creating Designs……… 5-19 Copying Designs 5-20 Renaming designs 5-21 Changing the design hierarchy 5-22 Adding Levels of Hierarchy ■日■口口m 5-22 Grouping Cells Into Subdesigns 5-22 Removing Levels of Hierarchy 5-25 Ungrouping Hierarchies Explicitly During Optimization 5-28 Contents Design Compiler User guide Version F-201 1. 09-SP2 Ungrouping Hierarchies Automatically During Optimization 5-28 Merging Cells From Different Subdesigns 5-31 Editing Designs 5-31 Translating Designs From One Technology to Another 5-33 Translating Designs in Design Compiler 5-33 Translating Designs in Design Compiler Topographical Mode 5-34 Restrictions on Translating Between Technologies 34 Removing Designs From Memory 5-35 Saving Designs 5-35 Commands to save design Files 5-36 Using the write Command ■■■ 5-36 Using the write_ milkyway command 5-37 Saving Designs in. ddc Format 5-37 Ensuring Name Consistency Between the Design Database and the netlist 5-38 Naming Rules Section of the synopsys_dc setup File 5-38 Using the define_name_rules-map Command 5-38 Resolving Naming Problems in the Flow 5-39 Working With Attributes 5-40 Setting Attribute values 5-41 Using an Attribute-Specific Command 5-41 Using the set_attribute Command 5-42 Viewing attribute values 5-42 Saving attribute values 5-43 Defining Attributes 5-43 Removing attributes 5-43 The Object Search Order 5-44 6. Defining the Design Environment Defining the Operating Conditions Determining Available Operating Condition Options 63 Specifying Operating Conditions 6-4 Defining Wire Load Models 6-4 Hierarchical Wire load models 6-5 Determining Available Wire load models Contents Design Compiler User guide Version F-2011. 09-SP2 Specifying Wire Load Models and Modes 6-8 Modeling the System Interface 6-10 Defining Drive Characteristics for Input Ports∴..∴..∴.∴∴. 6-10 The set_driving_cell Command 6-11 The set_drive and set_input_transition Commands 6-11 Defining Loads on Input and Output Ports 6-13 Defining fanout loads on output ports 6-13 Setting Logic Constraints on Ports 6-14 Defining Ports as Logically Equivalent 6-14 Defining Logically Opposite Input Ports 6-15 Allowing Assignment of Any Signal to an Input 6-15 Specifying Input Ports Always One or Zero 6-16 Tying Input Ports to Logic 1 6-16 Tying Input Ports to Logic 0 6-17 Specifying Unconnected Output Ports 6-17 Specifying Power Intent 6-18 Power Intent Concepts 6-18 UPF Commands in Synopsys tools 6-19 set_scope 6-21 load upf 6-22 save_ up 6-22 Support for Multicorner-Multimode designs 6-22 7. Defining Design Constraints Design Compiler Constraint Types 7-2 Design Rule Constraints 7-3 Design Rule Cost Function Maximum transition Time Defining Maximum Transition Time 7-5 Specifying Clock-Based Maximum Transition 7-5 Maximum fanout 7-6 Maximum Fanout Calculation Example 7-7 Defining Maximum Fanout ■■■■着 7-8 Defining expected Fanout for output ports 7-8 Maximum Capacitance 7-9 Defining Maximum Capacitance 7-9 Contents 【实例截图】
【核心代码】