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VPX标准草案(vita46d0-r0d11)

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  • 实例大小:1.35M
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  • 发布时间:2020-08-01
  • 实例类别:一般编程问题
  • 发 布 人:robot666
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实例介绍

【实例简介】
仅供硬件开发参考,VPX标准草案(vita46d0-r0d11)
3. 8 Connector Pin Definition -P1 26 4 3U MODULE 28 4.1 Overview -3U Module 28 4.2 Connectors-3U Module. 4.3 Alignment and Keying-3U Module. 4.4 Connector Pin Definition -3U Module p2 29 4.4.1 Locations on 3U module for User defined connector ........................................29 4.4.2 Standard Connector P2 29 5 6U MODULE 31 5.1 Overview 香。···看。鲁垂·D。··音●。·b·垂自··。,·。q 。。。1 31 5.2 Connectors 31 5.3 Alignment and Keying.......... 32 5.4 Connector pin Definition 32 5.4.1 Connector P2 .32 5.4.2 Connector P3. ...........................................................................................................33 5.4 3 Connector P4 看音番 35 5.4.4 Locations for User defined Connectors 36 5.45 Connector ps 37 5.4.6 Connector P6 .38 6 BACKPLANES 41 6.1 Overview 41 6. 1. 1 Backplane Dimensions 41 6.1.2 Power Delivery……………………… 41 6.1. 3 Connector Selection ···.··:·.···: 41 62ⅤITA46 slot numbering……,…,…,…,…,…,…,…,…,…,…,…,…,…,…,…,……242 6.3 Required Connections 43 6.3.1 JTAG Pin allocation …………………43 6.3.2 System Management Connections 44 6.3. 3 System Reference Clock...........44 6.3. 4 Non-Volatile Memory read only 144 6.3.53.3VAUX 45 6.3.6 SYSRESET 45 Do not specify or claim conformance to this document Page 2 of 75 VITA460-200xD0.11 8/30/2005 64 Backplane Fabric Connections Electrical Requirements……,…,,…,…45 6.4.1 Backplane Fabric Connections Signal Integrity Requirements 45 6.4.2 Backplane materials · 45 6.4.3 Differential Fabric Connector routing..............46 6.4.4 Trace length matching, trace widths and spacing……………………………46 6.4.5 Spacing..... 47 6.4.6 6.4.6 Trace lengths 47 6.4.7 Crosstalk isolation …47 6. 4. 8 Insertion loss .48 6.5 Hybrid Back plane. 66 Backplane Pin Mappings( Reference only)…........…,… 48 7 SYSTEM 54 7.1 Safety Ground.…...........54 7.2 Power Supply.............................54 7.2.1 Capacity 54 7. 2.2 Voltage levels 7.2.3 Dielectric Separation 56 7.3 Slot Type Indication.………,,…,,…,,…,,…,…,…,…,…,,,…,,,,,…,,56 74 Glyphs… b看●e。。 56 Do not specify or claim conformance to this document Page 3 of75 VITA460-200xD0.11 8/30/2005 List of Figures FIGURE 3-1 CONNECTOR IDENTIFICATION FOR 3U AND 6U MODULES 18 FIGURE A-13 U AIR COOLED MODULE LAYOUT∴….……………………………………57 FIGURE A-23 U CONDUCTION COOLED LAYOUT……… 60 FIGURE A-3 6U AIR COOLED LAYOUT FIGURE A-4 6U CONDUCTION COOLED LAYOUT 62 FIGURE A-5 3U CONDUCTION COOLED MODULE END VIEW 63 FIGURE A-6 6U CONDUCTION COOLED MODULE END VIEW 64 FIGURE A-7 3U CHASSIS SIDE WALL 65 FIGURE A-8 MODULE SIDE VIEW ,66 FIGURE B-1 3U AIR COOLED BACKPLANE PLAN VIEW 67 FIGURE B-2 6U AIR COOLED BACKPLANE PLAN VIEW 音音。·音音音垂音音 FIGURE B-3 3U CONDUCTION COOLED BACKPLANE PLAN VIEW 69 FIGURE B-4 6U CONDUCTION COOLED BACKPLANE PLAN VIEW .垂· 70 FIGURE B-5 6U BACKPLANE END VIEW FIGUREC-1 3U PCB FABRICATION DRAWING 72 FIGURE C-2 6U PCB FABRICATION DRAWING List of tables TabLE 3-1 MODULE PO AND PI CONNECTORS 19 TABLE 3-2 PO UTILITY CONNECTOR …20 TABLE3-3 PO SIGNAL DEFIⅠ NITIONS( SEE TEXT FOR ADDITIONAL DETAILS).…………21 TABLE 4-1 3U MODULE CONNECTORS 28 TABLE 4-2 3U MODULE P2 DIFFERENTIAL PINOUT. ...................................................................29 TABLE4-33 U MODULE P2 SINGLE- ENDED PINOUT∴…………………………………30 TABLE 5-1 6U MODULE CONNECTORS 31 TABLE 5-2 6U MODULE P2 DIFFERENTIAL PINOUT ···看 32 TABLE 5-3 6U MODULE P2 SINGLE-ENDED PINOUT TABLE 5-4 6U MODULE P3 DIFFERENTIAL PINOUT 34 TABLE 5-5 6U MODULE P3 SINGLE-ENDED PINOUT 34 TABLE5-66 U MODULE P4 DIFFERENTIAL PINOUT,…………35 TABLE 5-7 6U MODULE P4 SINGLE-ENDED PINOUT 36 ··,···,····, TabLE 5-8 6U MODULE PS DIFFERENTIAL PINOUT 37 TABLE5-96 U MODULE P5 SINGLE- ENDED PINOUT……………………38 TABLE 5-10 6U MODULE P6 DIFFERENTIAL PINOUT.......39 TABLE5-116 U MODULE P6 SINGLE-ENDED PINOUT∴……………39 TABLE 6-1 CURRENT AND POWER AVAILABLE PER SLOT 41 TABLE6-2 GEOGRAPHICAL ADDRESS PIN ASSIGNMENTS………42 TABLE6-3 JTAG SIGNALS…… 43 TABLE 6-4 PO ( UTILITY CONNECTOR) BACKPLANE MAPPING ........49 TABLE 6-5 P1 (DIFFERENTIAL) BACKPLANE MAPPING 49 Do not specify or claim conformance to this document Page 4 of75 VITA460-200xD0.11 8/30/2005 TABLE 6-6 P2 (DIFFERENTIAL) BACKPLANE MAPPING 49 TABLE6-7P2( SINGLE-ENDED) BACKPLANE MAPPING…,…,…,…,…,…,…,…………50 TABLE6-8P3( DIFFERENTIAL) BACKPLANE MAPPING.,,…,…… 50 TABLE 6-9 P3(SINGLE-ENDED) BACKPLANE MAPPING....................51 TABLE6-10P4( DIFFERENTIAL) BACKPLANE MAPPING……,…,,…,,…,…,……………51 TABLE 6-11 P4 (SINGLE-ENDED) BACKPLANE MAPPING 51 TABLE 6-12 P5(DIFFERENTIAL) BACKPLANE MAPPING 52 TABlE6-13P5( SINGLE-ENDED) BACKPLANE MAPPING……,…, 2 TAbLE6-14P6( DIFFERENTIAL) BACKPLANE MAPPING………… TABLE 6-15 P6 (SINGLE-ENDED) BACKPLANE MAPPING 53 Do not specify or claim conformance to this document Page 5 of 75 VITA460-200xD0.11 8/30/2005 Abstract This standard describes Vita 46.0 Advanced Module Format for VMEbus systems,an evolutionary step forward for the provision of high-speed interconnects in harsh-environment applications Foreword ME has been the de-facto bus standard for Commercial off the Shelf( cots) Circuit Card Assemblies since the 1980s. vme boards have proven to be remarkably capable of evolving to support newer technologies with innovations such as VME Subsystem Bus, PCI Mezzanine Cards(Pmcs)and VmE320 However, advances in technologies, appearing particularly in interconnects, have demonstrated the need for an advance in system development. This advance needs to accommodate high speed interconnect, particularly serial interconnects, and higher power delivery in concert with better heat removal This draft standard addresses these needs in the context of ieee 110l form factor modules Other specifications may address alternate outlines, such as VITA-48 Draft Because electronics miniaturization is driving the plug-in module i/o count, most system interconnects will need Multi-gigabit diffcrcntial tcchnology Core computing cluster switched fabrics Serial rapidIo, PCI Express, Advanced Switching Interconnect Sufficient ports to enable distributed switching or centralized switching The plethora of high-speed interfaces available for tomorrow's plug-in modules Network interfaces( Fibre Channel, 10 GbE XAUL, Infiniband Digital video(TmDs, Panellink, OpenLDI Mass storage interface(Fibre Channel, Serial ATA FPGA-based inter-board connections(e. g. Xilinx RocketIO) Custom sensor interfaces VITA 46 provides an evolutionary rOadmap for Vme users To leverage the broad spectrum of high-spccd interconnect technologics Backward compatibility with vme bus electrical, software and selected mechanicals Enables heterogeneous architectures which preserve existing investments in COTS-based systems Addresses both 3U and 6u form factors with commonality Harsh environment fit 'designed-in'up front in the standard Rugged air or conduction-cooled form factors High value placed on rear-panel I/o High-speed connector survivability/compliance Do not specify or claim conformance to this document Page 6 of 75 VITA460-200xD0.11 8/30/2005 Connector with ESD protection, and options for handling covers to accommodate 2-level maintenance Space constrained - high compute density applications Other defense and aerospace market needs are also under consideration standards Innovation is the Cots Industry's Most Compelling Value Proposition Do not specify or claim conformance to this document Page 7 of 75 VITA460-200xD0.11 8/30/2005 Working Group Members At the time this standard was completed, the Working group for this standard had the following membership Name Company Nauman arshad Curtiss-Wright Controls Embedded computing Randy banton Mercury Computer systems Steve belvin i-b-S-1 Rodger bird Boeing Ken boycttc Critca Computcr Melissa heckman Bustronic Gorky Chin Curtiss-Wright Controls Embedded Computing David compston Radstone Stewart dewar Curtiss-Wright Controls Embedded Computing Gerard Drewek General Dynamics-AIS Chris eckert SBS Technologies, Inc. Jim Fedder Greg Griffith Tyco Bill Hanna boeing Richard Hodges Parker-Hannafin Richard Jaenicke Mercury Computer Systems Aaron Raiway pectrum Signal Processing Emil Kheyfets Curtiss-Wright Controls Embedded Computing Steve Konsowski Northrop grumman Jing Kwok Curtiss-Wright Controls Embedded Computing Tony Lavely Mercury Computer Systems Michael monroe Elma Bustronic Corp Tim Moty ka Northrop grumman Bill northey FCI Elwood parsons Foxconn Bob patterson Tyco David Pepper GE Fanuc Jim roble Bocing John rynearson VITA Jacob sealander Curtiss-Wright Controls Embedded Computing Mike shorey Mercury computer systems Andrew Spence Amphenol backplane systems Jeff smith GHz SyStems, Inc Ivan Straznicky Curtiss-Wright Controls Embedded Computing Bob sullivan Hybricon Bruce Thomas Curtiss-Wright Controls Embedded Computing Larry Thompson Crane div, Naval surface Warfare Center Michael Thompson Penlair Electronic Packaging(schroon) Dan Toohey Mercury Computer Systems Bob Fulford MoLorola Embedded CommunicaTions Computing John Wemekamp Curtiss-Wright Controls Embedded Computing Do not specify or claim conformance to this document Page 8 of 75 VITA460-200xD0.11 8/30/2005 The following people were on the sponsor balloting committee Name Company When the ansi Standards board approved this standard on Xxxx xx, 200x, it had the following membershi Name Company Comments. Corrections andor additions Anyone wishing to provide comments, corrections and/or additions to this proposed standard, please direct them to the draft editor Tony Lavely Mercury Computer systems, Inc 199 Riverneck Road Chelmsford. MA USa 01824 19789671272 E-mail: atlamc com The best way to provide corrections and small additions is via marking up the specific pages and e-mailing them to the chair. For longer additions, the chair still prefers to receive textual information via e-mail. If mechanical drawings are involved they should be done with AutoCAD. This document is being prepared with microsoft word 2003 for Windows compatible computers Do not specify or claim conformance to this document Page 9 of 75 VITA460-200xD0.11 8/30/2005 【实例截图】
【核心代码】

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