实例介绍
【实例简介】
详细讲解ZYNQ开发过程所涉及到的技术，包括环境搭建、ZYNQ小系统，fsbl创建、uboot编译以及创建，对刚入门ZYNQ的开发者会有很大帮助
Processing System(PS) 1o Peripherals Reset 2X SPI Application Processor Unit (APU) Clock SWDT 2x|2C NEONTM/ FPU Engine NEONTM/ FPU Engine Generation ITTC 2X CAN Cortex TM-A9 Cortex TM-A9 System MMU MPCore TM MMU MPCore TM 2X UART CPU CPU GPIO Control 32 KB I 32 KB D 32 KB I 32 KB D 2X SD/SDIO Regs Cache Cache Cache Cache with DMA O Snoop Control Unit ACP DMA 8 KH MUX 2X USB Channel 512 KB L2 Cache Controller (MIO) with dMA OCM 256 KB OCM 2X GigE Core Sight TM Interconnect with DMA BootROM Central Components FLASH Memory Interconnect Interfaces DAP SRAMINOR Memory Interfaces NAND DEVC Programmable DDR2/3, LPDDR2 Quad sPl Logic to Memory Controller Interconnect Extended mio General Purpose DMA Config IRQ High Performance XADC (EMIO) Master Slave Ports Sync Al Ports AMBAB Connection Legend Programmable Logic(PL) Select GTX Arrow direction shows control Data flows both directions Configurable AXI3 32 bit/64 bit AXI3 64 bit/Ax 3 32 bit/AHB 32 bit/ APB 32 bit PCle Gen2 E XILINX zynq③-7000AⅢ Programmable Soc Family Cost-optimized Devices Mid-Ranee Devices Device NameS-7007s2-701252-70145z-7010z7015z-7020 Z-7030 Z-7035 z-7045 Z-7100 Part Number XC7Z007S XC7Z012S XC72014S XC72010 XC7Z015 XC72020XC72030 XC7Z035 XC72045 Xc了2100 Singile-Core Dua - ari Dual-Coreari Processor Core ARM Cortex"w-A9 MPCore Ta Cortex-A9 MPCore Cortex-A9 MPCore Up to 766MHz Up to 866MHz Up to 1GHz1) Processor Extensions NEON SIMD Enzine and Single/Double Precision Floating Point Unit per processor L1 Cache 32KB Instruction, 32KB Data per processor L2 Cche 512K日 On-Chip Memory 255KB External Memory Support/2 DDR3 DDR2PDDR2 Extemal Static Memory Support 2x Quad-SPI, NAND NOR DMA Channels 8(4 dedicated to PLy Peripherals 2x UART 2x CAN 208.2x 2C.2x. 4x32bGP0 Peripherals w/ built-in DMA2 2x USB 2.0 [ OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO RsA Authentication of first stage boot loader Security AES and sHA 256b Decryption and Authentication for Secure Boot 2x AX32b Master 2xAx 32b slave Processing System to Programmable Logic Interface Ports 4xAⅪ64b/32 b Memory AX 64bACP Primary Interfaces Interrupts Only) 16 Interrupts 7 Series PL Equivalent| Artix-7 Artix-7 Artix-7Artix-7 Artix-7 Artix-7 Kintex-7 Kintex-7 Kintex-7 Kintex-r Logic Cells 23K 55K 55K 28K 了4K 85K 125K 275K 350K 444K Lok- Up Tables(Ts144034404060017,604620053,200 171900 218,600 277400 Fip-Flop288006880081,2003520092400106400 157200 343.800 437,200 55400 Total Block RAMI 1.8Mb 2.5Mb 3. SMb 2.1Mb 3.3Mb 4.9Mb 9.3Mb 175Mb 91Mb 26.5Mb I#36Kb Blocks)(50 72 (107 60 95 140) 25) 50o 545 755 DsP Slices 65 120 170 160 22D 400 2020 PCI Express Gen2 x4 Gen2 x4 Gen2 x4 Gen2 x8 Gen2 x8 EE.E G∈n2x8 Analog Mixed Signal(AMS)/XADC2 2x 12 bit, MSPS ADCs with up to 17 Differential Inputs Security AES & SHA 256b Decryption E Authentication for Secure Programmable Logic config Commercial 1 Speed Grades Extended 23 3 Industrial 1.-2 1.-2,-2L 1,-2.-2L E XILINX L XILINX ALL PROGRAMMABLE 开发全过程 开发流程框图 Install xilinx Tools System Design Application Hardware Design Development Vivado IPl: Configure Ps Develop RTL/IP SDK: Build Compile Fetch Sources: U-boot, Linux: Ram Disk Add /Integrate IP Application Code Generate Bitstream s Export to SDK BuildBuild Create*Create Hardware handoff U- boot Linux‖ RamDisk ATE Application System Software Code Binary (hdf). U-boot Julmage uRam Disk ATF Development Bitstream SDK/ HSI: Create FSBL Create Devicetree FSBL SDK/ Bootgen: Create Boot Image :Create PMUFW PMUFW BOOT. BIN For Zynq UltraScale+ MPSoC Booting and Running Linux designs only Target Platform E XILINX 工具 Vivado 2016.4 回x File F。13置 indow Help Q- Quick Access VIVADO E XILINX HLr Editions ALL PROGRAMMABLE Quick Start Recent Projects c H: /Workspace/0703 baochuang/pcie/pcie zcT02 / Workspace/0530 guao/zc702 Create lew Project Open Project Open Example Project project 1 H:/Workspace/0621 baochuang/project 1 Tasks pcie E: /*pcie/pcie 售國已 roject 1 Recent Checkpoi Manage IP Xilin icl store post_synth.dop h:/Workspace/0503 shannon/pro Information center post synth. dcp H:/ Workspace/0503 shannon/pr top_route design_count_11_12301630 dcp H=/Workspace/0504 shannon/12301630 prfailed project/12301 black_ box. dep Document ation and tutorial Quick iake videos Release otes Guid H: /Workspace/0503 shannon/pro top route_count_ss_20170410 dcp Tcl Consol start_Eul e a Icl command her e K XILINX 硬件平台拾建 ZC702-[H /Workspace/ 0705_guao/c702/zc702xpr)-Vivado 2016 4 N87 回 Eile Edit Flow Iools Lindow Layout liew Help 点我加速 Q-Quick Access 已的自自×争D%∑2: it layout 汉◆ avi gator ock Desiga- design 1 X Q島 Pr。ject團 an:ger 品di1 品aeie_1 Project Settings Add sources anguage Templates TF IP Catalog 日日 IP Integrator Search:Q'rynq Create Block Design 5 urces E Design画sals圖 Board Open block lesig t Generate Block Desig Simulation <g Simulation Settings Run simulation RIL Analysis Icl Console El aboration Settings F ( createproject ze702H: / Workspace/0705guao/zc702-"part xcz02021g404-1 pen卫1 borated Desi ClFO: [IP Flow 19-234] Refreshing IP repositories [LIFO: [IP- Flow 19-1704] Io user IP repositories specified anthesis AILIFO:[IP_Flow 19-2313] Loaded Vivado IP repository D: /Xilinx/Vivado/2016.4/data/iy' 费 Synthesis Settings set property board part xilinx. com: zc702: partO: 1. 2 [current project] EITER to select, ESC to cancel, Ctrl+Q for IP details Run synthe s15 createbd_design desi en_1 e create_bd_design: Time (s): cpu 00: 00: 08: elapsed=00: 00: 05. Memory (MB): peak 867 230: gain 15. 422 Implementation lementation Setti Run Implementati Type a Tel command here un E XILINX 硬件平台拾建 02-[H: /Workspace/0705__guao/zc702/zc702 xpr]-Vivado 2016.4 回_义 EditFlow Tools Mind[ Re-customizeIP 点我加速 Quick access Re乱dy ZYNQ Processing Syste (5. 5) Flow lavi gator I Documentation Presets P IP Location (f Import XPS Settings Page lavi gat Zyng block design Summary Report 4Pr。1e Nan乱ger Lyng Block Design Project sett vO Peripherals Genera Add source PS-PL Confi guration P|0 set ngs Application Processor Unit (APU SWDT Language Templates Peripheral I/o Pir Hanan 12C0 TTC M LP Catalog M Cortex-A9 ARMC怒x9 MIO Confi guration CANO System Level CAN1 d IP Integrator Contol reds Clock Confi guration UART0 MUX Snoop Contrd unt Open Block Design ⑩ R Configuration M|) DMAB Channel 512KB L2 Cache and Centro er USB0 oCM 256K日 4 Simulatie Cves ght SRAM interrupts NETO 8 Simlation Settings ENET 1 Central Comoonents interconnect M Run Simulation FLASH Memory ntedaoeg SRAMNOR Memory Interlaces RIL Analysis QUAD SPI DEvC DDR233 LPDDR2 128 Loac wM Inteconnect 0pen卫 laborated D SMG Timna Canton DMA ync Synthesis Processing System(PS) a23 0112|3 DMA Run Synthesis 82bGP Channeis Hoh Pedomamge XADC MID (EMO) cock fots AXI 32b/84b Save Open synthesized D SHA Pot Pote Ports A Implementation Implementation Setti Programmable Logic(PL) Run Implementation Open Implemented Des OK Cancel E XILINX 硬件平台拾建 y zc702-[H: /Workspace/0705- guao/zc702/zc702 xpr]-Vivado 2016.4 Eile edit卫Iq1sind: Layout wie青1e1lp 点我加速 Q Quick Access 日的朗自自X争D∑同里utgt·豢N|思 e: dy Flow Navi gator Block Desig- desi gn 1 Q园粤 ources □L 4 Project圃 anager 圳热 口De5 i gn Sour ces(1) Project settings @品e1rer( design l wrapper. v)) or Add sources E-a design 1_i-design 1 (design 1. bd)(1) Q Language Templates Eoe design 1 (design 1.v)(1) aFa processing_system70-design 1 process IP Catalog R.n fonetrainte Ⅲl processing sy stem? 0 TP Integrator Hierarchy IP Sources Libraries Compile Order ekue品sm(easl(lad R中 ZYNQ DDDR FIXED_10中 DFIXED_IO e Properties ZINgT Process ing System ve design 1 wrapper.v e Simulation Setti eral Properties RTL Anal Elaboration Settings endgroup Verilog Output written to: H: Workspace/ 0705_guao/zc702/zc702 srcs/sources 1/bd/desi gn 1/hdl/design_1v Synthesis Setting Rum synthesis import_ files-force -norecurse H: /Workspace/0705_Euao/zc702/zc702 srcs/sources_1/bd/design _1/hdl/design_1_wrapper.v Open Synthesized Des update_compile_order -fileset sources_1 update_ compile order -fileset sim_ 1 Implementation > Sett Run Implementation ype a Tcl command here 量0 pen Implemented Des Iel Console O Me:55国Lg国 ReportsDesig甲nkms E XILINX 【实例截图】
【核心代码】
详细讲解ZYNQ开发过程所涉及到的技术，包括环境搭建、ZYNQ小系统，fsbl创建、uboot编译以及创建，对刚入门ZYNQ的开发者会有很大帮助
Processing System(PS) 1o Peripherals Reset 2X SPI Application Processor Unit (APU) Clock SWDT 2x|2C NEONTM/ FPU Engine NEONTM/ FPU Engine Generation ITTC 2X CAN Cortex TM-A9 Cortex TM-A9 System MMU MPCore TM MMU MPCore TM 2X UART CPU CPU GPIO Control 32 KB I 32 KB D 32 KB I 32 KB D 2X SD/SDIO Regs Cache Cache Cache Cache with DMA O Snoop Control Unit ACP DMA 8 KH MUX 2X USB Channel 512 KB L2 Cache Controller (MIO) with dMA OCM 256 KB OCM 2X GigE Core Sight TM Interconnect with DMA BootROM Central Components FLASH Memory Interconnect Interfaces DAP SRAMINOR Memory Interfaces NAND DEVC Programmable DDR2/3, LPDDR2 Quad sPl Logic to Memory Controller Interconnect Extended mio General Purpose DMA Config IRQ High Performance XADC (EMIO) Master Slave Ports Sync Al Ports AMBAB Connection Legend Programmable Logic(PL) Select GTX Arrow direction shows control Data flows both directions Configurable AXI3 32 bit/64 bit AXI3 64 bit/Ax 3 32 bit/AHB 32 bit/ APB 32 bit PCle Gen2 E XILINX zynq③-7000AⅢ Programmable Soc Family Cost-optimized Devices Mid-Ranee Devices Device NameS-7007s2-701252-70145z-7010z7015z-7020 Z-7030 Z-7035 z-7045 Z-7100 Part Number XC7Z007S XC7Z012S XC72014S XC72010 XC7Z015 XC72020XC72030 XC7Z035 XC72045 Xc了2100 Singile-Core Dua - ari Dual-Coreari Processor Core ARM Cortex"w-A9 MPCore Ta Cortex-A9 MPCore Cortex-A9 MPCore Up to 766MHz Up to 866MHz Up to 1GHz1) Processor Extensions NEON SIMD Enzine and Single/Double Precision Floating Point Unit per processor L1 Cache 32KB Instruction, 32KB Data per processor L2 Cche 512K日 On-Chip Memory 255KB External Memory Support/2 DDR3 DDR2PDDR2 Extemal Static Memory Support 2x Quad-SPI, NAND NOR DMA Channels 8(4 dedicated to PLy Peripherals 2x UART 2x CAN 208.2x 2C.2x. 4x32bGP0 Peripherals w/ built-in DMA2 2x USB 2.0 [ OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO RsA Authentication of first stage boot loader Security AES and sHA 256b Decryption and Authentication for Secure Boot 2x AX32b Master 2xAx 32b slave Processing System to Programmable Logic Interface Ports 4xAⅪ64b/32 b Memory AX 64bACP Primary Interfaces Interrupts Only) 16 Interrupts 7 Series PL Equivalent| Artix-7 Artix-7 Artix-7Artix-7 Artix-7 Artix-7 Kintex-7 Kintex-7 Kintex-7 Kintex-r Logic Cells 23K 55K 55K 28K 了4K 85K 125K 275K 350K 444K Lok- Up Tables(Ts144034404060017,604620053,200 171900 218,600 277400 Fip-Flop288006880081,2003520092400106400 157200 343.800 437,200 55400 Total Block RAMI 1.8Mb 2.5Mb 3. SMb 2.1Mb 3.3Mb 4.9Mb 9.3Mb 175Mb 91Mb 26.5Mb I#36Kb Blocks)(50 72 (107 60 95 140) 25) 50o 545 755 DsP Slices 65 120 170 160 22D 400 2020 PCI Express Gen2 x4 Gen2 x4 Gen2 x4 Gen2 x8 Gen2 x8 EE.E G∈n2x8 Analog Mixed Signal(AMS)/XADC2 2x 12 bit, MSPS ADCs with up to 17 Differential Inputs Security AES & SHA 256b Decryption E Authentication for Secure Programmable Logic config Commercial 1 Speed Grades Extended 23 3 Industrial 1.-2 1.-2,-2L 1,-2.-2L E XILINX L XILINX ALL PROGRAMMABLE 开发全过程 开发流程框图 Install xilinx Tools System Design Application Hardware Design Development Vivado IPl: Configure Ps Develop RTL/IP SDK: Build Compile Fetch Sources: U-boot, Linux: Ram Disk Add /Integrate IP Application Code Generate Bitstream s Export to SDK BuildBuild Create*Create Hardware handoff U- boot Linux‖ RamDisk ATE Application System Software Code Binary (hdf). U-boot Julmage uRam Disk ATF Development Bitstream SDK/ HSI: Create FSBL Create Devicetree FSBL SDK/ Bootgen: Create Boot Image :Create PMUFW PMUFW BOOT. BIN For Zynq UltraScale+ MPSoC Booting and Running Linux designs only Target Platform E XILINX 工具 Vivado 2016.4 回x File F。13置 indow Help Q- Quick Access VIVADO E XILINX HLr Editions ALL PROGRAMMABLE Quick Start Recent Projects c H: /Workspace/0703 baochuang/pcie/pcie zcT02 / Workspace/0530 guao/zc702 Create lew Project Open Project Open Example Project project 1 H:/Workspace/0621 baochuang/project 1 Tasks pcie E: /*pcie/pcie 售國已 roject 1 Recent Checkpoi Manage IP Xilin icl store post_synth.dop h:/Workspace/0503 shannon/pro Information center post synth. dcp H:/ Workspace/0503 shannon/pr top_route design_count_11_12301630 dcp H=/Workspace/0504 shannon/12301630 prfailed project/12301 black_ box. dep Document ation and tutorial Quick iake videos Release otes Guid H: /Workspace/0503 shannon/pro top route_count_ss_20170410 dcp Tcl Consol start_Eul e a Icl command her e K XILINX 硬件平台拾建 ZC702-[H /Workspace/ 0705_guao/c702/zc702xpr)-Vivado 2016 4 N87 回 Eile Edit Flow Iools Lindow Layout liew Help 点我加速 Q-Quick Access 已的自自×争D%∑2: it layout 汉◆ avi gator ock Desiga- design 1 X Q島 Pr。ject團 an:ger 品di1 品aeie_1 Project Settings Add sources anguage Templates TF IP Catalog 日日 IP Integrator Search:Q'rynq Create Block Design 5 urces E Design画sals圖 Board Open block lesig t Generate Block Desig Simulation <g Simulation Settings Run simulation RIL Analysis Icl Console El aboration Settings F ( createproject ze702H: / Workspace/0705guao/zc702-"part xcz02021g404-1 pen卫1 borated Desi ClFO: [IP Flow 19-234] Refreshing IP repositories [LIFO: [IP- Flow 19-1704] Io user IP repositories specified anthesis AILIFO:[IP_Flow 19-2313] Loaded Vivado IP repository D: /Xilinx/Vivado/2016.4/data/iy' 费 Synthesis Settings set property board part xilinx. com: zc702: partO: 1. 2 [current project] EITER to select, ESC to cancel, Ctrl+Q for IP details Run synthe s15 createbd_design desi en_1 e create_bd_design: Time (s): cpu 00: 00: 08: elapsed=00: 00: 05. Memory (MB): peak 867 230: gain 15. 422 Implementation lementation Setti Run Implementati Type a Tel command here un E XILINX 硬件平台拾建 02-[H: /Workspace/0705__guao/zc702/zc702 xpr]-Vivado 2016.4 回_义 EditFlow Tools Mind[ Re-customizeIP 点我加速 Quick access Re乱dy ZYNQ Processing Syste (5. 5) Flow lavi gator I Documentation Presets P IP Location (f Import XPS Settings Page lavi gat Zyng block design Summary Report 4Pr。1e Nan乱ger Lyng Block Design Project sett vO Peripherals Genera Add source PS-PL Confi guration P|0 set ngs Application Processor Unit (APU SWDT Language Templates Peripheral I/o Pir Hanan 12C0 TTC M LP Catalog M Cortex-A9 ARMC怒x9 MIO Confi guration CANO System Level CAN1 d IP Integrator Contol reds Clock Confi guration UART0 MUX Snoop Contrd unt Open Block Design ⑩ R Configuration M|) DMAB Channel 512KB L2 Cache and Centro er USB0 oCM 256K日 4 Simulatie Cves ght SRAM interrupts NETO 8 Simlation Settings ENET 1 Central Comoonents interconnect M Run Simulation FLASH Memory ntedaoeg SRAMNOR Memory Interlaces RIL Analysis QUAD SPI DEvC DDR233 LPDDR2 128 Loac wM Inteconnect 0pen卫 laborated D SMG Timna Canton DMA ync Synthesis Processing System(PS) a23 0112|3 DMA Run Synthesis 82bGP Channeis Hoh Pedomamge XADC MID (EMO) cock fots AXI 32b/84b Save Open synthesized D SHA Pot Pote Ports A Implementation Implementation Setti Programmable Logic(PL) Run Implementation Open Implemented Des OK Cancel E XILINX 硬件平台拾建 y zc702-[H: /Workspace/0705- guao/zc702/zc702 xpr]-Vivado 2016.4 Eile edit卫Iq1sind: Layout wie青1e1lp 点我加速 Q Quick Access 日的朗自自X争D∑同里utgt·豢N|思 e: dy Flow Navi gator Block Desig- desi gn 1 Q园粤 ources □L 4 Project圃 anager 圳热 口De5 i gn Sour ces(1) Project settings @品e1rer( design l wrapper. v)) or Add sources E-a design 1_i-design 1 (design 1. bd)(1) Q Language Templates Eoe design 1 (design 1.v)(1) aFa processing_system70-design 1 process IP Catalog R.n fonetrainte Ⅲl processing sy stem? 0 TP Integrator Hierarchy IP Sources Libraries Compile Order ekue品sm(easl(lad R中 ZYNQ DDDR FIXED_10中 DFIXED_IO e Properties ZINgT Process ing System ve design 1 wrapper.v e Simulation Setti eral Properties RTL Anal Elaboration Settings endgroup Verilog Output written to: H: Workspace/ 0705_guao/zc702/zc702 srcs/sources 1/bd/desi gn 1/hdl/design_1v Synthesis Setting Rum synthesis import_ files-force -norecurse H: /Workspace/0705_Euao/zc702/zc702 srcs/sources_1/bd/design _1/hdl/design_1_wrapper.v Open Synthesized Des update_compile_order -fileset sources_1 update_ compile order -fileset sim_ 1 Implementation > Sett Run Implementation ype a Tcl command here 量0 pen Implemented Des Iel Console O Me:55国Lg国 ReportsDesig甲nkms E XILINX 【实例截图】
【核心代码】
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