Allwinner_F1C200s_Datasheet_V1.0.pdf

【实例简介】
全志F1c200s datasheet，适用于想要基于全志F1c200s芯片的开发设备的人员。
DAllinger Technology Revision History Revision History Revision Date Description 1.0 Apr18,2017 Initial release version F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 3 DAllinger Technology Table of Contents Table of contents Overview 2. Features .:::::::::: 2.1 CPU Architecture 2.2. Memory subsystem 2.3. System Peripheral 8·面 2. 4. Display subsystem. 5666677 2.5. Video engine 2.6. Image Subsystem 2.7. Audio Subsyste 2.8. System Peripherals.................... 8 2.9. Packa .10 3. Block Diagram......... 11 4. Pin Description 41. Pin characte 12 4.2. G PlO Multiplexing fi .:::: 14 4.3. Detailed pin description 5. Electrical characteristics 18 5.1 Absolute maxi 18 5.2. Recommended Operating Conditions.................18 5.3. DC Electrical Characteristics 18 5.4. Oscillator Electrical Characteristics..... :::.::::::· 19 5.5. Power Up/down Sequence 19 6. Pin Assignment 20 6.1. Pin Map.......... 20 6.2. Package Dimension 21 F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 4 DAllinger Technology Overview 1. Overview The F1C200s processor represents Allwinner's latest achievement in mobile applications processors. the processor targets the needs of video boombox markets The F1c200s is based on the arm9 CPu architecture with a high degree of functional integration, and supports Full Hd video playback including h. 264, H 263, MPEG 12/4 decoder Integrated audio codec and 2S/PCM interface provide end users with a good audio experience. TV-IN interface enables video input by connecting to video devices such as camera, and Tv-oUT interface enables video output by connecting to Tv devices To reduce the BOM costs, the F1C200s built-in DDRI memory, and it is packed with general-purpose peripherals such as USB OTG, UART, SPl, TWL, TP, SD/MMC, CSI etc. The F1C200s outperforms competitors in terms of its powerful performance low power consumption, and flexible scalability Applications e Video playback Audio playback ●FM F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 5 DAllinger Technology Features 2. Features 2. 1. CPU Architecture The f1c200s platform is based on arM9 CPU architecture Five-stage pipeline architecture Support 16KByte D-Cache Support 32KByte I-Cache 2.2. Memory Subsystem This section consists of internal memory and external memory Boot ROM ● SDRAM SD/MMC Interface Boot rom ●| nterna| memon On-Chip RoM boot loader Support system boot from SPl Nor/Nand Flash and SD/tF card Support system code download through USB OTG SDRAM SIP DDR1 SD/MMC Interface e External memory Support secure digital memory protocol commands(up to SD2. 0) Support secure digital i/o protocol commands(up to SDIO2 0 Support multimedia card protocol commands (up to eMMC4. 41) Support one SD(Verson10to 2.0)or MMC(version 3. 3 to eMMC4. 41) Support hardware CRC generation and error detection Support host pull-up control Support SDio interrupts in 1-bit and 4-bit modes Support SDIO suspend and resume operation Support sdio read wait Support block size of 1 to 65535 bytes Support descriptor-based internal Dma controller Internal 128 bytes FIFO for data transfer Support 3. 3V IO pad 23. System Peripheral This section includes. ● Timer INTO CCU DMA PWM Timer Three timers F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 6 DAllinger Technology Features Support watchdog reset Support audio and video synchronize counter INTC Support up to 64 interrupts Support 4-level priority Support interrupt mask Support interrupt fast forcing Support one external interrupt Support 6 Plls Control of clock generation division, distribution and gating Control of device software reset DMA Support Normal dma and dedicated DMa Support two kinds of interrupt Support hardware continuous transfer mode PWM Support two PWM outputs Support cycle mode and pulse mode e Support 24MHz maximum output frequency 2. 4. Display Subsystem This section includes · Display engine Display output Display engine Support four layers over lay, each ayer size up to 2048X2048 pixels Support multi-format input formats 10/48/ 16/32 bpp color YUV444YUV422YUV420/YUV411 Support hardware cursor Support scaling function for one layer ARGB8888/YUV444 YUV420/YUV422/YUV411 Input and output size up to 1280x720 pixels Resize ratio from 1 16X to 32X 4-tap 32-phase anti-aliasing filter in horizontal and vertical direction u Scaler supports write-back to memory function Display output LCD RGB interface, TTL interface, up to 1280x720@60fps LCD Serial RGB interface, CCIR656 interface, up to 720x576@ 60fps LCD i8080 interface with 18/16/9/8 bit, up to 800x480@ 60fps LCD Dither function, support RGB666/RGB565 interface TV CVBS output, support NTSC/PAL, with auto plug detecting 2.5. Video Engine Support H. 264 BP/MP/HP up to 1280x720@ 30fps decoding F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 7 DAllinger Technology Features Support format MPEG1 and MPEG2 up to 1280x720@30fps decoding Support format mPEG4 SP/ASP GMC and H 263 including Sorenson Spark up to 1280x 720@ 30fps decoding Support mPEG encode up to 1280x720@30fps Support JPEG encode size up to 8192x 8192 Support jpeg decode size up to 16384 x 16384 2.6. Image Subsystem This section includes ●CSl CVBS Input Support 8-bit CMOS-sensor interface Support YUV camera up to 5Mega pixel Support CCiR656 protocol for NTSC and PAl CVBS Input Sur NTSC/PAL · Support3 D comb filter Support two Tv cVbS channels: TVINo, TVIN1 2.7. Audio Subsystem Audio codec Two audio digital-to-analog(DAC) channel Stereo capless headphone drivers Up to 100dB DR Supports DAC Sample Rates from &KHz to 192KHz Support analog/ digital volume control Analog low-power loop from fm/ lime-in /microphone to headphone outputs Three audio inputs One micro phone input Stereo FM left/right input One Line-in input One audio analog-to-digital (aDC)channel 96dB SNR@A-weight Supports ADC Sample rates from 8KHz to 48KHz a Support auto Gain Control(AGC 2.8. System Peripherals This section includes: ●USB2.00TG ● KEYADO TP Digital Audio Interface UART ●sPl TWI R RSB F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 8 Allwinner Technology Features ●oWA USB 20 OTG Support AMbA AHB Slave mode Support the Host Negotiation Protocol(HNP)and the Sessi st Protocol (SRP) Support the UTMI+ Level 3 interface. The 8-bit bidirectional data buses are used 64-Byte endpoint o for Control Transfer( Support high-Bandwidth Isochronous Interrupt transfers Automated splitting/combining of packets for Bulk transfers Support point-to-point and point-to-multipoint transfer in both host and peripheral mode Include automatic ping capabilities Soft connect/disconnect function Perform all transaction scheduling in hardware Power Optimization and Power Management capabilities Include interface to an external dedicated Central dMa controller. Data is transferred through special bus for saving AHb bus bandwidth Support industry-standard single port SRAM for USB Configurable Data FIFO. The size is 2048 byte with 32-bit word width. The ram can be used by other modules when USB OTG disable KEYADO 6-bit resolution Support hold key and general key Support single key and continuous key Sample rate up to 250Hz 12-bit SAR type analog-to-digital converter 4-wire I/F ●Dua| Touch detect Touch-pressure measurement Sampling frequency 2MHz Single-Ended conversion of touch screen inputs and ratio metric conversion of touch screen inputs TACQ up to 262ms Median and averaging filter to reduce noise Pen down detection, with programmable sensitivity Support x, Y change function Digital Audio Interface 12S or PCM configured by software Master/ Slave mode operation configured by software 12S Audio data sample rate from 8KHz to 192KHz 12S Data format for standard 12S, Left Justified and Right Justified PCM supports linear sample 8-bits or 16-bits),8-bits u-law and A-law commanded sample UART Three uart controllers Compatible with industry-standard 16550 UARTs Support iRDA version 1.0 SIR protocol with maximum baud rate to 115200bps for all UARTs Support for word length from 5 to 8 bits, an optional parity bit, and 1, 1.5 or 2 stop bits Programmable parityleven, odd and no parity 32-Bytes Transmit and receive data FIFOs Support DMA controller interface Software/ hardware Flow Control Interrupt support for FIFOs, Status Change SPI Two SPi controllers F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 9 DAllinger Technology Features Full-duplex synchronous serial interface Master/ Slave configurable 8-bit wide by 64-entry Fifo for both transmit and receive data Polarity and phase of the chip select (SPl Ss)and SPl Clock(sPl SClk ) are configurable TWI ● Three twi contro|ers Software-programmable for Slave or Master Support repeated start signal Multi-master systems supported Allow 10-bit addressing with twi bus e Performs arbitration and clock synchronization Own address and general call address detection Interrupt on address detection Support speeds up to 400kbitss('fast mode') Allow operation from a wide range of input clock frequencies R Full physical layer implementation Support CIR for remote control 64x8bits fifo for data buffer Programmable fiFo thresholds RSB Support speed up to 20MHz With ultra low power Support push-pull bus · Support host mode Support programmable output delay of CD signal Support parity check for address and data transmission Support multi-devices OWA C-60958 transmitter functionality Support S/PDIF Interface Support channel status insertion for the transmitter Support Parity generation on the transmitter ne32×24 bits f「(X) for audio data transfer Programmable FIFo thresholds Interrupt and DMA support 2.9. Package ·QFN88,10mmx10mm F1C200s Datasheet(Revision 1.01 Copyright @2017 Allwinner Technology Co, Ltd. All Rights Reserved Page 10 【实例截图】
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