Nexys4 DDR开发板官方说明文档

【实例简介】
Nexys4 DDR的官方说明文档，提供开发板的介绍及各模块的说明等。
Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT The nexys4 ddR is an incremental update to the nexys 4 board the major improvement is the replacement of the 16 MiB Cellular RAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a dDR2 controller and is backwards compatible with the asynchronous SRaM interface of thecellularram,withcertainlimitationsSeethenexys4Ddrpageatwww.digilentinc.comforupdates Furthermore to accommodate the new memory the pin- out of the fpga banks has changed as well. the constraints file of existing projects will need to be updated The audio output(AUD PWM)needs to be driven open-drain as opposed to push-pull on the Nexys 4 The nexys4 ddR board can receive power from the digilent USB-JTAG port J6)or from an external power supply Jumper JP3 (near the power jack determines which source is used. All Nexys4 dDR power supplies can be turned on and off by a single logic-level power switch (SW16). a power-good LED (LD22), driven by the "power good" output of the adp2118 supply, indicates that the supplies are turned on and operating normally An overview of the Nexys4 ddR power circuit is shown in Figure 2. 唧弯 Figure 2. Nexys4 DDR power circuit. The USB port can deliver enough power for the vast majority of designs. Our out-of-box demo draws 400mA of current from the 5V input rail. a few demanding applications including any that drive multiple peripheral boards might require more power than the USB port can provide. Also, some applications may need to run without being connected to a PCs USB port. In these instances, an external power supply or battery pack can be used An external power supply can be used by plugging into to the power jack (jP3 )and setting jumper 13 to "wall The supply must use a coax, center-positive 21mm internal-diameter plug, and deliver 4.5VDC to 5.VDC and at tht Digilent, Inc. All rights oduct and company names mentioned may be trademarks of their respective owners Page 3 of 29 Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT least 1A of current(i.e, at least 5W of power). Many suitable supplies can be purchased from digilent, through Digi-Key, or other catalog vendors An external battery pack can be used by connecting the batterys positive terminal to the center pin of JP3 and the negative terminal to the pin labeled J12, directly below JP3. Since the main regulator on the nexys4 ddr cannot accommodate input voltages over 55VDC, an external battery pack must be limited to 5.5VDC. The minimum voltage of the battery pack depends on the application if the USB Host function(J5)is used at least 4.6V needs to be provided. In other cases, the minimum voltage is 3.6V Voltage regulator circuits from analog devices create the required 3. 3V, 1.8V, and 1.0V supplies from the main power input Table 1 provides additional information Typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs Supply Circuits Device Current(max/typical) FPGA 1/0, USB ports, Clocks 3.3V RAM 1/O, Ethernet, SD slot C17:ADP2118 3A/0.1to15A Sensors. Flash 1.0V FPGA Core C22:ADP2118 3A/0.2to1.3A DDR2, FPGA Auxiliary and 1.8V C23:ADP2138 RAM 08A/0.5A Table 1. Nexys4 DDR power supplies Figure 2. Applying power outside of the specs outlined in this document is not covered by warranty f thf * o.% The nexys 4 DDR features overcurrent and overvoltage protection on the input power rail. a 3.5A fuse(R287)and a 5V Zener diode (d16 )provide a non- resettable protection for other on-board integrated circuits, as display In happens, either or both might get permanently damaged. the damaged parts are not user-replaceable After power-on, the artix-7 FPGA must be configured (or programmed) before it can perform any functions you can configure the fpga in one of four ways 1. A PC can use the Digilent USB-JTAG circuitry(portJ6, labeled"PRoG") to program the FPga any time the power is on 2. A file stored in the nonvolatile serial sPl)flash device can be transferred to the fpga using the spi port 3. A programming file can be transferred to the fpga from a micro SD card 4. A programming file can be transferred from a USb memory stick attached to the USB hId port tht Digilent, Inc. All rights oduct and company names mentioned may be trademarks of their respective owners Page 4 of 29 Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT Figure 3. Nexys4 DDR configuration options Figure 3 shows the different options available for configuring the fPgA. an on-board"mode"jumper(jp1)and media selection jumper (JP2 )select between the programming modes The fPga configuration data is stored in files called bitstreams that have the bit file extension. The Ise or vivado software from Xilinx can create bitstreams from Vhdl, verilog, or schematic- based source files in the ise toolset EDK is used for Micro Blaze TM embedded processor-based designs Bitstreams are stored in SRAM-based memory cells within the FPGa. this data defines the FPGa's logic functions and circuit connections, and it remains valid until it is erased by removing board power by pressing the reset button attached to the Prog input, or by writing a new configuration file using the jTAG port An Artix -7 100T bitstream is typically 30, 606, 304 bits and can take a long time to transfer. the time it takes to program the Nexys 4 can be decreased by compressing the bitstream before programming and then allowing the FPGA to decompress the bitstream itself during configuration Depending on design complexity, compression ratios of 10 can be achieved. Bitstream compression can be enabled within the Xilinx tools(IsE or Vivado)to occur during generation For instructions on how to do this, consult the Xilinx documentation for the toolset being used After being successfully programmed, the FPga will cause the"DoNE LED to illuminate. Pressing the"PROG button at any time will reset the configuration memory in the FPGA. after being reset, the Fpga will immediately Attempt to reprogram itself from whatever method has been selected by the programming mode jumpers The following sections provide greater detail about programming the nexys 4 ddr using the different methods available The Xilinx tools ty pically communicate with FP GAs using the Test Access port and Boundary-Scan Architecture, commonly referred to as jTAG. during JTAG programming a bit file is transferred from the pc to the fpga using the onboard Digilent USB-JTAG circuitry(port J6)or an external JTAG programmer such as the Digilent JTAG-HS2, attached to port J10. You can perform jTAG programming any time after the nexys 4 ddr has been powered on, regardless of what the mode jumper(jPl)is set to. If the fpga is already configured then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG tht Digilent, Inc. All rights oduct and company names mentioned may be trademarks of their respective owners Page 5 of 29 Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT setting (seen in Figure 3 is useful to prevent the fpga from being configured from any other bitstream source until a JTAG programming occurs Programming the nexys 4 dDR with an uncompressed bitstream using the on-board USB-JtAG circuitry usually takes around five seconds TAG programming can be done using the hardware server in vivado or the imPact tool includedwithIseandthelAbtoolsversionofvivado.thedemonstrationprojectavailableatwww.digilentinc.com gives an in-depth tutorial on how to program your board Since the fPga on the Nexys4 DDR is volatile, it relies on the Quad-SPl flash memory to store the configuration between power cycles. This configuration mode is called Master SPl. The blank fPga takes the role of master and reads the configuration file out of the flash device upon power-up To that effect, a configuration file needs to be downloaded first to the flash When programming a nonvolatile flash device, a bitstream file is transferred to the flash in a two-step process. First, the fPga is programmed with a circuit that can program flash devices, and then data is transferred to the flash device via the fpga circuit ( this complexity is hidden from the user by the xilinx tools). This is called indirect programming After the flash device has been programmed it can automatically configure the FPga at a subsequent power-on or reset event as determined by the mode jumper setting(see Figure 3). Programming files stored in the flash device will remain until they are overwritten regardless of power- cycle events Programming the flash can take as long as four to five minutes which is mostly due to the lengthy erase process inherent to the memory technology. once written however, fpga configuration can be very fast -less than a second Bitstream compression, SPI bus width and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed The Nexys4 DDR supports xl, 2, and x4 bus widths and data rates of up to 50 MHz for Quad-SPI programming Quad-SPI programming can be done using the imPact tool included with ise or the lab tools version of vivado You can program the fpga from a pen drive attached to the USB Host port (J5) or a microsd card inserted into J1 y doing the following 1. Format the storage device Pen drive or microSD card)with a FAT32 file system 2. Place a single bit configuration file in the root directory of the storage device 3. Attach the storage device to the nexys4 DDR 4. Set the JP1 Programming Mode jumper on the Nexys4 ddr to"USB/SD 5. Select the desired storage device using JP2 6. Push the prog button or power -cycle the nexys4 ddr The fpga will automatically configure with the bit file on the selected storage device. any bit files that are not built for the proper Artix 7 device will be rejected by the Pga The auxiliary Function Status, or"BUSY"LED, gives visual feed back on the state of the configuration process when the fpga is not yet programmed When steadily lit, the auxiliary microcontroller is either booting up or currently reading the configuration medium(microSD or pen drive)and downloading a bitstream to the fPga a slow pulse means the microcontroller is waiting for a configuration medium to be plugged in pyright Digilent, Inc. All rights her product and company names mentioned may be trademarks of thcir respective owne Page 6 of 29 Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT In case of an error during configuration, the led will blink rapidly When the fpga has been successfully configured, the behavior of the led is application-specific. For example, if a USB keyboard is plugged in, a rapid blink will signal the receipt of an hid input report from the keyboard The nexys4 ddR board contains two external memories: a 1Gib(128MiB)DDR2 SDRAM and a 128Mib(16MiB non-volatile serial Flash device. the ddr2 modules are integrated on-board and connect to the fpga using the industry standard interface. The serial Flash is on a dedicated quad- mode(x4)spl bus the connections and pin assignments between the fPga and external memories are shown below The Nexys4 DDR includes one Micron MT47H64M16HR-25 H DDR2 memory component, creating a single rank, 16- bit wide interface. It is routed to a 1. 8V-powered Hr (High Range) fPga bank with 50 ohm controlled single-ended trace impedance 50 ohm internal terminations in the fpga are used to match the trace characteristics. similarly on the memory side on-die terminations (odT)are used for impedance matching For proper operation of the memory a memory controller and physical layer(Phy) interface needs to be included in the fpga design there are two recommended ways to do that, which are outlined below and differ in complexity and design flexibility The straightforward way is to use the Digilent -provided DDR-to-SRAM adapter module which instantiates the memory controller and uses an asynchronous SRAM bus for interfacing with user logic. This module provides backward compatibility with projects written for older Nexys-line boards featuring a cellularRAM instead of ddr2 It trades memory bandwidth for simplicity More advanced users or those who wish to learn more about ddR SDRAM technology may want to use the xilinx 7-series memory interface solutions core generated by the mig ( memory Interface generator) Wizard. depending on the tool used (ISE, EDK or Vivado), the mig wizard can generate a native fIFo-style or an AXl4 interface to connect to user logic. this workflow allows the customization of several ddr parameters optimized for the particular application Table 2 below lists the mig wizard settings optimized for the nexys4 DDR Setting Value Memory type DDR2 SDRAM Max clock period 3000ps(667Mbps data rate) Recommended clock period (for easy clock generation) 3077ps(650Mbps data rate) Memory part IMT47H64M16HR-25E Data width Data mask Enabled Chip Select pin Enabled Rtt(nominal)-On-die termination 50ohms nternal∨ref Enabled Internal termination impedance 50ohms Table 2. DDR2 settings for the Nexys4 DDR Although the FPGA, memory IC, and the board itself are capable of the maximum data rate of 667 Mbps, the limitations in the clock generation primitives restrict the clock frequencies that can be generated from the 100 MHz system clock. Thus, for simplicity the next highest data rate of 650Mbps is recommended. pyright Digilent, Inc. All rights ler product and company na entioned may be trademarks of thcir respective ownet Page 7 of 29 Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT The mig wizard will require the fixed pin -out of the memory signals to be entered and validated before generating the IP core For your convenience, an importable UCF file is provided on the Digilent website to speed up the process For more details on the xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions User Guide(ug586) FPGA configuration files can be written to the Quad-SPl Flash (Spansion part number $25FL128S ), and mode settings are available to cause the fpga to automatically read a configuration from this device at power on. an Artix-7 100T configuration file requires just less than four mib (mebibyte) of memory leaving about 77%of the flash device available for user data. Or, if the fPga is getting configured from another source the whole memory can be used for custom data The contents of the memory can be manipulated by issuing certain commands on the spi bus. The implementation of this protocol is outside the scope of this document. all signals in the Spl bus except scK are general-purpose user l0 pins after FPGa configuration SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGa primitive called STARTUPE2 NOTE: Refer to the manufacturers data sheets and Xilinx user guides for more information Figure 4. Nexys4 DDR SPl flash pin-out. The nexys 4 ddr board includes an SMSc 10/100 Ethernet Phy ( SMSc part number lan8720A)paired with an Rj- 45 Ethernet jack with integrated magnetics. The SMSC PHY uses the RMll interface and supports 10/100 Mb/s Figure 5 illustrates the pin connections between the artix-7 and the ethernet PhY. At power-on reset, the Phy is set to the following defaults RMll mode interface Auto-negotiation enabled advertising all 10 /100 mode capable PHY address=00001 http://www.xilinx.com/support/documentation/ipdocumentation/mig7series/v21/ug5867seRiesMis.pdF nhttp:/www.spansion.com/ssupport/dAtasheets/s25fl128s256s00.pdf http://www.xilinx.com/support/documentation/userguides/ug4707seRiesConfigpdf pyright Digilent, Inc. All rights reserve her product and company names mentioned may be trademarks of thcir respective owners Page 8 of 29 Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT Two on-board LEDs(LD23= LED2, LD24=LED1)connected to the phy provide link status and data activity feedback, see the phy datasheet for details EDK-based designs can access the Phy using either the axi ethernetlite(aXi ethernetlite)IP core or the Ixi ethernet(Tri Mode Ethernet mAc)IP core. a mii to_ rmii core(Ethernet phy Mll to reduced mil)needs to be inserted to convert the mac interface from mil to rmll. also a 50 Mhz clock needs to be generated for the mii to rmii core and the clkin pin of the external Phy. to account for skew introduced by the mii to rmii core generate each clock individually, with the external PhY clock having a 45 degree phase shift relative to the mii to rmii Ref clk. an edk demonstration project that properly uses the ethernet phy can be found on the Nexys4ddrproductpageatwww.digilentinc.com ise designs can use the IP Core generator wizard to create an ethernet mac controller ip core NoTE: Refer to the lan8720a data sheet for further information Figure 5 Pin connections between the Artix-7 and the ethernet PHy. The nexys4 ddR board includes a sing le 100 Mhz crystal oscillator connected to pin e3(E3 is a mrcc input on bank 35). The input clock can drive MMCMs or Plls to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design Some rules restrict which MMCMs and Plls may be driven by the 100 MHz input clock For a full description of these rules and of the capabilities of the artix-7 clocking resources, refer to the 7 Series fPgas clocking resources User guide"available from Xilinx Xilinx offers the Clocking Wizard ip core to help users generate the different clocks required for a specific design This wizard will properly instantiate the needed MMCMs and plls based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these http://ww1.microchipcom/downloads/en/deviceDoc/8720a.pdf cht digilent Inc. All reserve her product and company names mentioned may be trademarks of thcir respective owne Page 9 of Nexys4 DDRTM FPGA Board Reference Manual ADIGILENT clocking resources that can be inserted into the user's design the clocking wizard can be accessed from within the Project Navigator or Core Generator tools The Nexys4 ddR includes an ftdi FT2232HQ USB-UaRT bridge attached to connector J6) that allows you use pc applications to communicate with the board using standard Windows COM port commands. Free USB-COM port driversavailablefromwww.ftdichip.comunderthevirtualComportorVcpheadingconvertUsbpacketsto UART/serial port data Serial port data is exchanged with the FPga using a two-wire serial port(TXD/RXD) and optional hardware flow control (RTS/CTS). After the drivers are installed, i/o commands can be used from the pc directed to the Com port to produce serial data traffic on the C4 and d4 PGa pins Two on-board status lEds provide visual feedback on traffic flowing through the port: the transmit lEd (LD20 )and the receive lEd (LD19) signal names that imply direction are from the point-of-view of the dte (Data Terminal Equipment), in this case the pC The Ft2232HQ is also used as the controller for the Digilent USB-JTAG circuitry but the USB-UART and USB-JTAG functions behave entirely independent of one another programmers interested in using the uart functiona lity of the ft2232 within their design do not need to worry about the jtag circuitry interfering with the UART data transfers and vice-versa the com bination of these two features into a single device allows the nexys4 ddr to be programmed, communicated with via UART, and powered from a computer attached with a single micro USB cable The connections between the FT2232HQ and the artix-7 are shown in Figure 6. Figure 6. Nexys4 DDR FT2232HQ connections The auxiliary Function microcontroller(Microchip PIC24FJ128 )provides the nexys4 DDR with USB Embedded HID host capability. After power-up the microcontroller is in configuration mode either downloading a bitstream to the FPGa, or waiting to be programmed from other sources. Once the FPga is programmed, the microcontroller switches to application mode, which is USB HID Host in this case. Firmware in the microcontroller can drive a mouse or a keyboard attached to the type a usb connector at 5 labeled"USB Host. Hub support is not currently available so only a single mouse or a single keyboard can be used. only keyboards and mice supporting the boot HID interface are supported. the plC24 drives several signals into the fPga-two are used to implement a standard PS/ 2 interface for communication with a mouse or keyboard and the others are connected to the fPga's two-wire serial programming port so the fpga can be programmed from a file stored on a uSb pen drive or microsd card tht Digilent, Inc. All rights oduct and company names mentioned may be trademarks of their respective owners Page 10 of 29 【实例截图】
【核心代码】