verilog_IEEE官方标准手册-2005_IEEE_P1364

【实例简介】
The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timi
The clear directive from the users for these three task forces was to start by solving some of the following problems Consolidate existing IeeE Std 1364-1995 Verilog generate statement Multi-dimensional arrays Enhanced Verilog file i/o Re-entrant tasks Standardize Verilog configurations Enhance timing representation Enhance the vpi routines Achievements Over a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrm The three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of con solidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for the Behavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance- ments that were requested (including the ones stated above) Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configu ration management and has been added to facilitate both the sharing of verilog designs between designers and/or design groups and the repeatability of the exact contents of a given simulation session Clause 15 Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more full how timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format (SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001 Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioral and other areas of the lrm. minimum work has been done on the pli routines and most of the work has been concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu- lation control, work area access, error handling, assign/deassign and support for array of instances, generate and file 1/0 Work on this standard would not have been possible without funding from the cas society of the ieee and Open verilog International The IEEE Std 1364-2001 Verilog standards Group organization Many individuals from many different organizations participated directly or indirectly in the standardization process. The main body of the Ieee Std 1364-2001 working group is located in the United States, with a subgroup in Japan (EIAJ/1364HDL) The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to be approved by this group to be implemented the three task forces focused on their specific areas and their recommendations were eventually voted on by the Ieee Std 1364-2001 working group 【实例截图】
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