USB4 1.0 20190829 Specification.pdf

【实例简介】

USB4 1.0 20190829 Spec

【核心代码】

Contents
1 Introduction........................................................................................................................................................ 1
1.1 Scope of the Document ........................................................................................................................ 1
1.2 USB Product Compliance..................................................................................................................... 1
1.3 Document Organization....................................................................................................................... 1
1.4 Design Goals............................................................................................................................................ 1
1.5 Related Documents ............................................................................................................................... 1
1.6 Conventions ............................................................................................................................................ 2
1.6.1 Precedence ............................................................................................................................... 2
1.6.2 Keywords .................................................................................................................................. 2
1.6.2.1 Informative ................................................................................................................................ 2
1.6.2.2 May ................................................................................................................................................ 2
1.6.2.3 N/A ................................................................................................................................................ 2
1.6.2.4 Normative................................................................................................................................... 2
1.6.2.5 Optional ....................................................................................................................................... 2
1.6.2.6 Reserved...................................................................................................................................... 2
1.6.2.7 Shall............................................................................................................................................... 2
1.6.2.8 Should........................................................................................................................................... 3
1.6.3 Capitalization .......................................................................................................................... 3
1.6.4 Italic Text ................................................................................................................................. 3
1.6.5 Numbering ............................................................................................................................... 3
1.6.6 Bit, Byte, DW, and Symbol Conventions .......................................................................... 3
1.6.7 Implementation Notes .......................................................................................................... 3
1.6.8 Connection Manager Notes ................................................................................................. 3
1.6.9 Pseudocode .............................................................................................................................. 3
1.6.10 CRC Algorithms ....................................................................................................................... 4
1.6.11 FourCC ....................................................................................................................................... 4
1.7 Reserved Values and Fields................................................................................................................ 4
1.8 Terms and Abbreviations.................................................................................................................... 5
2 Architectural Overview .................................................................................................................................10
2.1 USB4 System Description..................................................................................................................10
2.1.1 Architectural Constructs....................................................................................................12
2.1.1.1 Routers.......................................................................................................................................12
2.1.1.2 Adapters ....................................................................................................................................12
2.1.1.3 USB4 Ports and Links ..........................................................................................................12
2.1.1.4 USB4 Devices...........................................................................................................................13
2.1.1.5 USB4 Host.................................................................................................................................14
2.1.1.6 Re-timers...................................................................................................................................15
2.1.1.7 Connection Manager ............................................................................................................15
2.1.2 USB4 Mechanical ..................................................................................................................15
2.1.3 USB4 Power ...........................................................................................................................15
2.1.4 USB4 System Configuration ..............................................................................................15
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2.1.5 Thunderbolt™ 3 (TBT3) Compatibility Support .........................................................15
2.1.6 USB Type-C Alternate Mode Compatibility Support..................................................15
2.2 USB4 Fabric Architecture .................................................................................................................15
2.2.1 USB4 Functional Stack........................................................................................................16
2.2.1.1 Electrical Layer.......................................................................................................................16
2.2.1.2 Logical Layer ...........................................................................................................................17
2.2.1.3 Transport Layer .....................................................................................................................17
2.2.1.4 Configuration Layer .............................................................................................................17
2.2.1.5 Protocol Adapter Layer ......................................................................................................17
2.2.2 USB4 Fabric Topology ........................................................................................................17
2.2.3 Paths ........................................................................................................................................19
2.2.4 Communication Constructs ...............................................................................................20
2.2.4.1 USB4 Link..................................................................................................................................20
2.2.4.2 Sideband Channel..................................................................................................................21
2.2.5 USB4 Host-to-Host Communications .............................................................................22
2.2.6 Programming Model............................................................................................................22
2.2.6.1 Connection Manager ............................................................................................................22
2.2.6.2 Configuration Spaces ...........................................................................................................23
2.2.6.3 Operations ................................................................................................................................23
2.2.7 Time Synchronization.........................................................................................................23
2.2.8 USB4 Fabric Data Integrity ...............................................................................................23
2.2.9 Global Life of a Router ........................................................................................................24
2.2.10 Protocol Tunneling ..............................................................................................................24
2.2.10.1 USB3 Tunneling......................................................................................................................25
2.2.10.2 Display Tunneling .................................................................................................................29
2.2.10.3 PCIe Tunneling .......................................................................................................................32
2.2.10.4 Host Interface Adapter........................................................................................................36
3 Electrical Layer ................................................................................................................................................39
3.1 Sideband Channel Electrical Specifications ................................................................................39
3.2 USB4 Ecosystem...................................................................................................................................40
3.2.1 Insertion-Loss Considerations (Informative) .............................................................40
3.2.2 Coded Bit-Error-Ratio Considerations (Informative)...............................................41
3.3 USB4 Electrical Compliance Methodology ...................................................................................41
3.3.1 System Compliance Test Point Definitions ..................................................................41
3.3.2 AC Coupling Capacitors ......................................................................................................42
3.3.3 Reference Clock-and-Data-Recovery (CDR) Function ..............................................43
3.3.4 Reference Equalization Function ....................................................................................43
3.3.4.1 Reference CTLE......................................................................................................................44
3.3.4.2 Reference DFE ........................................................................................................................46
3.3.5 Time Domain Measurements ............................................................................................46
3.3.6 Compliance Boards ..............................................................................................................46
3.3.6.1 Compliance Plug Test Board ............................................................................................46
3.3.6.2 Compliance Receptacle Test Board...............................................................................46
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3.4 Router Assembly Transmitter Compliance .................................................................................46
3.4.1 Transmitter Specifications Applied for All Speeds ....................................................46
3.4.1.1 Transmitter Frequency Variations during Link Training ...................................48
3.4.1.2 Transmitter Differential Return Loss...........................................................................49
3.4.1.3 Transmitter Common Mode Return Loss ...................................................................50
3.4.1.4 Transmit Equalization.........................................................................................................51
3.4.2 Transmitter Compliance Specifications for Gen 2 .....................................................53
3.4.3 Transmitter Compliance Specifications for Gen 3 Interconnects .........................55
3.5 Router Assembly Receiver Compliance ........................................................................................57
3.5.1 Receiver Specifications Applied for All Speeds ..........................................................57
3.5.1.1 Receiver Differential Return Loss..................................................................................57
3.5.1.2 Receiver Common Mode Return Loss ..........................................................................58
3.5.2 Receiver Uncoded BER Tolerance Testing ...................................................................59
3.5.3 Receiver Multi Error-Bursts Testing..............................................................................61
3.6 Captive Device Compliance ..............................................................................................................62
3.6.1 Captive Device Compliance Test Setup .........................................................................62
3.6.2 Captive Device Transmitter Specifications ..................................................................63
3.6.2.1 Conducted Energy in Wireless Bands ..........................................................................63
3.6.2.2 Transmitter Specifications................................................................................................64
3.6.2.3 Transmitter Differential Return Loss...........................................................................67
3.6.2.4 Transmitter Common Mode Return Loss ...................................................................67
3.6.2.5 Transmit Equalization.........................................................................................................67
3.6.3 Captive Device Receiver Specifications .........................................................................67
3.6.3.1 Receiver Specifications Applied for All Speeds........................................................67
3.6.3.2 Receiver Differential Return Loss..................................................................................68
3.6.3.3 Receiver Common Mode Return Loss ..........................................................................68
3.6.4 Captive Device Receiver Uncoded BER Tolerance Testing......................................68
3.6.5 Captive Device Receiver Multi Error-Bursts Testing ................................................69
3.7 Low Frequency Periodic Signaling (LFPS)...................................................................................70
3.7.1 LFPS Signal Definition ........................................................................................................71
3.8 Receiver Lane Margining (Testability) .........................................................................................71
3.8.1 Background ............................................................................................................................71
3.8.1.1 Software Margining Mode .................................................................................................72
3.8.1.2 Hardware Margining Mode...............................................................................................72
3.8.2 Receiver Voltage Margining and Timing Margining Requirements ......................73
3.8.3 Receiver Parameter Access ...............................................................................................75
4 Logical Layer ....................................................................................................................................................76
4.1 Sideband Channel ................................................................................................................................76
4.1.1 Transactions ..........................................................................................................................77
4.1.1.1 Symbols......................................................................................................................................77
4.1.1.2 Transactions ............................................................................................................................77
4.1.1.3 SB Register Space ..................................................................................................................85
4.1.2 Lane Initialization................................................................................................................93
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4.1.2.1 Phase 1 – Determination of Initial Conditions .........................................................94
4.1.2.2 Phase 2 – Router Detection...............................................................................................96
4.1.2.3 Phase 3 – Determination of USB4 Port Characteristics........................................96
4.1.2.4 Phase 4 – Lane Parameters Synchronization and Transmit Start ...................97
4.1.2.5 Phase 5 – Link Equalization..............................................................................................97
4.2 Logical Layer State Machine ......................................................................................................... 100
4.2.1 Lane Adapter State Machine .......................................................................................... 100
4.2.1.1 Disabled..................................................................................................................................101
4.2.1.2 CLd............................................................................................................................................101
4.2.1.3 Training ..................................................................................................................................102
4.2.1.4 CL0............................................................................................................................................109
4.2.1.5 Lane Bonding .......................................................................................................................110
4.2.1.6 Low Power (CL0s, CL1, and CL2)................................................................................111
4.2.2 USB4 Link Transitions ..................................................................................................... 127
4.2.2.1 Transition from One Single-Lane Link to Two Single-Lane Links ................127
4.2.2.2 Transition from Two Single-Lane Links to Dual-Lane Link ............................127
4.2.2.3 Transition from Dual-Lane Link to Two Single-Lane Links ............................129
4.2.2.4 Transition from Two Single-Lane Links to One Single-Lane Link................129
4.2.3 Logical Layer Link State.................................................................................................. 129
4.3 USB4 Link Encoding ........................................................................................................................ 129
4.3.1 Lane Distribution .............................................................................................................. 131
4.3.2 Symbol Encoding ............................................................................................................... 132
4.3.2.1 Symbol Encoding of Transport Layer Bytes...........................................................132
4.3.3 Ordered Sets ....................................................................................................................... 133
4.3.4 Bit Swap ............................................................................................................................... 134
4.3.4.1 Sync Bits .................................................................................................................................134
4.3.4.2 Data Symbol Payload........................................................................................................134
4.3.4.3 Ordered Set Payload .........................................................................................................135
4.3.5 Scrambling .......................................................................................................................... 136
4.3.6 RS-FEC .................................................................................................................................. 137
4.3.6.1 RS-FEC Activation and Deactivation..........................................................................139
4.3.6.2 Pre-coding .............................................................................................................................140
4.4 USB4 Link Operation ....................................................................................................................... 140
4.4.1 Start of Data........................................................................................................................ 140
4.4.2 Error Cases and Recovery .............................................................................................. 140
4.4.3 Clock Compensation and SKIP ...................................................................................... 142
4.4.4 Dual-Lane Skew ................................................................................................................. 142
4.4.5 Disconnect........................................................................................................................... 143
4.4.5.1 Upstream Facing Port Disconnect ..............................................................................143
4.4.5.2 Downstream Port Disconnect.......................................................................................144
4.4.6 Lane Adapter Disable and Enable ................................................................................ 146
4.4.6.1 Disabled Adapter is the Upstream Adapter............................................................146
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4.4.6.2 Disabled Adapter is not the Upstream Adapter....................................................147
4.4.7 Time Sync Notification Ordered Set (TSNOS) .......................................................... 149
4.5 Sleep and Wake ................................................................................................................................. 150
4.5.1 Entry to Sleep..................................................................................................................... 150
4.5.2 Behavior in Sleep State ................................................................................................... 151
4.5.3 Wake Events ....................................................................................................................... 152
4.5.4 Exit from Sleep................................................................................................................... 152
4.6 Timing Parameters .......................................................................................................................... 153
5 Transport Layer............................................................................................................................................ 156
5.1 Transport Layer Packets ................................................................................................................ 156
5.1.1 Bit/Byte Conventions ...................................................................................................... 156
5.1.2 Format.................................................................................................................................. 156
5.1.2.1 Header.....................................................................................................................................157
5.1.2.2 Payload Padding .................................................................................................................158
5.1.2.3 Error Correction Code (ECC).........................................................................................158
5.1.3 Transport Layer Packets................................................................................................. 158
5.1.3.1 Tunneled Packets ...............................................................................................................158
5.1.3.2 Control Packets ...................................................................................................................159
5.1.3.3 Link Management Packets..............................................................................................159
5.1.4 Effect of Link State on Transport Layer Packets ..................................................... 162
5.1.5 Minimum Headers Gap .................................................................................................... 162
5.2 Routing ................................................................................................................................................ 163
5.2.1 Adapter Numbering Rules .............................................................................................. 163
5.2.2 HopID Rules ........................................................................................................................ 164
5.2.3 Routing Tables ................................................................................................................... 165
5.2.4 Routing Rules ..................................................................................................................... 165
5.2.4.1 Control Packets ...................................................................................................................165
5.2.4.2 Link Management Packets..............................................................................................165
5.2.4.3 Tunneled Packets ...............................................................................................................166
5.2.4.4 Routing Example.................................................................................................................166
5.2.5 Connectivity Rules ............................................................................................................ 167
5.3 Quality of Service (QOS)................................................................................................................. 169
5.3.1 Packet Ordering................................................................................................................. 169
5.3.2 Flow Control ....................................................................................................................... 169
5.3.2.1 Ingress Adapter...................................................................................................................169
5.3.2.2 Egress Adapter ....................................................................................................................174
5.3.2.3 Credit Counter Synchronization..................................................................................176
5.3.3 Bandwidth Arbitration and Priority ........................................................................... 177
5.3.3.1 Scheduling .............................................................................................................................177
5.4 Path Tear-down ................................................................................................................................ 178
5.4.1 Egress Adapter................................................................................................................... 179
5.4.2 Ingress Adapter ................................................................................................................. 179
5.5 Timing Parameters .......................................................................................................................... 179
6 Configuration Layer..................................................................................................................................... 181
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6.1 Domain Topology ............................................................................................................................. 181
6.2 Router Addressing ........................................................................................................................... 181
6.3 Router States ..................................................................................................................................... 183
6.3.1 Uninitialized Unplugged State ...................................................................................... 183
6.3.2 Uninitialized Plugged State ............................................................................................ 183
6.3.3 Sleep State........................................................................................................................... 184
6.3.4 Enumerated State.............................................................................................................. 184
6.4 Control Packet Protocol ................................................................................................................. 184
6.4.1 Control Adapter ................................................................................................................. 184
6.4.2 Control Packets.................................................................................................................. 184
6.4.2.1 Bit/Byte Conventions .......................................................................................................184
6.4.2.2 Format.....................................................................................................................................184
6.4.2.3 Read Request........................................................................................................................186
6.4.2.4 Read Response.....................................................................................................................187
6.4.2.5 Write Request......................................................................................................................188
6.4.2.6 Write Response ...................................................................................................................189
6.4.2.7 Notification Packet ............................................................................................................190
6.4.2.8 Notification Acknowledgement Packet ....................................................................191
6.4.2.9 Hot Plug Event Packet......................................................................................................192
6.4.2.10 Inter-Domain Request......................................................................................................193
6.4.2.11 Inter-Domain Response...................................................................................................194
6.4.3 Control Packet Routing ................................................................................................... 195
6.4.3.1 Upstream-Bound Packets ...............................................................................................195
6.4.3.2 Downstream-Bound Packets.........................................................................................195
6.4.3.3 Processing of Read and Write Requests...................................................................197
6.4.4 Control Packet Reliability............................................................................................... 198
6.5 Notification Events .......................................................................................................................... 199
6.6 Notification Acknowledgement.................................................................................................... 199
6.7 Router Enumeration ........................................................................................................................ 200
6.8 Hot Plug and Hot Unplug Events ................................................................................................. 201
6.8.1 Router Hot Plug ................................................................................................................. 202
6.8.1.1 Enumerated Routers.........................................................................................................202
6.8.1.2 Uninitialized Routers........................................................................................................202
6.8.1.3 Hot Plugged Router ...........................................................................................................202
6.8.2 Router Hot Unplug ............................................................................................................ 202
6.8.2.1 Hot Unplug on the Upstream Facing Port................................................................202
6.8.2.2 Hot Unplug on a Downstream Facing Port..............................................................203
6.9 Downstream Facing Port Reset.................................................................................................... 203
6.10 Timing Parameters .......................................................................................................................... 203
7 Time Synchronization................................................................................................................................. 204
7.1 Time Synchronization Architecture............................................................................................ 204
7.1.1 Synchronization Hierarchy ............................................................................................ 204
7.1.1.1 Intra-Domain Hierarchy..................................................................................................204
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7.1.1.2 Inter-Domain Hierarchy..................................................................................................205
7.1.2 Time Sync Parameters ..................................................................................................... 205
7.1.2.1 Local Time .............................................................................................................................205
7.1.2.2 Time Offset............................................................................................................................206
7.1.2.3 Frequency Offset.................................................................................................................206
7.2 Time Stamp Measurement ............................................................................................................. 207
7.2.1 Asymmetry Corrections .................................................................................................. 207
7.3 Time Sync Protocol .......................................................................................................................... 208
7.3.1 Time Sync Handshake...................................................................................................... 208
7.3.1.1 Bi-Directional Time Sync Handshake........................................................................209
7.3.1.2 Uni-Directional Time Sync Handshake.....................................................................213
7.3.2 Inter-Domain Time Sync ................................................................................................. 215
7.3.3 Packet Formats .................................................................................................................. 217
7.3.3.1 Time Sync Notification Ordered Set Format ..........................................................217
7.3.3.2 Follow-Up Packet Format...............................................................................................217
7.3.3.3 Inter-Domain Time Stamp Packet...............................................................................219
7.4 Time Computations.......................................................................................................................... 220
7.4.1 Intra-Domain Equations ................................................................................................. 222
7.4.2 Inter-Domain Equations ................................................................................................. 224
7.4.2.1 Inter-Domain Time Stamp Computation .................................................................225
7.4.2.2 Inter-Domain Frequency Offset Computation.......................................................225
7.4.2.3 Inter-Domain Time Offset Computation ..................................................................226
7.4.2.4 Grandmaster Time Computation.................................................................................227
7.4.3 Filtering ............................................................................................................................... 228
7.5 Time Synchronization Accuracy Requirements ...................................................................... 229
7.5.1 Paired Measurement ........................................................................................................ 229
7.5.2 Standalone Measurement ............................................................................................... 229
7.5.3 Measuring Method ............................................................................................................ 230
7.5.4 Accuracy Parameters ....................................................................................................... 231
7.6 Software Configuration .................................................................................................................. 232
7.6.1 Intra-Domain Time Synchronization Setup .............................................................. 232
7.6.2 Inter-Domain Time Synchronization Setup .............................................................. 232
7.6.3 Post Time Mechanism ...................................................................................................... 232
7.6.4 Time Disruption Bit.......................................................................................................... 233
8 Configuration Spaces .................................................................................................................................. 234
8.1 Configuration Fields Access Types ............................................................................................. 234
8.2 Configuration Spaces....................................................................................................................... 234
8.2.1 Router Configuration Space ........................................................................................... 235
8.2.1.1 Basic Configuration Registers.......................................................................................237
8.2.1.2 TMU Router Configuration Capability.......................................................................244
8.2.1.3 Vendor Specific Capability (VSC) ................................................................................251
8.2.1.4 Vendor Specific Extended Capability (VSEC).........................................................252
8.2.2 Adapter Configuration Space......................................................................................... 253
8.2.2.1 Basic Configuration Registers.......................................................................................255
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8.2.2.2 TMU Adapter Configuration Capability....................................................................259
8.2.2.3 Lane Adapter Configuration Capability....................................................................261
8.2.2.4 USB4 Port Capability.........................................................................................................265
8.2.2.5 USB3 Adapter Configuration Capability...................................................................270
8.2.2.6 DP Adapter Configuration Capability........................................................................272
8.2.2.7 PCIe Adapter Configuration Capability.....................................................................283
8.2.3 Path Configuration Space ............................................................................................... 284
8.2.3.1 Path 0 Entry ..........................................................................................................................284
8.2.3.2 Lane Adapters......................................................................................................................285
8.2.3.3 Protocol Adapters ..............................................................................................................287
8.2.3.4 Path Configuration Space Access.................................................................................289
8.2.4 Counters Configuration Space....................................................................................... 290
8.3 Operations .......................................................................................................................................... 291
8.3.1 Router Operations ............................................................................................................ 291
8.3.1.1 DP Tunneling Operations................................................................................................293
8.3.1.2 NVM Operations..................................................................................................................295
8.3.1.3 Router Discovery Operations........................................................................................301
8.3.1.4 Port Control Operations ..................................................................................................307
8.3.2 Port Operations ................................................................................................................. 308
8.3.2.1 Compliance Port Operations .........................................................................................309
8.3.2.2 Service Port Operations...................................................................................................319
8.3.2.3 Receiver Lane Margining Port Operations..............................................................320
9 USB3 Tunneling ............................................................................................................................................ 329
9.1 USB3 Adapter Layer ........................................................................................................................ 330
9.1.1 Encapsulation..................................................................................................................... 330
9.1.1.1 LFPS Encapsulation...........................................................................................................331
9.1.1.2 Ordered Set Encapsulation ............................................................................................334
9.1.1.3 Link Command Encapsulation......................................................................................336
9.1.1.4 Idle Symbols .........................................................................................................................336
9.1.1.5 LMP Encapsulation............................................................................................................336
9.1.1.6 TP Encapsulation................................................................................................................337
9.1.1.7 ITP Encapsulation..............................................................................................................337
9.1.1.8 Data Packet (DP) Encapsulation..................................................................................338
9.1.2 Bandwidth Negotiation ................................................................................................... 340
9.1.3 Timing Parameters ........................................................................................................... 342
9.2 Internal USB3 Device ...................................................................................................................... 342
9.2.1 Link Layer ........................................................................................................................... 343
9.2.1.1 Link Training and Status State Machine (LTSSM)...............................................343
9.2.1.2 Timers and Timeouts........................................................................................................343
9.2.2 USB3 Protocol Layer ........................................................................................................ 344
9.2.3 Descriptors ......................................................................................................................... 344
9.3 Paths..................................................................................................................................................... 344
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9.3.1 Path Setup ........................................................................................................................... 344
9.3.2 Path Teardown................................................................................................................... 345
10 DisplayPort™ Tunneling............................................................................................................................. 346
10.1 DP Adapter Protocol Stack ............................................................................................................ 346
10.1.1 Transport Layer................................................................................................................. 347
10.1.2 Protocol Adapter Layer ................................................................................................... 347
10.1.3 DP Physical Layer ............................................................................................................. 347
10.2 DP Adapter States ............................................................................................................................ 347
10.2.1 Reset ..................................................................................................................................... 348
10.2.2 Present ................................................................................................................................. 348
10.2.3 Plugged................................................................................................................................. 349
10.2.4 Paired ................................................................................................................................... 349
10.3 Interfaces ............................................................................................................................................ 349
10.3.1 DisplayPort ......................................................................................................................... 349
10.3.1.1 LTTPR......................................................................................................................................349
10.3.1.2 Non-LTTPR............................................................................................................................349
10.3.2 Programming Model......................................................................................................... 349
10.3.2.1 Adapter Configuration Space ........................................................................................349
10.3.2.2 Path Configuration Space................................................................................................350
10.3.3 Hot Plug and Hot Removal Events ............................................................................... 350
10.3.3.1 DP OUT Adapters................................................................................................................350
10.3.3.2 DP IN Adapters ....................................................................................................................351
10.3.4 DisplayPort Over USB4 Fabric ...................................................................................... 353
10.3.4.1 DisplayPort Data Packet Types ....................................................................................353
10.3.4.2 AUX Path Packet..................................................................................................................353
10.3.4.3 Main-Link Path Packet Formats...................................................................................360
10.4 System Flows ..................................................................................................................................... 360
10.4.1 Connection Manager Discovery .................................................................................... 360
10.4.2 Path Configuration............................................................................................................ 361
10.4.2.1 Setup ........................................................................................................................................361
10.4.2.2 Tear-down.............................................................................................................................363
10.4.3 HPD Event Propagation................................................................................................... 363
10.4.3.1 HPD Plug.................................................................................................................................363
10.4.3.2 HPD Unplug...........................................................................................................................363
10.4.3.3 IRQ ............................................................................................................................................364
10.4.3.4 HPD Delay Requirements ...............................................................................................364
10.4.3.5 Manual HPD Control .........................................................................................................364
10.4.4 AUX Request and Response Handling ......................................................................... 365
10.4.4.1 LTTPR Mode .........................................................................................................................365
10.4.4.2 Non-LTTPR Mode...............................................................................................................366
10.4.4.3 AUX Delay Requirements................................................................................................370
10.4.4.4 Aggregated DisplayPort Capabilities .........................................................................371
10.4.4.5 DPCD Tunneling Device-Specific Field .....................................................................372
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10.4.5 DP Adapters Init Flow ..................................................................................................... 372
10.4.5.1 Multi-Function DP..............................................................................................................372
10.4.6 Source Discovery............................................................................................................... 372
10.4.6.1 LTTPR Recognition and Modes Change ...................................................................373
10.4.6.2 DPRX Capabilities Read ...................................................................................................373
10.4.6.3 Sink Count Read..................................................................................................................374
10.4.7 Down-Spread Control ...................................................................................................... 374
10.4.8 Stream Mode Set................................................................................................................ 374
10.4.9 DSC and FEC Enable ......................................................................................................... 374
10.4.10 DP Link Training ............................................................................................................... 375
10.4.10.1 LTTPR......................................................................................................................................375
10.4.10.2 Non-LTTPR............................................................................................................................380
10.4.10.3 Transition to High Speed Tunnel ................................................................................382
10.4.11 Power States Set................................................................................................................ 382
10.4.12 DP Main-Link Disable ...................................................................................................... 382
10.4.13 Link-Init ............................................................................................................................... 382
10.4.14 DP PHY Testability............................................................................................................ 383
10.4.14.1 DP IN Adapter PHY Layer Testing ..............................................................................383
10.4.14.2 DP OUT Adapter PHY Layer Testing ..........................................................................383
10.5 High Speed Tunneling ..................................................................................................................... 384
10.5.1 SST Tunneling .................................................................................................................... 384
10.5.1.1 Video Data Packet ..............................................................................................................385
10.5.1.2 Main Stream Attribute Packet ......................................................................................390
10.5.1.3 Blank Start Packet..............................................................................................................392
10.5.1.4 Secondary Data Packet ....................................................................................................393
10.5.1.5 Fill Count................................................................................................................................397
10.5.2 MST Tunneling ................................................................................................................... 400
10.5.2.1 Sub-MTP TU..........................................................................................................................400
10.5.2.2 MTP to Sub-MTP TU Examples.....................................................................................406
10.5.2.3 MST Packet Format ...........................................................................................................408
10.5.2.4 MST Packets to DP MTP...................................................................................................409
10.5.3 FEC......................................................................................................................................... 409
10.5.3.1 SR Count.................................................................................................................................409
10.5.3.2 DP IN Adapter Requirements .......................................................................................410
10.5.3.3 DP OUT Adapter Requirements ...................................................................................410
10.5.3.4 FEC_DECODE Packet.........................................................................................................410
10.5.4 DP OUT Adapter Buffer ................................................................................................... 411
10.5.4.1 Buffer Operation.................................................................................................................412
10.5.4.2 Accumulation Cycles .........................................................................................................412
10.5.5 HDCP ..................................................................................................................................... 413
10.6 DP Link Clock Sync........................................................................................................................... 413
10.6.1 Synchronization Method................................................................................................. 413
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10.6.1.1 Events ......................................................................................................................................414
10.6.1.2 Lifetime Counter.................................................................................................................414
10.6.1.3 DP Clock Sync Packet........................................................................................................416
10.6.2 DP Adapter Requirements .............................................................................................. 417
10.6.2.1 DP IN Adapter Requirements .......................................................................................417
10.6.2.2 DP OUT Adapter Requirements ...................................................................................418
10.7 Timing Parameters .......................................................................................................................... 418
11 PCI Express Tunneling................................................................................................................................ 420
11.1 PCIe Adapter Layer .......................................................................................................................... 421
11.1.1 Encapsulation..................................................................................................................... 421
11.1.1.1 PCIe TLP and DLLP............................................................................................................421
11.1.1.2 PCIe Ordered Sets ..............................................................................................................425
11.1.1.3 Electrical Idle State............................................................................................................427
11.1.1.4 PERST ......................................................................................................................................427
11.1.2 USB4 Hot-Plug.................................................................................................................... 428
11.2 Internal PCIe Ports .......................................................................................................................... 428
11.2.1 PCIe Physical Layer Logical Sub-block ....................................................................... 428
11.2.1.1 Encoding.................................................................................................................................428
11.2.1.2 Link Training and Status State Machine (LTSSM)...............................................428
11.2.1.3 ASPM L1 Entry.....................................................................................................................429
11.2.1.4 Clock Tolerance Compensation....................................................................................429
11.2.1.5 Compliance Mode...............................................................................................................429
11.2.1.6 Clock Power Management..............................................................................................429
11.2.1.7 L2 State ...................................................................................................................................429
11.2.2 PCIe Data Link Layer........................................................................................................ 429
11.2.3 PCIe Transaction Layer ................................................................................................... 429
11.2.4 PCIe Link Timers (Informative) ................................................................................... 430
11.2.5 Precision Time Measurement (PTM) Mechanism ................................................... 431
11.2.5.1 Parameter Generator........................................................................................................433
11.2.5.2 Parameter Consumer........................................................................................................433
11.2.5.3 PTM Calculations................................................................................................................434
11.2.6 Timing Parameters ........................................................................................................... 435
11.3 Paths..................................................................................................................................................... 436
11.3.1 Path Set-Up ......................................................................................................................... 436
11.3.2 Path Tear-Down................................................................................................................. 436
12 Host Interface................................................................................................................................................ 438
12.1 Descriptor Ring Mode ..................................................................................................................... 439
12.1.1 DW, Byte, and Bit Order .................................................................................................. 439
12.1.2 Raw Mode ............................................................................................................................ 439
12.1.3 Frame Mode ........................................................................................................................ 439
12.2 End-to-End (E2E) Flow Control ................................................................................................... 441
12.2.1 E2E Flow Control Packets .............................................................................................. 441
12.2.1.1 E2E Credit Grant Packet..................................................................................................441
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12.2.1.2 E2E Credit Sync Packet....................................................................................................443
12.2.2 Flow Control Rules ........................................................................................................... 443
12.2.2.1 Credit Update .......................................................................................................................443
12.2.2.2 Credit Counter Synchronization..................................................................................443
12.2.2.3 Transmitting Host Interface Rules .............................................................................444
12.2.2.4 Receiving Host Interface Rules.....................................................................................445
12.3 Transmit Interface ........................................................................................................................... 446
12.3.1 Transmit Descriptor Structure ..................................................................................... 446
12.3.2 Transmit Flow.................................................................................................................... 447
12.3.2.1 Frame Mode..........................................................................................................................447
12.3.2.2 Raw Mode ..............................................................................................................................448
12.4 Receive Interface .............................................................................................................................. 449
12.4.1 Receive Descriptor Structure ........................................................................................ 449
12.4.2 Receive Flow....................................................................................................................... 451
12.4.2.1 Frame Mode..........................................................................................................................451
12.4.2.2 Raw Mode ..............................................................................................................................452
12.5 Interrupts ........................................................................................................................................... 453
12.5.1 Interrupt Causes................................................................................................................ 453
12.5.2 Interrupt Masks ................................................................................................................. 453
12.5.3 Interrupt Vectors .............................................................................................................. 453
12.5.4 Interrupt Moderation ...................................................................................................... 453
12.6 Programming Interface .................................................................................................................. 454
12.6.1 Access Types....................................................................................................................... 454
12.6.2 Registers Summary........................................................................................................... 455
12.6.3 Registers Description ...................................................................................................... 456
12.6.3.1 Host Interface Control......................................................................................................456
12.6.3.2 Transmit Descriptor Rings.............................................................................................457
12.6.3.3 Receive Descriptor Rings................................................................................................459
12.6.3.4 Interrupts...............................................................................................................................462
12.7 Timing Parameters .......................................................................................................................... 467
13 Interoperability with Thunderbolt™ 3 (TBT3) Systems .................................................................. 468
13.1 Electrical Layer ................................................................................................................................. 468
13.2 Logical Layer...................................................................................................................................... 468
13.2.1 Sideband Channel ............................................................................................................. 468
13.2.1.1 Bidirectional Re-timer .....................................................................................................468
13.2.1.2 Transactions .........................................................................................................................469
13.2.1.3 SB Register Space ...............................................................................................................471
13.2.1.4 Lane Initialization ..............................................................................................................472
13.2.2 Logical Layer State Machine .......................................................................................... 477
13.2.2.1 CLd State.................................................................................................................................477
13.2.2.2 TS1 and TS2 Ordered Sets..............................................................................................477
13.2.3 USB4 Link Operation........................................................................................................ 478
13.2.3.1 USB4 Link Transitions .....................................................................................................478
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13.2.3.2 Pre-Coding.............................................................................................................................478
13.2.4 Sleep and Wake.................................................................................................................. 478
13.2.4.1 Entry to Sleep.......................................................................................................................478
13.2.4.2 Behavior in Sleep State ....................................................................................................479
13.2.4.3 Wake Events .........................................................................................................................479
13.2.4.4 Exit from Sleep ....................................................................................................................479
13.2.5 Timing Parameters ........................................................................................................... 479
13.3 Transport Layer ................................................................................................................................ 480
13.3.1 Adapter Numbering Rules .............................................................................................. 480
13.3.2 Maximum HopID................................................................................................................ 480
13.3.3 Connectivity Rules ............................................................................................................ 480
13.4 Configuration Layer ......................................................................................................................... 480
13.4.1 Notification Packet ........................................................................................................... 480
13.4.2 Bit Banging Interface ....................................................................................................... 481
13.4.3 Control Packet Routing ................................................................................................... 481
13.4.3.1 Downstream-Bound Packets.........................................................................................481
13.4.3.2 Uninitialized Router Flow ..............................................................................................482
13.5 Time Synchronization ..................................................................................................................... 482
13.6 Configuration Spaces....................................................................................................................... 483
13.6.1 Router Configuration Space ........................................................................................... 483
13.6.1.1 Vendor Specific 1 Capability..........................................................................................484
13.6.1.2 Vendor Specific 3 Capability..........................................................................................488
13.6.1.3 Vendor Specific 4 Capability..........................................................................................490
13.6.1.4 Vendor Specific Extended 6 Capability.....................................................................491
13.6.2 Adapter Configuration Space......................................................................................... 496
13.6.2.1 Basic Attributes...................................................................................................................496
13.6.2.2 USB4 Port Capability.........................................................................................................497
13.7 PCI Express Tunneling .................................................................................................................... 497
13.7.1 PCIe Power Management ................................................................................................ 497
13.7.1.1 L1...............................................................................................................................................497
13.7.1.2 L2...............................................................................................................................................498
13.8 DisplayPort Tunneling .................................................................................................................... 498
13.8.1 AUX Handling ..................................................................................................................... 498
13.8.1.1 DP IN Adapter Requirements .......................................................................................498
13.8.1.2 DP OUT Adapter Requirements ...................................................................................498
13.8.2 IRQ Handling ...................................................................................................................... 498
13.8.3 Connection Manager Discovery .................................................................................... 499
13.8.3.1 TBT3 Connection Manager ............................................................................................499
13.8.3.2 TBT3 Router Discovery ...................................................................................................499
13.8.4 Sink Count Read ................................................................................................................ 500
13.8.5 Power States Set................................................................................................................ 500
13.8.6 DisplayPort Link Training .............................................................................................. 500
13.8.6.1 DP IN Adapter Requirements .......................................................................................500
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13.8.6.2 DP OUT Adapter Requirements ...................................................................................502
13.9 USB3 Functionality .......................................................................................................................... 503
13.10 Host-to-Host Tunneling .................................................................................................................. 504
A Verification of CRC, Scrambling, and FEC Calculations .................................................................... 505
A.1 Transport Layer Packet HEC......................................................................................................... 505
A.2 Control Packet CRC .......................................................................................................................... 505
A.3 Sideband Channel AT Transaction CRC ..................................................................................... 505
A.4 Scrambler............................................................................................................................................ 506
A.5 Logical Layer RS-FEC ...................................................................................................................... 507
A.6 USB3 Tunneling CRC........................................................................................................................ 512
A.7 Host Interface Frame CRC.............................................................................................................. 513
A.8 ECC Examples .................................................................................................................................... 516
B Summary of Transport Layer Packets.................................................................................................... 518
C Examples of Link Power Management Flows ...................................................................................... 519
C.1 Entry to Low Power States ............................................................................................................ 519
C.1.1 Successful Entry to CL2 State ........................................................................................ 519
C.1.2 Successful Entry to CL0s State ...................................................................................... 519
C.1.3 Rejection to Enter CL2 State.......................................................................................... 520
C.1.4 Concurrent Requests to Enter Low Power State ..................................................... 521
C.1.5 CL2_REQ Ordered Sets are Not Received................................................................... 521
C.1.6 CL2_REQ Ordered Sets are Partially Received ......................................................... 522
C.1.7 Error in CL2_ACK Ordered Sets .................................................................................... 523
C.1.8 Error in CL_OFF Ordered Sets ....................................................................................... 524
C.2 Exit from Low Power States .......................................................................................................... 525
C.2.1 Example: Exit from CL0s State ...................................................................................... 525
C.2.2 Example: Exit from CL2 (or CL1) State ...................................................................... 527
D Serial Time Link Protocol (STLP)............................................................................................................ 530
D.1 Time Synchronization ..................................................................................................................... 530
D.2 Serial Time Link Packet Format................................................................................................... 530
D.3 TMU_CLK_OUT and TMU_CLK_IN................................................................................................. 533
E Ingress Buffer Space.................................................................................................................................... 534
E.1 Target Bandwidth Buffer Calculation ........................................................................................ 534
E.1.1 Example for USB3 Tunneling Ingress Buffer Calculation ..................................... 534
E.2 Ingress Buffers Calculation for DP Main Path ......................................................................... 535
Figures
Figure 2-1. USB4/USB3.2 Dual Bus System Architecture ................................................................................................. 11
Figure 2-2. Single-Lane USB4 Link .............................................................................................................................................. 12
Figure 2-3. Dual-Lane USB4 Link ................................................................................................................................................. 13
Figure 2-4. Example of a USB4-Based Dock ............................................................................................................................ 14
Figure 2-5. USB4 Functional Stack Layers ............................................................................................................................... 16
Figure 2-6. USB4 Port, Protocol Adapter and Control Adapter across Functional Layers ................................. 16
Figure 2-7. Example USB4 Physical Topology (No Loop) and Spanning Tree......................................................... 18
Figure 2-8. Example USB4 Physical Topology (with Loop) and Spanning Tree ..................................................... 18
Figure 2-9. Paths across a USB4 Fabric ..................................................................................................................................... 19
Figure 2-10. USB4 Communication by Functional Layer .................................................................................................. 20
Figure 2-11. Example Control Packet Traversing Several Routers............................................................................... 21
Figure 2-12. Example USB4 Host-to-Host Connections ..................................................................................................... 22
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Figure 2-13 Example of a USB4 Host with USB3 Tunneling Highlighted.................................................................... 25
Figure 2-14. Example of a USB4 Hub with USB3 Tunneling Highlighted................................................................... 26
Figure 2-15. Example of a USB4 Peripheral Device with USB3 Tunneling Highlighted ...................................... 26
Figure 2-16. Protocol Stack for USB3 Tunneling................................................................................................................... 27
Figure 2-17. Example of a USB4 Fabric with USB3 Tunneling........................................................................................ 28
Figure 2-18. Protocol Stacks along a USB3 Tunnel .............................................................................................................. 29
Figure 2-19. Example Topology for DisplayPort Tunneling ............................................................................................ 29
Figure 2-20. DP IN and OUT Protocol Adapters in LTTPR Mode................................................................................... 30
Figure 2-21. DP IN and OUT Protocol Adapters in Non-LTTPR Mode......................................................................... 31
Figure 2-22. Protocol Stacks along a DisplayPort Tunneled Path ................................................................................. 32
Figure 2-23. Example Structure of a USB4 Host with PCIe Tunneling Highlighted............................................... 33
Figure 2-24. Example USB4 Hub with PCIe Tunneling Highlighted ............................................................................. 33
Figure 2-25. Example USB4 Device with PCIe Tunneling Highlighted........................................................................ 34
Figure 2-26. Protocol Stack for PCIe Tunneling .................................................................................................................... 34
Figure 2-27. Example of a USB4 Fabric with PCIe Tunneling.......................................................................................... 35
Figure 2-28. Protocol Stacks along a PCIe Tunnel................................................................................................................ 36
Figure 2-29. Protocol Stacks along a Path between Hosts................................................................................................ 37
Figure 2-30. Descriptor Ring and Data Buffers...................................................................................................................... 38
Figure 3-1. Combined Forward-Error-Correction and Pre-Coding Scheme............................................................. 41
Figure 3-2. Compliance Points Definition................................................................................................................................. 42
Figure 3-3. Examples for AC-Coupling Capacitor Placement........................................................................................... 42
Figure 3-4. Jitter Transfer Function............................................................................................................................................ 43
Figure 3-5. Reference Receiver Equalization.......................................................................................................................... 44
Figure 3-6. Frequency Response of Gen 2 Reference CTLE.............................................................................................. 45
Figure 3-7. Frequency Response of Gen 3 Reference CTLE.............................................................................................. 45
Figure 3-8. Example Transmitter Frequency Variation During Training .................................................................. 49
Figure 3-9. Example Transmitter Frequency During Steady-State............................................................................... 49
Figure 3-10. TX Differential Return Loss Mask...................................................................................................................... 50
Figure 3-11. TX Common-Mode Return Loss Mask ............................................................................................................. 50
Figure 3-12. Transmitter Equalizer Structure ....................................................................................................................... 51
Figure 3-13. Transmitter Equalization Frequency Response for Gen 2 Systems ................................................... 53
Figure 3-14. Transmitter Equalization Frequency Response for Gen 3 Systems ................................................... 53
Figure 3-15. TX Mask Notations ................................................................................................................................................... 55
Figure 3-16. RX Differential Return-Loss Mask..................................................................................................................... 58
Figure 3-17. RX Common Mode Return-Loss Mask ............................................................................................................. 58
Figure 3-18. Receiver Tolerance Test Topologies ................................................................................................................ 59
Figure 3-19. Receiver Tolerance Test Setups ......................................................................................................................... 60
Figure 3-20. Captive Device Compliance Test Setup........................................................................................................... 63
Figure 3-21. Captive Device Receiver Test Setup ................................................................................................................. 69
Figure 3-22. Signaling During Power Management State Exit........................................................................................ 71
Figure 3-23. Software Margining Mode Example ................................................................................................................. 72
Figure 3-24. Hardware Margining Flow.................................................................................................................................... 73
Figure 3-25. RX Margining Range Requirements.................................................................................................................. 74
Figure 3-26. Optional RX Margining Range Capabilities.................................................................................................... 75
Figure 4-1. Cable Topologies (Informative)............................................................................................................................ 77
Figure 4-2. Symbol and Bit Order on Sideband Channel ................................................................................................... 78
Figure 4-3. Propagation of a Broadcast RT Transaction.................................................................................................... 81
Figure 4-4. Sideband Channel Receive Transaction State Machine.............................................................................. 84
Figure 4-5. Overview of Lane Initialization............................................................................................................................. 94
Figure 4-6. Example of Lane Reversal........................................................................................................................................ 95
Figure 4-7. Progression of Link Equalization ......................................................................................................................... 98
Figure 4-8. The Lane Adapter State Machine........................................................................................................................100
Figure 4-9. Training Sub-State Machine..................................................................................................................................102
Figure 4-10. Lane Bonding Sub-State Machine....................................................................................................................110
Figure 4-11. Structure of a CL_WAKE1.X Ordered Set......................................................................................................114
Figure 4-12. Packet Flow in the Logical Layer .....................................................................................................................130
Figure 4-13. Byte Transmission Order on Lanes ................................................................................................................131
Figure 4-14. Byte Ordering of Transport Layer Packets to the Logical Layer .......................................................131
Figure 4-15. Byte Ordering of Idle Packets to the Logical Layer..................................................................................132
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Figure 4-16. Symbol Encoding of Data Symbols..................................................................................................................133
Figure 4-17. Symbol Encoding of Ordered Set Symbols ..................................................................................................134
Figure 4-18. Bit and Byte Ordering on the Wire – Data Payload .................................................................................135
Figure 4-19. Bit and Byte Ordering on the Wire – Ordered Set Payload ..................................................................136
Figure 4-20. RS-FEC Data Structures........................................................................................................................................139
Figure 4-21. Lane Disable of the Upstream Adapter .........................................................................................................147
Figure 4-22. Lane Disable Flow ..................................................................................................................................................148
Figure 4-23. Lane Adapter Enable Flow..................................................................................................................................149
Figure 5-1. Convention for Transport Layer Diagrams....................................................................................................156
Figure 5-2. Transport Layer Packet Format..........................................................................................................................157
Figure 5-3. Idle Packet Contents.................................................................................................................................................159
Figure 5-4. Credit Grant Packet Format..................................................................................................................................160
Figure 5-5. Path Credit Sync Packet Format .........................................................................................................................161
Figure 5-6. Shared Buffers Credit Sync Packet Format....................................................................................................161
Figure 5-7. Two Concurrent Data Symbols Example ........................................................................................................163
Figure 5-8. Routing Table..............................................................................................................................................................165
Figure 5-9. Routing Example........................................................................................................................................................167
Figure 5-10. Example of Connectivity for USB3 Adapters ..............................................................................................168
Figure 5-11. Egress Adapter Scheduler...................................................................................................................................177
Figure 6-1. Example of TopologyID Assignment.................................................................................................................182
Figure 6-2. Router State Machine...............................................................................................................................................183
Figure 6-3. Control Packet Format............................................................................................................................................184
Figure 6-4. Route String Format.................................................................................................................................................185
Figure 6-5. Read Request...............................................................................................................................................................186
Figure 6-6. Read Response............................................................................................................................................................188
Figure 6-7. Write Request .............................................................................................................................................................189
Figure 6-8. Write Response ..........................................................................................................................................................190
Figure 6-9. Notification Packet....................................................................................................................................................191
Figure 6-10. Notification Acknowledgment Packet...........................................................................................................192
Figure 6-11. Hot Plug Event Packet...........................................................................................................................................193
Figure 6-12. Inter-Domain Request..........................................................................................................................................194
Figure 6-13. Inter-Domain Response .......................................................................................................................................195
Figure 6-14. Example of Control Packet Routing Between Domains .........................................................................196
Figure 7-1. Time Synchronization Hierarchy within a Domain (Informative)......................................................205
Figure 7-2. Local Time Counter Format..................................................................................................................................206
Figure 7-3. TimeOffsetFromGM Register Format.................................................................................................................206
Figure 7-4. FreqOffsetFromGM Register Format..................................................................................................................206
Figure 7-5. Time Measurement Model for 64/66b Encoding...........................................................................................207
Figure 7-6. Bi-Directional Time Sync Handshake...............................................................................................................209
Figure 7-7. Slave State Machine for Bi-Directional Time Sync Handshake (Recommended).........................211
Figure 7-8. Master State Machine for Bi-Directional Time Sync Handshake (Recommended)......................212
Figure 7-9. Uni-Directional Time Sync Handshake............................................................................................................213
Figure 7-10. Master State Machine for Uni-Directional Time Sync Handshake (Recommended)................214
Figure 7-11. Slave State Machine for Bi-Directional Time Sync Handshake (Recommended) ......................214
Figure 7-12. Inter-Domain Time Sync Protocol (Informative).....................................................................................217
Figure 7-13. Follow-Up Packet Format ...................................................................................................................................218
Figure 7-14. Inter-Domain Time Stamp Packet Format...................................................................................................220
Figure 7-15. Inter-Domain Topology (Informative)..........................................................................................................221
Figure 7-16. Filter Attenuation ...................................................................................................................................................228
Figure 7-17. Dynamic Noise Types............................................................................................................................................229
Figure 7-18. Standalone Measurement Points .....................................................................................................................230
Figure 7-19. Time Events...............................................................................................................................................................231
Figure 7-20. Measuring Method .................................................................................................................................................231
Figure 8-1. Structure of the Router Configuration Space................................................................................................236
Figure 8-2. UUID Format................................................................................................................................................................244
Figure 8-3. Structure of the TMU Router Configuration Capability............................................................................245
Figure 8-4. Structure of a Vendor Specific Capability .......................................................................................................251
Figure 8-5. Structure of a Vendor Specific Extended Capability ..................................................................................252
Figure 8-6. Structure of the Adapter Configuration Space .............................................................................................254
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Figure 8-7. Basic Configuration Registers of the Adapter Configuration Space....................................................255
Figure 8-8. Structure of the TMU Adapter Configuration Capability .........................................................................259
Figure 8-9. Structure of the Lane Adapter Configuration Capability .........................................................................261
Figure 8-10. Structure of USB4 Port Capability...................................................................................................................265
Figure 8-11. Structure of USB3 Adapter Configuration Capability .............................................................................270
Figure 8-12. Structure of DP IN Adapter Configuration Capability ............................................................................273
Figure 8-13. Structure of DP OUT Adapter Configuration Capability ........................................................................278
Figure 8-14. Structure of PCIe Adapter Configuration Capability...............................................................................283
Figure 8-15. Structure of Path 0 Entry Configuration Space .........................................................................................285
Figure 8-16. Structure of Path Entry ‘n’ in Path Configuration Space at Lane Adapter .....................................286
Figure 8-17. Structure of Path Entry ‘n’ in Path Configuration Space of a Protocol Adapter..........................287
Figure 8-18. Configuration of a Path.........................................................................................................................................290
Figure 8-19. Structure of the Counters Configuration Space.........................................................................................290
Figure 8-20. Get Capabilities Operation Data Response for Capability Index 0....................................................304
Figure 9-1. LFPS Tunneled Packet Format ............................................................................................................................332
Figure 9-2. Ordered Set Tunneled Packet Format..............................................................................................................335
Figure 9-3. Link Command Tunneled Packet Format.......................................................................................................336
Figure 9-4. Tunneled ITP Packet Format................................................................................................................................337
Figure 9-5. Structure of an Unsegmented USB3 Data Packet........................................................................................338
Figure 9-6. Segmentation of a USB3 Data Packet................................................................................................................339
Figure 9-7. Bandwidth Negotiation by the Internal Host Controller .........................................................................341
Figure 9-8. Bandwidth Negotiation by the Connection Manager ................................................................................342
Figure 10-1. DP Adapter Protocol Stack Layers ..................................................................................................................347
Figure 10-2. DP Adapter State Machine ..................................................................................................................................348
Figure 10-3. DP Adapter Path Directions ...............................................................................................................................350
Figure 10-4. DP Stream Resource Mapping Examples .....................................................................................................352
Figure 10-5. AUX Channel Framing...........................................................................................................................................354
Figure 10-6. AUX Packet Format................................................................................................................................................354
Figure 10-7. AUX Packet Example .............................................................................................................................................355
Figure 10-8. HPD Packet Format................................................................................................................................................356
Figure 10-9. SET_CONFIG Packet Format...............................................................................................................................356
Figure 10-10. ACK Packet Format..............................................................................................................................................360
Figure 10-11. Power On to HPD Sequence.............................................................................................................................361
Figure 10-12. Target AUX Transaction Flow ........................................................................................................................366
Figure 10-13. Snoop AUX Transaction Flow.........................................................................................................................366
Figure 10-14. Example DP Source Discovery Sequence ..................................................................................................367
Figure 10-15. DP IN Adapter AUX Handling State Machine ...........................................................................................369
Figure 10-16. AUX Timing.............................................................................................................................................................371
Figure 10-17. Example DP Source Discovery Sequence ..................................................................................................373
Figure 10-18. DP Link Training – LTTPR CR_DONE ..........................................................................................................377
Figure 10-19. DP Link Training – LTTPR – EQ Phase........................................................................................................378
Figure 10-20. DP Link Training – DPRX – CR_DONE Phase............................................................................................379
Figure 10-21. DP Link Training – DPRX – EQ Phase..........................................................................................................380
Figure 10-22. Main-Link SST Stream to Tunneled Packets ............................................................................................385
Figure 10-23. TU Set Packing for a 4-Lane Main-Link......................................................................................................386
Figure 10-24. TU Set Packing for a 2-Lane Main-Link......................................................................................................386
Figure 10-25. TU Set Packing for a 1-Lane Main-Link......................................................................................................387
Figure 10-26. EOC Symbol Packing Example........................................................................................................................388
Figure 10-27. TU Set Header Format........................................................................................................................................388
Figure 10-28. Video Data Packet Format................................................................................................................................390
Figure 10-29. MSA Header Format............................................................................................................................................390
Figure 10-30. MSA Header Format............................................................................................................................................391
Figure 10-31. Blank Start Header Format..............................................................................................................................392
Figure 10-32. Blank Start Packet Format...............................................................................................................................393
Figure 10-33. Secondary TU Header Format........................................................................................................................394
Figure 10-34. Tunneled Secondary Data Path Format.....................................................................................................396
Figure 10-35. Secondary Data to Secondary TUs Examples ..........................................................................................397
Figure 10-36. Non-Secondary Data Packet Fill Count Examples .................................................................................399
Figure 10-37. Secondary Data Packet Fill Count Examples............................................................................................400
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Figure 10-38. Sub-MTP TU Structures.....................................................................................................................................401
Figure 10-39. Sub-MTP TU Header Format...........................................................................................................................401
Figure 10-40. Sub-MTP TU 4-Lane Mapping.........................................................................................................................405
Figure 10-41. Sub-MTP TU 2-Lane Mapping.........................................................................................................................405
Figure 10-42. Sub-MTP TU 1-Lane Mapping.........................................................................................................................406
Figure 10-43. Unallocated Sequence, 1-Lane .......................................................................................................................406
Figure 10-44. Shifting SR, 1-Lane...............................................................................................................................................407
Figure 10-45. ACT Sequence, 1-Lane........................................................................................................................................407
Figure 10-46. SF and VCPF Sequence 4-Lane .......................................................................................................................408
Figure 10-47. MST Packet Format.............................................................................................................................................409
Figure 10-48. FEC_DECODE Packet Format ..........................................................................................................................411
Figure 10-49. FEC Command Format.......................................................................................................................................411
Figure 10-50. Active Video to Blanking...................................................................................................................................412
Figure 10-51: Adjust PLL Event Occurrence..........................................................................................................................414
Figure 10-52. Lifetime Counter Format..................................................................................................................................415
Figure 10-53. Filtered Lifetime Counter Logic Concept...................................................................................................415
Figure 10-54. DP Clock Sync Packet Format.........................................................................................................................416
Figure 10-55. DP Clock Sync Packet Example ......................................................................................................................417
Figure 11-1. Tunneled PCIe TLP.................................................................................................................................................422
Figure 11-2. Tunneled PTM Example.......................................................................................................................................423
Figure 11-3. Tunneled PCIe DLLP..............................................................................................................................................424
Figure 11-4. PCIe DLLP and TLP Tunneled Packet Payload...........................................................................................425
Figure 11-5: Example of PTM Relationships..........................................................................................................................432
Figure 11-6: PTM ResponseD Message ....................................................................................................................................433
Figure 11-7: TMU to PTM Parameters Illustration .............................................................................................................435
Figure 12-1. Segmentation of a Frame.....................................................................................................................................440
Figure 12-2. Example of Forwarding an E2E Credit Grant Packet..............................................................................442
Figure 12-3. E2E Credit Grant / Sync Packet Format........................................................................................................442
Figure 12-4. Transmit Descriptor Structure .........................................................................................................................446
Figure 12-5. Receive Descriptor Structure (Posted by Host)........................................................................................449
Figure 12-6. Receive Descriptor Structure (Posted by Host Interface Adapter Layer).....................................450
Figure 12-7. Interrupt Moderation............................................................................................................................................454
Figure 12-8. Structure of the Interrupt Status Registers.................................................................................................462
Figure 12-9. Structure of the Interrupt Vector Allocation Registers (IVAR)..........................................................465
Figure 12-10. Structure of the Receive Ring Vacancy Control Register....................................................................466
Figure 13-1. Bidirectional Re-timer Topology .....................................................................................................................469
Figure 13-2. Bounce Mechanism................................................................................................................................................471
Figure 13-3. Structure of the Vendor Specific 1 Capability ............................................................................................484
Figure 13-4. Structure of the Vendor Specific 3 Capability ............................................................................................488
Figure 13-5. Structure of the Vendor Specific 4 Capability ............................................................................................490
Figure 13-6. Structure of the Vendor Specific Extended 6 Capability .......................................................................491
Figure 13-7. Structure of the Common Region ....................................................................................................................491
Figure 13-8. Structure of a USB4 Port Region......................................................................................................................493
Figure 13-9. DP IN Adapter Link Training State Machine...............................................................................................501
Figure 13-10. DP OUT Adapter Link Training State Machine........................................................................................502
Figure 13-11. Example of a USB4-Based Dock with an Internal Host Controller.................................................503
Figure A-1. Examples of Transport Layer Packet HEC Calculation.............................................................................505
Figure A-2. Examples of USB3 Tunneling Calculations ....................................................................................................513
Figure A-3. Example of a Credit Grant Record .....................................................................................................................516
Figure A-4. Example of an HPD Packet Payload ..................................................................................................................516
Figure A-5. Example of a SET_CONFIG Packet Payload....................................................................................................516
Figure A-6. Example of TU Set Header.....................................................................................................................................517
Figure A-7. Example of a Sub-MTP TU Header.....................................................................................................................517
Figure A-8. Example of an E2E Credit Sync Packet Payload ..........................................................................................517
Figure C-1. Successful Entry to CL2 State...............................................................................................................................519
Figure C-2. Successful Entry to CL0s State.............................................................................................................................520
Figure C-3. Failure to Enter CL2 State......................................................................................................................................520
Figure C-4. Concurrent Requests to Enter CL2 State.........................................................................................................521
Figure C-5. Error in CL2_REQ Ordered Sets ..........................................................................................................................522
Version 1.0 - xxx - Universal Serial Bus 4
August, 2019 Specification
Copyright © 2019 USB 3.0 Promoter Group. All rights reserved.
Figure C-6. CL2_REQ Ordered Sets are Partially Received .............................................................................................522
Figure C-7. Errors in CL2_REQ Reception and CL_NACK Response............................................................................523
Figure C-8. Error in CL2_ACK Ordered Sets...........................................................................................................................524
Figure C-9. Error in CL_OFF Ordered Sets..............................................................................................................................524
Figure C-10. CL0s Exit.....................................................................................................................................................................526
Figure C-11. CL2 (or CL1) Exit.....................................................................................................................................................528
Figure D-1. Pulse Width Modulation ........................................................................................................................................530
Figure D-2. Serial Time Link Packet Structure.....................................................................................................................531
Figure D-3. Serial Time Link Packet Format.........................................................................................................................531
Figure D-4. TMU_CLK_OUT and TMU_CLK_IN Parameters.............................................................................................532
Figure D-5. Definition of TCOJTR..................................................................................................................................................533