实例介绍
【实例简介】
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or tw
PLEASEL DONT VIOLATE THE LAW This document is copyrighted by JEDEC and may not be reproduced without permission For information contact JEdEC Solid State Technology Association 3103 North 1 Oth street Suite 240 South Arlington, VA22201-2107 orrefertowww.jedec.orgunderStandards-documents/CopyrightInformation JEDEC Standard No, 209-4B Page 1 LOW POWER DOUBLE DATA RATE (LPDDR)4 From JEDEC Board Ballot JCB-16-51, formulated under the cognizance of the JC-42 6 Subcommittee on Low Power Memories.) Scope This document defines the LPDDR4 standard, including features functionalities ac and dc characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3JESD79-3), DDR4(JESD79-4 ), LPDDR ( JESD209), LPDDR2 (JESD209-2)and LPDDR3 JESD209-3) Each aspect of the standard was considered and approved by committee ballot(s). the accumulation of these ballots was then incorporated to prepare the LPDDR4 standard JEDEC Standard No. 209-4B Page 2 Package ballout and Pin definition 2.1 Pad order 2.1.1 Pad order for dual channel ch A Top Ch B Top DD2 1 DD2 101DD2 141DD2 2 CKE A 102 MSS 142 CKE B /DD1 43 CS A 03DD1 143 CS B DD2 44 SS 04DD2 144 NSS 5 CA1 A 105 MSS 145心CA1B 6 NSSQ 6 CAO A 106 MSSQ 146 CAO B DQ8 A 7 D 107DQ8 B 147DD2 8 DDQ 8 ODT(ca)_A 108 NDDQ 48 ODT(ca)B 9 DQ9 A 9 NSS 109 DQ9 B 149NSS 10 NSSQ 50DD1 110 MSSQ 150DD1 1 DQ10 A 51 NSSQ 111DQ10B 151 NSSQ 12 NDDQ 2 DQ7 A 112 VDDQ 152 DQ7 B 13 DQ11 A 3 NDDQ 113DQ11B 153№DDQ 14 SSQ 54 DQ6A 114 NSSQ 154 DQ6 B 15 DQS1_t_A 55 NSSQ 115 DQS1 t 155 NSSQ 16 DQS1 CA 56 DQ5 A 116 DQS1 CB156 DQ5 B 17 DDQ 57 DDQ 117 NDDQ 157NDDQ 18 58 DQ4_A 118M 158D4B 19 MSSQ 59 NSSQ 119 MSSQ 159 MSSQ 20 DQ12A 20 DQ12 B 160DM 21 NDDQ 1 NDDQ 121 DDQ 161MDDQ 22 DQ13A 62 DQSO_C_A 122DQ13B 162 DQSO C B 23 SSQ 63 DQSo t A 23 MSSQ 163 DQSo t B 24 DQ14A 64 SSQ 24Q14B164NQ 25 DDQ 65 DQ3A 125 NDDQ 165 DQ3_B 26 DQ15_A 66 NDDQ 26DQ15_ DDQ SSQ 7 DQ2 A 127sQ 167 DQ2 B 68 NSSQ 128 RESET_n]VSSQ VDDQ 9 DQ1 A 129 VDDQ 169 DQ1 B 30 DD2 0 NDDQ 130DD2 170 VDDQ 1 DD1 1 DQ0 A 131DD1 171 DQ0 B 32 NSS 2 MSSQ 132 NSS 172 NSSQ 33 CA5 A 133 CA5 B 173 NSS 34CA4 A 74DD2 134 CA4 B 174DD2 35 DD2 75DD1 135DD2 175|DD1 36 CA3_A 76 SS 36 CA3_B 176NSS 7 CA2 A 7 D 137 CA2 B 177DD2 38 MSS Ch A Bottom 138 NSS Ch B Bottom 39 CKc A 139 CK C B 40 CK_t_A 140 CK t B requires review of MR and calibration features assigned to specific data bits/bytes Swapping at the application level NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte NOTE 2 Additional pads are allowed for DRAM mtg-specific pads(DNU), or additional power pads as long as the extra pads are grouped with like-named pads JEDEC Standard No, 209-4B Page 3 2.1 Pad Order(contd) 2.1.2 Pad order for single channel TOP 1 DD2 40 CK C VSS 41 CK t DD1 2 DD2 DD2 43 CKE 5 NSS 4 CS VSSQ 5 DQ8 46CA1 DDQ 7 CAO 9 DQ9 8 DD2 10 NSSQ 9 DT(ca) 11DQ10 50 NSS 12 NDDQ 13pQ11 52 MSSQ 14 NSSQ 53pQ7 5 DQS1 t 54 MDDQ 16 DQS1 C 55pQ6 7 MDDQ 6 SsQ 57pQ5 19 NSSQ 58 NDDQ 20pQ12 59pQ4 p1ⅣDDQ 0 MssQ 22pQ13 23 SSQ 92 NDDQ 24pQ14 3 DQSO_ C 25 NDDQ 4 paso_t 26pQ15 65 NSSQ 27 SSq 6 pQ3 28区Q 7 NDDQ 9 NDDQ 8 DQ2 30 DD 9 SSQ 31 RESET n 70pQ1 2 DD1 1 MDDQ 33 NSS 2 DQ0 34cA5 73 MSSQ 35cA4 4 NSS 6|DD2 5 DD2 37 CA3 6 DD1 38 CA2 7 NSS 39 MSS 8 DD2 Bottom NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of mR and calibration features assigned to specific data bits/bytes NOtE 2 Additional pads are allowed for DRAM mfg-specific pads (DNU), or additional power pads as long as the extra pads are grouped with like-named pads NotE3 A RESET n pad is added. The reset n pad location is vendor specific. See vendor device datasheets for details about rESeT n pad location 2.2 Package Ballout 2.2.1 272 ball 15 mm x 15 mm 0.4 mm pitch, Quad-Channel POP FBGA (top view) Using Variation VFFCDB for Mo-273 23 89101112131415161718192021 26 333435 ss VDE1 CA4_a VDDC 2C1_a VDcoDQ15-al 2:_a VDDQ Dast VDDQ DQ1D ss DQ8_a D20_c VDD1 DC2_c VDDQ Dso_c DQ5 c DO7 DNU CA3 a s CAs a 200_a C CAz_ cK_c-a CKEO-cCKE1_c VDD2 a CK t c VDD2 ECED_a vs CKE :A2 G CA3 c VDD1 H CALa vss VDD2 VDDQ ∠o0c∠Q1c Da15 c VDDQ DOE Ck t cK c VSSDQ14 Mno5-a noz_ DMI na12-cnQ1_1 DQ, CA, CS, DNU, NC vss cQst_c Dos_a asc t a Dos t dQs c Dost_tc DQ11-c VDDQ DQ2 a RESET n ZQ DO10cVDDO U DQ1 aI Vs VSS DQ9 c WI_ VD Do1_b VS5 VSS NOTE 1 15 mm x 15 mm, 0.4 mm pitch AAI VDDO Do10 dVDDQ note2 272 ball count, 36 rows aB Das_b Dasc_tb NotE 3 Top View, Al in top left corner. cOst_tc DQ11_d AC PaSO. VSS NOTE 4 ODT(ca)_[x] balls are wired to OdT(ca)[x] pads of Rank O DRAM die. ODT (ca)_x] pads for other vSs DOS1-c_d AD VDDQDMIO-_b ranks(if present) are disabled in the package DMI1-dVDDQ aE DQ5_b Da4_b NoTE 5 Package Channel a and Channel c shall be assigned to die Channel a of different DRAM die 2012dDa13d NotE 6 Die pad VsS and vssQ signals are combined to VSS package balls vss DQ14d AG VDDQ Da7_b NOTE 7 Package requires dual channel die or functional equivalent of single channel die-stack Da15_d VDO AHI CAC b ODTca _ b AJI CAl b VSS VSs CA5 d AL I C<Et-b AM C<ED_b vSS CK C d APcA2bcK。b ceo d_d ar VSS CA3 b s cAb vss RESET vss a14. b vss b vss pos1 tb vss bo11b DNU D1CA4b VDDC NC VDrQDQ15-b VDD2 DQ13_ bo12_b VDDo bosic_b vDDoDo13-b vss Da8_bDo0-dydp1 Da2_d vDO Daso_c d vADa DMio_d vonzDa5-d vbo Do7_d voDo cAo_d vDDa._d vDD1vssDNU 2.2.2 LPDDR4 34X34 Quad x16 Channel (Fits 14x14 0. 4 mm pitch)-Using MO-317A 67891011121314151617181920212223242526272829 A NC\DD2 DQ3_A vss DQ5 A ODTica)d CAo A cs:ACKE1 A Vss VsscQ1-A VDD2 wDo1 A zQ1_A z01DDq:0c non voD2 Dq13c vss yssCA2cCKE1-ccs1cCAo-c OOT ca)d DQ5-c VSs DQ3 C VDD2 NCA BVSSDQ-A MIO_ A wrQ DC7_A VDD? S0_A_A VDD2CA4ADQ15A nQ15-CCA4_C unn?CKFn_C DMTO C CA1 A VDD2 I YSSCAS-A YSS CA3_C VSS VDD2CA1_C DQ1AIDQSO_t A DCSO_ c A VSS DC6_A vSs CK CA VSS CAS_A DQ14 A VSS DQS1 cCAIrQS1_ A voDo DQB A D28 C vEDe Dosl tCI DQS1e-C vSS DQ14CCA5-C vSS CKtcI VSs DQ6-cI vSs DQ50 c c DosotCIDQ1-C VoDD E VDD2 VSS VSS VDD2E F VDD2VDD2 VDD2 VDD2F G yS SSG H RFURFU R司 M RFU RF 凡|RM NRFURFU FURN RRR习 R R VRFU W REL RE NOTE 1 14 mm x 14 mm, 0.4 mm pitch note 2 376 ball count. 34 rows RRRFY NOTE 3 Top View, A1 in top left corner AB|R元uRF NOTE 4 ODT(ca)_[x] balls are wired to ODT(ca)X] pads of Rank 0 DRAM die. ODT(ca)X] pads for other RR RU AB ranks(if present) are disabled in the package AC RFU RFU NoTE 5 Package Channel a and channel d shall be assigned to die channel a of different lPddR4 die NoTE 6 DRAM die pad VsS and vssQ signals are combined to VSS package balls AE RFU RFL NOTE 7 Package requires dual channel die or functional equivalent of single channel die-stack RR RU AE AF RFURFU RRR=AF RRURRAG cmmO AH vSS VSS VSSAH AJ nnz VDD2 VDD2AJ AKI VDD2 VSS VSS VDD2 AK DO1 B DOS0 t B DCSO c B vsS DC6 3 vSs CK B CK cB VSS CA5 B D014 B VSSDOS1 c B DOSI: B vDDQ DOB B D08 D VEDQ t D COS1 c D vs Q14 D ICAS DVSS E DI CK t D vSs DO6 D VSS 2050 c D DoS0 t D DO1 D az AM[p∞ VDDQ VSsVES∞4 CA1_B VDD2wcA3 B vss VoDQcQ12ws DQ2_B VCD2 VDD2 DQp DDQ VSS CA3 DDQ DQ0_D AM DC7BVDD2 CS0_ECKEO-_B VDD2 CA4_BDQ15B RFU RFU VSS. AP NC \DD2 Do3 B vss Do5 oDeca) cAo Bcs: B CKE1B B vss vss co1 DQ10_B RFU RFU DQ-0_D CA2_D CKE1_D CS1_DCA DQ3 13 JEDEC Standard No. 209-4B Page 6 2.2.3 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323A im cCoM Mssm kssm pATSm CcOm bATOm bLKm Vccn bAT6m vicam DAT7m Ccam STm SSm CCm MSSm VDDI CCm pATim pAT4m VSSm CcQm MSSm PAT2m PAT3m VSSm SSm MMC VCCQm SSm SSm SSm SF8 vnDa Q1 A 2Q0 A DD1 VDD VDD2 VDD eMCP 144FBGA VDDO 19X21 DDO VDD2 DO2 A VDD2 SiA VDDQ VDDO VDD VDD pC12 A DQ13 O4 A Q14A DD1 5A NSS FA2_ A VDD2 CK_c_A NSS E0_A Pso_ A FA1 A VCD pQs ADD2 3s VDDQ FQ15A DD2 CK_t A kKE1-A F31_A ves FA0 A ODT(a) A VDD1 VODQ ss NOTE 10. 4 mm pitch 2 rows NOTE 2 Top View, A1 in top left corner. noTE 3 Body size: 8 mm x 9.5 mm NoTE 4 ODT(ca)a balls are wired to ODT (ca)A pads of Rank 0 DRAM die. ODT(ca) pads for other anks(if present) are disabled in the package NotE 5 DRAM die pad vss and vssQ signals are combined to Vss package balls NoTE 6 The flash ball-out supports eMMC 5.X NOTE 7 Vendor specific function (VSF)-this terminal should not have any external electrical connections but it may have an internal connection the terminal may be routed to provide accessibility and may be used for general purpose vendor specific operations 【实例截图】
【核心代码】
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or tw
PLEASEL DONT VIOLATE THE LAW This document is copyrighted by JEDEC and may not be reproduced without permission For information contact JEdEC Solid State Technology Association 3103 North 1 Oth street Suite 240 South Arlington, VA22201-2107 orrefertowww.jedec.orgunderStandards-documents/CopyrightInformation JEDEC Standard No, 209-4B Page 1 LOW POWER DOUBLE DATA RATE (LPDDR)4 From JEDEC Board Ballot JCB-16-51, formulated under the cognizance of the JC-42 6 Subcommittee on Low Power Memories.) Scope This document defines the LPDDR4 standard, including features functionalities ac and dc characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3JESD79-3), DDR4(JESD79-4 ), LPDDR ( JESD209), LPDDR2 (JESD209-2)and LPDDR3 JESD209-3) Each aspect of the standard was considered and approved by committee ballot(s). the accumulation of these ballots was then incorporated to prepare the LPDDR4 standard JEDEC Standard No. 209-4B Page 2 Package ballout and Pin definition 2.1 Pad order 2.1.1 Pad order for dual channel ch A Top Ch B Top DD2 1 DD2 101DD2 141DD2 2 CKE A 102 MSS 142 CKE B /DD1 43 CS A 03DD1 143 CS B DD2 44 SS 04DD2 144 NSS 5 CA1 A 105 MSS 145心CA1B 6 NSSQ 6 CAO A 106 MSSQ 146 CAO B DQ8 A 7 D 107DQ8 B 147DD2 8 DDQ 8 ODT(ca)_A 108 NDDQ 48 ODT(ca)B 9 DQ9 A 9 NSS 109 DQ9 B 149NSS 10 NSSQ 50DD1 110 MSSQ 150DD1 1 DQ10 A 51 NSSQ 111DQ10B 151 NSSQ 12 NDDQ 2 DQ7 A 112 VDDQ 152 DQ7 B 13 DQ11 A 3 NDDQ 113DQ11B 153№DDQ 14 SSQ 54 DQ6A 114 NSSQ 154 DQ6 B 15 DQS1_t_A 55 NSSQ 115 DQS1 t 155 NSSQ 16 DQS1 CA 56 DQ5 A 116 DQS1 CB156 DQ5 B 17 DDQ 57 DDQ 117 NDDQ 157NDDQ 18 58 DQ4_A 118M 158D4B 19 MSSQ 59 NSSQ 119 MSSQ 159 MSSQ 20 DQ12A 20 DQ12 B 160DM 21 NDDQ 1 NDDQ 121 DDQ 161MDDQ 22 DQ13A 62 DQSO_C_A 122DQ13B 162 DQSO C B 23 SSQ 63 DQSo t A 23 MSSQ 163 DQSo t B 24 DQ14A 64 SSQ 24Q14B164NQ 25 DDQ 65 DQ3A 125 NDDQ 165 DQ3_B 26 DQ15_A 66 NDDQ 26DQ15_ DDQ SSQ 7 DQ2 A 127sQ 167 DQ2 B 68 NSSQ 128 RESET_n]VSSQ VDDQ 9 DQ1 A 129 VDDQ 169 DQ1 B 30 DD2 0 NDDQ 130DD2 170 VDDQ 1 DD1 1 DQ0 A 131DD1 171 DQ0 B 32 NSS 2 MSSQ 132 NSS 172 NSSQ 33 CA5 A 133 CA5 B 173 NSS 34CA4 A 74DD2 134 CA4 B 174DD2 35 DD2 75DD1 135DD2 175|DD1 36 CA3_A 76 SS 36 CA3_B 176NSS 7 CA2 A 7 D 137 CA2 B 177DD2 38 MSS Ch A Bottom 138 NSS Ch B Bottom 39 CKc A 139 CK C B 40 CK_t_A 140 CK t B requires review of MR and calibration features assigned to specific data bits/bytes Swapping at the application level NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte NOTE 2 Additional pads are allowed for DRAM mtg-specific pads(DNU), or additional power pads as long as the extra pads are grouped with like-named pads JEDEC Standard No, 209-4B Page 3 2.1 Pad Order(contd) 2.1.2 Pad order for single channel TOP 1 DD2 40 CK C VSS 41 CK t DD1 2 DD2 DD2 43 CKE 5 NSS 4 CS VSSQ 5 DQ8 46CA1 DDQ 7 CAO 9 DQ9 8 DD2 10 NSSQ 9 DT(ca) 11DQ10 50 NSS 12 NDDQ 13pQ11 52 MSSQ 14 NSSQ 53pQ7 5 DQS1 t 54 MDDQ 16 DQS1 C 55pQ6 7 MDDQ 6 SsQ 57pQ5 19 NSSQ 58 NDDQ 20pQ12 59pQ4 p1ⅣDDQ 0 MssQ 22pQ13 23 SSQ 92 NDDQ 24pQ14 3 DQSO_ C 25 NDDQ 4 paso_t 26pQ15 65 NSSQ 27 SSq 6 pQ3 28区Q 7 NDDQ 9 NDDQ 8 DQ2 30 DD 9 SSQ 31 RESET n 70pQ1 2 DD1 1 MDDQ 33 NSS 2 DQ0 34cA5 73 MSSQ 35cA4 4 NSS 6|DD2 5 DD2 37 CA3 6 DD1 38 CA2 7 NSS 39 MSS 8 DD2 Bottom NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of mR and calibration features assigned to specific data bits/bytes NOtE 2 Additional pads are allowed for DRAM mfg-specific pads (DNU), or additional power pads as long as the extra pads are grouped with like-named pads NotE3 A RESET n pad is added. The reset n pad location is vendor specific. See vendor device datasheets for details about rESeT n pad location 2.2 Package Ballout 2.2.1 272 ball 15 mm x 15 mm 0.4 mm pitch, Quad-Channel POP FBGA (top view) Using Variation VFFCDB for Mo-273 23 89101112131415161718192021 26 333435 ss VDE1 CA4_a VDDC 2C1_a VDcoDQ15-al 2:_a VDDQ Dast VDDQ DQ1D ss DQ8_a D20_c VDD1 DC2_c VDDQ Dso_c DQ5 c DO7 DNU CA3 a s CAs a 200_a C CAz_ cK_c-a CKEO-cCKE1_c VDD2 a CK t c VDD2 ECED_a vs CKE :A2 G CA3 c VDD1 H CALa vss VDD2 VDDQ ∠o0c∠Q1c Da15 c VDDQ DOE Ck t cK c VSSDQ14 Mno5-a noz_ DMI na12-cnQ1_1 DQ, CA, CS, DNU, NC vss cQst_c Dos_a asc t a Dos t dQs c Dost_tc DQ11-c VDDQ DQ2 a RESET n ZQ DO10cVDDO U DQ1 aI Vs VSS DQ9 c WI_ VD Do1_b VS5 VSS NOTE 1 15 mm x 15 mm, 0.4 mm pitch AAI VDDO Do10 dVDDQ note2 272 ball count, 36 rows aB Das_b Dasc_tb NotE 3 Top View, Al in top left corner. cOst_tc DQ11_d AC PaSO. VSS NOTE 4 ODT(ca)_[x] balls are wired to OdT(ca)[x] pads of Rank O DRAM die. ODT (ca)_x] pads for other vSs DOS1-c_d AD VDDQDMIO-_b ranks(if present) are disabled in the package DMI1-dVDDQ aE DQ5_b Da4_b NoTE 5 Package Channel a and Channel c shall be assigned to die Channel a of different DRAM die 2012dDa13d NotE 6 Die pad VsS and vssQ signals are combined to VSS package balls vss DQ14d AG VDDQ Da7_b NOTE 7 Package requires dual channel die or functional equivalent of single channel die-stack Da15_d VDO AHI CAC b ODTca _ b AJI CAl b VSS VSs CA5 d AL I C<Et-b AM C<ED_b vSS CK C d APcA2bcK。b ceo d_d ar VSS CA3 b s cAb vss RESET vss a14. b vss b vss pos1 tb vss bo11b DNU D1CA4b VDDC NC VDrQDQ15-b VDD2 DQ13_ bo12_b VDDo bosic_b vDDoDo13-b vss Da8_bDo0-dydp1 Da2_d vDO Daso_c d vADa DMio_d vonzDa5-d vbo Do7_d voDo cAo_d vDDa._d vDD1vssDNU 2.2.2 LPDDR4 34X34 Quad x16 Channel (Fits 14x14 0. 4 mm pitch)-Using MO-317A 67891011121314151617181920212223242526272829 A NC\DD2 DQ3_A vss DQ5 A ODTica)d CAo A cs:ACKE1 A Vss VsscQ1-A VDD2 wDo1 A zQ1_A z01DDq:0c non voD2 Dq13c vss yssCA2cCKE1-ccs1cCAo-c OOT ca)d DQ5-c VSs DQ3 C VDD2 NCA BVSSDQ-A MIO_ A wrQ DC7_A VDD? S0_A_A VDD2CA4ADQ15A nQ15-CCA4_C unn?CKFn_C DMTO C CA1 A VDD2 I YSSCAS-A YSS CA3_C VSS VDD2CA1_C DQ1AIDQSO_t A DCSO_ c A VSS DC6_A vSs CK CA VSS CAS_A DQ14 A VSS DQS1 cCAIrQS1_ A voDo DQB A D28 C vEDe Dosl tCI DQS1e-C vSS DQ14CCA5-C vSS CKtcI VSs DQ6-cI vSs DQ50 c c DosotCIDQ1-C VoDD E VDD2 VSS VSS VDD2E F VDD2VDD2 VDD2 VDD2F G yS SSG H RFURFU R司 M RFU RF 凡|RM NRFURFU FURN RRR习 R R VRFU W REL RE NOTE 1 14 mm x 14 mm, 0.4 mm pitch note 2 376 ball count. 34 rows RRRFY NOTE 3 Top View, A1 in top left corner AB|R元uRF NOTE 4 ODT(ca)_[x] balls are wired to ODT(ca)X] pads of Rank 0 DRAM die. ODT(ca)X] pads for other RR RU AB ranks(if present) are disabled in the package AC RFU RFU NoTE 5 Package Channel a and channel d shall be assigned to die channel a of different lPddR4 die NoTE 6 DRAM die pad VsS and vssQ signals are combined to VSS package balls AE RFU RFL NOTE 7 Package requires dual channel die or functional equivalent of single channel die-stack RR RU AE AF RFURFU RRR=AF RRURRAG cmmO AH vSS VSS VSSAH AJ nnz VDD2 VDD2AJ AKI VDD2 VSS VSS VDD2 AK DO1 B DOS0 t B DCSO c B vsS DC6 3 vSs CK B CK cB VSS CA5 B D014 B VSSDOS1 c B DOSI: B vDDQ DOB B D08 D VEDQ t D COS1 c D vs Q14 D ICAS DVSS E DI CK t D vSs DO6 D VSS 2050 c D DoS0 t D DO1 D az AM[p∞ VDDQ VSsVES∞4 CA1_B VDD2wcA3 B vss VoDQcQ12ws DQ2_B VCD2 VDD2 DQp DDQ VSS CA3 DDQ DQ0_D AM DC7BVDD2 CS0_ECKEO-_B VDD2 CA4_BDQ15B RFU RFU VSS. AP NC \DD2 Do3 B vss Do5 oDeca) cAo Bcs: B CKE1B B vss vss co1 DQ10_B RFU RFU DQ-0_D CA2_D CKE1_D CS1_DCA DQ3 13 JEDEC Standard No. 209-4B Page 6 2.2.3 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323A im cCoM Mssm kssm pATSm CcOm bATOm bLKm Vccn bAT6m vicam DAT7m Ccam STm SSm CCm MSSm VDDI CCm pATim pAT4m VSSm CcQm MSSm PAT2m PAT3m VSSm SSm MMC VCCQm SSm SSm SSm SF8 vnDa Q1 A 2Q0 A DD1 VDD VDD2 VDD eMCP 144FBGA VDDO 19X21 DDO VDD2 DO2 A VDD2 SiA VDDQ VDDO VDD VDD pC12 A DQ13 O4 A Q14A DD1 5A NSS FA2_ A VDD2 CK_c_A NSS E0_A Pso_ A FA1 A VCD pQs ADD2 3s VDDQ FQ15A DD2 CK_t A kKE1-A F31_A ves FA0 A ODT(a) A VDD1 VODQ ss NOTE 10. 4 mm pitch 2 rows NOTE 2 Top View, A1 in top left corner. noTE 3 Body size: 8 mm x 9.5 mm NoTE 4 ODT(ca)a balls are wired to ODT (ca)A pads of Rank 0 DRAM die. ODT(ca) pads for other anks(if present) are disabled in the package NotE 5 DRAM die pad vss and vssQ signals are combined to Vss package balls NoTE 6 The flash ball-out supports eMMC 5.X NOTE 7 Vendor specific function (VSF)-this terminal should not have any external electrical connections but it may have an internal connection the terminal may be routed to provide accessibility and may be used for general purpose vendor specific operations 【实例截图】
【核心代码】
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