实例介绍
【实例简介】
NVMe的官方文档，需要的可以下载。NVMe协议将PCIe协议整合成简单易懂的方式是现在ssd主流的协议。
NVM Express 1.3 Table of contents 1 INTRODUCTION mm 6 1.1 Overview 1.2 Scope 1.3 Outside of Scope 6666 1.4 Theory of Operation 1.5 Conventions 1.6 Definitio∩s. 12 7 Keywords 15 1.8 Byte, word and Dword Relationships .16 1.9 References 17 1.10 References Under development 17 2 SYSTEM BUS( PCI EXPRESS) REGISTERS…照18 2.1PC| Header.… 面国 .18 2.2 PCI Power Management Capabilities.…… 22 2.3 Message Signaled Interrupt Capability(Optional) 23 2.4 MSl-X Capability(optional) 24 2.5 PCI Express Capability 26 2.6 Advanced Error Reporting Capability( Optional)……… 31 2.7 Other Capability Pointers 35 3 CONTROLLER REGISTERS 3.1 Register Definition 36 3.2 Index/Data Pair registers(Optional) 47 4 DATA STRUCTURES mmmmmmmmmmmm 49 Submission Queue& Completion Queue Definition.….……… 49 4.2 Submission Queue Entry -Command Format 51 4.3 Physical Region Page Entry and List 54 44 Scatter gather list(SGL)…… 55 4.5 Metadata Region(MR)…..… 面面1 6 4.6 Completion Queue Entry 62 4.7 Controller Memory Buffer 68 4.8 Namespace list 69 4.9 Controller list 69 4. 10 Fused Operations ..70 4.11 Command arbitration 5 ADMIN COMMAND SET 74 Abort command 76 5.2 Asynchronous Event Request command “:: 77 5.3 Create I/0 Completion Queue command 81 5.4 Create I/o Submission Queue command .82 5.5 Delete I/O Completion Queue command 84 5.6 Delete I/O Submission Queue command 85 5.7 Doorbe‖! Buffer Config command… 86 5.8 Device Self-test command 87 5.9 Directive Receive command 89 5.10 Directi∨ e send command 89 Firmware Commit command 90 Firmware Image download command 92 5. 13 Get Features command ,国 93 NVM Express 1.3 5.14 Get Log Page command……… 95 5. 15 Identify command 12 Keep Alive command 国面 …139 5.17 NVMe-MI Receive command 140 5.18 NVMe-MI Send command .140 5.19 Namespace attachment command 141 20 Namespace Management command 143 Set features command 145 5.22 Virtualization management command 163 5.23 Format NVM command- NVM Command Set Specific ·: .165 5.24 Sanitize command- nVm command Set specific 167 5.25 Security Receive command-NVM Command Set Specific 169 5.26 Security Send command-NVM Command Set Specific 171 6 NVM COMMAND SETmmmmmummmmm 172 6. 1 Namespaces 173 6.2 Fused Operations 1面国面面面1面国面国面国B 175 6. 3 Command Ordering Requirements 175 6.4 Atomic Operations 176 6.5 End-to-end protection information 80 6.6 Compare command 180 6.7 Dataset Management command 182 6.8 Flush command 185 6.9 Read command ∴185 6. 10 Reservation Acquire command 188 6.11 Reservation Register command.……………… 190 6.12 Reservation Release command 191 6.13 Reservation Report command 192 6.14 Write command 194 6.15 Write Uncorrectable command 197 6.16 Write zeroes command 198 7 GONTROLLER ARCHITECTURE 200 troduction 200 7.2 Command Submission and Completion Mechanism(Informative) 200 7. 3 Resets 207 7.4 Queue Management 208 7.5 Interrupts 209 7.6 Controller Initialization and Shutdown Processing 212 7.7 Asynchronous Event Request Host Software Recommendations(Informative) 214 7.8 Feature values 214 7 NVMe qualified Names .215 7.10 Identifier Format and Layout (Informative) 216 7.11 Unique Identifier… ,国 218 7.12 Keep Alive E1面 219 7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer 220 8 FEATURESmmmmmmmmmmmmm 221 8.1 Firmware Update Process 8.2 Metadata Handling 222 8.3 End-to-end Data Protection(Optional) …223 8.4 Power Management 229 8.5 Virtualization Enhancements(optional) 234 8. 6 Doorbell stride for software emulation 239 8.7 Standard vendor specific command Format 239 NVM Express 1.3 8.8 Reservations(Optional) 239 8.9 Host Memory Buffer(optional) 246 8.10 Replay Protected Memory Block (Optional) 246 Device Self-test Operations(Optional) 258 8.12 Namespace Management( Optional)…… 260 8.13 Boot Partitions(Optional) ,261 8. 14 Telemetry(Optional) .264 8. 15 Sanitize Operations(Optional) 267 9 DIRECTIVES au272 9. Directive Use in l/o commands 272 9. 2 Identify(Directive Type ooh) 273 9. 3 Streams(Directive Type 01h, Optional 275 10 ERROR REPORTING AND RECOVERY mmmmmmmmmmmm 281 10.1 Command and Queue Error Handling…… 281 10.2 Media and Data Error Handling 281 10.3 Memory Error Handling 281 10.4 Internal Controller Error Handling 281 10.5 Controller fatal status Condition 282 NVM Express 1.3 1 Introduction 1.1 Overview NVM Express(NVMe)is an interface that allows host software to communicate with a non-volatile memory subsystem. This interface is optimized for Enterprise and Client solid state drives, typically attached as a register level interface to the PCI Express interface Note: During development, this specification was referred to as enterprise NVmHcl. However the name was modified to NVM Express prior to specification completion This interface is targeted for use in both Client and enterprise systems For an overview of changes from revision 1. 2. 1 to revision 1.3, refer to nvmexpress. org/changes for a document that describes the new features, including mandatory requirements for a controller to comply with revision 1.3 1.1.1 NVMe over pcle and nvme over fabrics NVM Express 1.3 and prior revisions define a register level interface for host software to communicate with a non-volatile memory subs ystem over PCI Express (NVMe over PCle). The NVMe over Fabrics specification defines a protocol interface and related extensions to NVMe that enable operation over other interconnects(e.g, Ethernet, InfiniBand TM, Fibre Channel). The NvMe over Fabrics specification has an NVMe Transport binding for each NVMe Transport (either within that specification or by reference) In this specification a requirement/feature may be documented as specific to NVMe over Fabrics or to a particular NVMe Transport binding. In addition, support requirements for features and functionality may differ between nvme over pcle and name over fabrics To comply with NVM Express 1.2.1, a controller shall support the NVM Subsystem NVMe Qualified Name in the Identify Controller data structure in Figure 109 12Sc。pe The specification defines a register interface for communication with a non-volatile memory subsystem. It lso defines a standard command set for use with the nvm subsystem 1.3 Outside of scope The register interface and command set are specified apart from any usage model for the nvm, but rather only specifies the communication interface to the nvM subsystem. Thus, this specification does not specify whether the non-volatile memory system is used as a solid state drive, a main memory, a cache memory, a backup memory, a redundant memory, etc. Specific usage models are outside the scope, optional, and not licensed This interface is specified above any non-volatile memory management, like wear leveling. Erases and other management tasks for NVM technologies like NANd are abstracted This specification does not contain any information on caching algorithms or techniques The implementation or use of other published specifications referred to in this specification, even if required for compliance with the specification, are outside the scope of this specification(for example, PCI, PCI EXpress and PC-×) 1.4 Theory of Operation NVM Express is a scalable host controller interface designed to address the needs of Enterprise and client systems that utilize PCI Express based solid state drives. The interface provides optimized command submission and completion paths. It includes support for parallel operation by supporting up to 65,535 /0 Queues with up to 64K outstanding commands per l/O Queue. Additionally, support has been added for NVM Express 1.3 many Enterprise capabilities like end-to-end data protection(compatible with SCSI Protection Information commonly known as T10 DIF, and SNIA DIX standards), enhanced error reporting, and virtualization The interface has the following key attributes Does not require uncacheable MMio register reads in the command submission or completion path A maximum of one MMIO register write is necessary in the command submission path Support for up to 65, 535 I0 queues, with each l/0 queue supporting up to 64K outstanding commands Priority associated with each l/o queue with well-defined arbitration mechanism All information to complete a 4KB read request is included in the 64B command itself, ensuring efficient small l/O operation Efficient and streamlined command set Support for MSI/MSI-X and interrupt aggregation Support for multiple namespaces Efficient support for I/o virtualization architectures like SR-lOV Robust error reporting and management capabilities Support for multi-path I/O and namespace sharing This specification defines a streamlined set of registers whose functionality includes Indication of controller capabilities Status for controller failures (command status is processed via cQ directly) Admin Queue configuration(I/O Queue configuration processed via Admin commands Doorbell registers for scalable number of Submission and completion Queues An NVM Express controller is associated with a single pcl function the capabil ities and settings that apply to the entire controller are indicated in the Controller Capabilities(CAP) register and the Identify Controller data structure A namespace is a quantity of non-volatile memory that may be formatted into logical blocks. An NVM Express controller may support multiple namespaces that are referenced using a namespace ID Namespaces may be created and deleted using the Namespace Management and Namespace Attachment commands. The identify namespace data structure indicates capabilities and settings that are specific to a particular namespace. The capabilities and settings that are common to all namespaces are reported by the Identify Namespace data structure for namespace ID FFFFFFFFh NVM Express is based on a paired Submission and Completion Queue mechanism. Commands are placed by host software into a Submission Queue Completions are placed into the associated Completion Queue by the controller. Multiple Submission Queues may utilize the same completion Queue. Submission and Completion Queues are allocated in memory An Admin Submission and associated Completion Queue exist for the purpose of controller management and control(e. g, creation and deletion of o Submission and Completion Queues, aborting commands etc. ) Only commands that are part of the Admin command set may be submitted to the Admin Submission An l/0 Command Set is used with an Io queue pair. This specification defines one 1/0 Command Set, named the NVM Command Set. The host selects one O Command Set that is used for all lo queue pairs Host software creates queues, up to the maximum supported by the controller. Typically the number of command queues created is based on the system configuration and anticipated workload. For example, on a four core processor based system, there may be a queue pair per core to avoid locking and ensure data structures are created in the appropriate processor core's cache. Figure 1 provides a graphical representation of the queue pair mechanism, showing a 1: 1 mapping between Submission Queues and Completion Queues. Figure 2 shows an example where multiple O Submission Queues utilize the same 7 NVM E 1/0 Completion Queue on Core B. Figure 1 and Figure 2 show that there is always a 1: 1 mapping between the Admin Submission Queue and Admin Completion Queue Figure 1: Queue Pair Example, 1: 1 Mapping Host Controller Mgmt Core 0 Core 1 Core N-1 Admin Admin I/O I/O I/O I/O I/O I/O Submission Completion Submission Completion Submission Completion Submission Completion Queue Queue Queue 1 Queue 1 Queue 2 Queue 2 Queue N Queue N Contro∥er Figure 2: Queue Pair Example, n: 1 Mapping Host Controller Mgmt Core A Core B Admin Admin 1/O I/O Submission Completion Submission Completion Submission Submission Submission Completion Queue Queue Queue M Queue N Queue X Queue y Queue Z Controller A Submission Queue(sQ)is a circular buffer with a fixed slot size that the host software uses to submit commands for execution by the controller. The host software updates the appropriate sQ tail doorbell register when there are one to n new commands to execute. The previous sQ tail value is overwritten ir the controller when there is a new doorbell register write. The controller fetches sQ entries in order from the Submission Queue, however, it may then execute those commands in any order Each Submission Queue entry is a command. Commands are 64 bytes in size. The physical memory locations in memory to use for data transfers are specified using Physical Region Page(PRP)entries or Scatter Gather Lists. Each command may include two PRP entries or one Scatter Gather List (SGL segment. If more than two PRP entries are necessary to describe the data buffer, then a pointer to a PrP List that describes a list of PRP entries is provided. If more than one SGl segment is necessary to describe the data buffer, then the SGL segment provides a pointer to the next SGL segment A Completion Queue(CQ) is a circular buffer with a fixed slot size used to post status for completed commands. A completed command is uniquely identified by a combination of the associated sQ identifier NVM Express 1.3 and command identifier that is assigned by host software. Multiple Submission Queues may be associated with a single Completion Queue. This feature may be used where a single worker thread processes all command completions via one Completion Queue even when those commands originated from multiple Submission Queues. The CQ Head pointer is updated by host software atter it has processed completion queue entries indicating the last free CQ slot. a Phase Tag(P)bit is defined in the completion queue entry to indicate whether an entry has been newly posted without consulting a register. This enables host software to determine whether the new entry was posted as part of the previous or current round of completion notifications. Specifically, each round through the Completion Queue entries, the controller verts the Phase Tag bit 1.4.1 Multi-Path l/O and Namespace Sharing This section provides an overview of multi-path O and namespace sharing. Multi-path l/0 refers to two or more completely independent PCI Express paths between a single host and a namespace while namespace sharing refers to the ability for two or more hosts to access a common shared namespace using different NVM Express controllers. Both multi-path /0 and namespace sharing require that the nvm subsystem contain two or more controllers. Concurrent access to a shared namespace by two or more hosts requires some form of coordination between hosts. The procedure used to coordinate these hosts is outside the scope of this specification Figure 3 shows an NVM subsystem that contains a single NvM Express controller and a single PCl Express port. Since this is a single Function PCI Express device, the Nvm Express controller shall be associated with PCI Function 0. A controller may support multiple namespaces. The controller in Figure 3 supports two namespaces labeled NS A and Ns B. Associated with each controller namespace is a namespace ID labeled as NSid 1 and NSID 2, that is used by the controller to reference a specific namespace.The namespace id is distinct from the namespace itself and is the handle a host and controller use to specify a particular namespace in a command The selection of a controller,'s namespace Ids is outside the scope of this specification. In this example namespace id 1 is associated with namespace A and namespace ID 2 is associated with namespace B. Both namespaces are private to the controller and this configuration supports neither multi-path O nor namespace sharing Figure 3: NVM Express Controller with Two Namespaces PCle port PCI Function o i NVM Express Controller NSID 1 NSID 2 NS A B igure 4 shows a multi-Function NVM Subsystem with a single PCI Express port containing two controllers one controller is associated with pcl function o and the other controller is associated with pcl function 1 Each controller supports a single private namespace and access to shared namespace B. The namespace iD shall be the same in all controllers that have access to a particular shared namespace In this example both controllers use namespace id 2 to access shared namespace B NVM Express 1.3 Figure 4: NVM Subsystem with Two Controllers and One Port PCle port cl Function 0 cl Function 1 NVMe controller NVMe controller NSID 1 NSID 2 NSID 3 NSID 2 NS C There is a unique Identify Controller data structure for each controller and a unique Identify Namespace data structure for each namespace Controllers with access to a shared namespace return the Identify Namespace data structure associated with that shared namespace (i. e, the same data structure contents are returned by all controllers with access to the same shared namespace). There is a globally unique mgy型码要:队从而避兔同步问 题。 Controllers associated with a shared namespace may operate on the namespace concurrently. Operations performed by individual controllers are atomic to the shared namespace at the write atomicity level of the controller to which the command was submitted (refer to section 6. 4). The write atomicity level is not required to be the same across controllers that share a namespace. If there are any ordering requirements between commands issued to different controllers that access a shared namespace, then host software or an associated application, is required to enforce these ordering requirements Figure 5 illustrates an NVM Subsystem with two PCI Express ports, each with an associated controller Both controllers map to PCI Function O of the corresponding port. Each PCI Express port in this example is completely independent and has its own PCI Express Fundamental Reset and reference clock input. A reset of a port only affects the controller associated with that port and has no impact on the other controller, shared namespace, or operations performed by the other controller on the shared namespace. the functional behavior of this example is otherwise the same as that illustrated in Figure 4 注释∶每个 PCI Express端口都是完全独立的,并且具有自己的 PCI Express基本复位和参考时钟输入。即使 复位操作也与其他的相互不影响 10 【实例截图】
【核心代码】
NVMe的官方文档，需要的可以下载。NVMe协议将PCIe协议整合成简单易懂的方式是现在ssd主流的协议。
NVM Express 1.3 Table of contents 1 INTRODUCTION mm 6 1.1 Overview 1.2 Scope 1.3 Outside of Scope 6666 1.4 Theory of Operation 1.5 Conventions 1.6 Definitio∩s. 12 7 Keywords 15 1.8 Byte, word and Dword Relationships .16 1.9 References 17 1.10 References Under development 17 2 SYSTEM BUS( PCI EXPRESS) REGISTERS…照18 2.1PC| Header.… 面国 .18 2.2 PCI Power Management Capabilities.…… 22 2.3 Message Signaled Interrupt Capability(Optional) 23 2.4 MSl-X Capability(optional) 24 2.5 PCI Express Capability 26 2.6 Advanced Error Reporting Capability( Optional)……… 31 2.7 Other Capability Pointers 35 3 CONTROLLER REGISTERS 3.1 Register Definition 36 3.2 Index/Data Pair registers(Optional) 47 4 DATA STRUCTURES mmmmmmmmmmmm 49 Submission Queue& Completion Queue Definition.….……… 49 4.2 Submission Queue Entry -Command Format 51 4.3 Physical Region Page Entry and List 54 44 Scatter gather list(SGL)…… 55 4.5 Metadata Region(MR)…..… 面面1 6 4.6 Completion Queue Entry 62 4.7 Controller Memory Buffer 68 4.8 Namespace list 69 4.9 Controller list 69 4. 10 Fused Operations ..70 4.11 Command arbitration 5 ADMIN COMMAND SET 74 Abort command 76 5.2 Asynchronous Event Request command “:: 77 5.3 Create I/0 Completion Queue command 81 5.4 Create I/o Submission Queue command .82 5.5 Delete I/O Completion Queue command 84 5.6 Delete I/O Submission Queue command 85 5.7 Doorbe‖! Buffer Config command… 86 5.8 Device Self-test command 87 5.9 Directive Receive command 89 5.10 Directi∨ e send command 89 Firmware Commit command 90 Firmware Image download command 92 5. 13 Get Features command ,国 93 NVM Express 1.3 5.14 Get Log Page command……… 95 5. 15 Identify command 12 Keep Alive command 国面 …139 5.17 NVMe-MI Receive command 140 5.18 NVMe-MI Send command .140 5.19 Namespace attachment command 141 20 Namespace Management command 143 Set features command 145 5.22 Virtualization management command 163 5.23 Format NVM command- NVM Command Set Specific ·: .165 5.24 Sanitize command- nVm command Set specific 167 5.25 Security Receive command-NVM Command Set Specific 169 5.26 Security Send command-NVM Command Set Specific 171 6 NVM COMMAND SETmmmmmummmmm 172 6. 1 Namespaces 173 6.2 Fused Operations 1面国面面面1面国面国面国B 175 6. 3 Command Ordering Requirements 175 6.4 Atomic Operations 176 6.5 End-to-end protection information 80 6.6 Compare command 180 6.7 Dataset Management command 182 6.8 Flush command 185 6.9 Read command ∴185 6. 10 Reservation Acquire command 188 6.11 Reservation Register command.……………… 190 6.12 Reservation Release command 191 6.13 Reservation Report command 192 6.14 Write command 194 6.15 Write Uncorrectable command 197 6.16 Write zeroes command 198 7 GONTROLLER ARCHITECTURE 200 troduction 200 7.2 Command Submission and Completion Mechanism(Informative) 200 7. 3 Resets 207 7.4 Queue Management 208 7.5 Interrupts 209 7.6 Controller Initialization and Shutdown Processing 212 7.7 Asynchronous Event Request Host Software Recommendations(Informative) 214 7.8 Feature values 214 7 NVMe qualified Names .215 7.10 Identifier Format and Layout (Informative) 216 7.11 Unique Identifier… ,国 218 7.12 Keep Alive E1面 219 7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer 220 8 FEATURESmmmmmmmmmmmmm 221 8.1 Firmware Update Process 8.2 Metadata Handling 222 8.3 End-to-end Data Protection(Optional) …223 8.4 Power Management 229 8.5 Virtualization Enhancements(optional) 234 8. 6 Doorbell stride for software emulation 239 8.7 Standard vendor specific command Format 239 NVM Express 1.3 8.8 Reservations(Optional) 239 8.9 Host Memory Buffer(optional) 246 8.10 Replay Protected Memory Block (Optional) 246 Device Self-test Operations(Optional) 258 8.12 Namespace Management( Optional)…… 260 8.13 Boot Partitions(Optional) ,261 8. 14 Telemetry(Optional) .264 8. 15 Sanitize Operations(Optional) 267 9 DIRECTIVES au272 9. Directive Use in l/o commands 272 9. 2 Identify(Directive Type ooh) 273 9. 3 Streams(Directive Type 01h, Optional 275 10 ERROR REPORTING AND RECOVERY mmmmmmmmmmmm 281 10.1 Command and Queue Error Handling…… 281 10.2 Media and Data Error Handling 281 10.3 Memory Error Handling 281 10.4 Internal Controller Error Handling 281 10.5 Controller fatal status Condition 282 NVM Express 1.3 1 Introduction 1.1 Overview NVM Express(NVMe)is an interface that allows host software to communicate with a non-volatile memory subsystem. This interface is optimized for Enterprise and Client solid state drives, typically attached as a register level interface to the PCI Express interface Note: During development, this specification was referred to as enterprise NVmHcl. However the name was modified to NVM Express prior to specification completion This interface is targeted for use in both Client and enterprise systems For an overview of changes from revision 1. 2. 1 to revision 1.3, refer to nvmexpress. org/changes for a document that describes the new features, including mandatory requirements for a controller to comply with revision 1.3 1.1.1 NVMe over pcle and nvme over fabrics NVM Express 1.3 and prior revisions define a register level interface for host software to communicate with a non-volatile memory subs ystem over PCI Express (NVMe over PCle). The NVMe over Fabrics specification defines a protocol interface and related extensions to NVMe that enable operation over other interconnects(e.g, Ethernet, InfiniBand TM, Fibre Channel). The NvMe over Fabrics specification has an NVMe Transport binding for each NVMe Transport (either within that specification or by reference) In this specification a requirement/feature may be documented as specific to NVMe over Fabrics or to a particular NVMe Transport binding. In addition, support requirements for features and functionality may differ between nvme over pcle and name over fabrics To comply with NVM Express 1.2.1, a controller shall support the NVM Subsystem NVMe Qualified Name in the Identify Controller data structure in Figure 109 12Sc。pe The specification defines a register interface for communication with a non-volatile memory subsystem. It lso defines a standard command set for use with the nvm subsystem 1.3 Outside of scope The register interface and command set are specified apart from any usage model for the nvm, but rather only specifies the communication interface to the nvM subsystem. Thus, this specification does not specify whether the non-volatile memory system is used as a solid state drive, a main memory, a cache memory, a backup memory, a redundant memory, etc. Specific usage models are outside the scope, optional, and not licensed This interface is specified above any non-volatile memory management, like wear leveling. Erases and other management tasks for NVM technologies like NANd are abstracted This specification does not contain any information on caching algorithms or techniques The implementation or use of other published specifications referred to in this specification, even if required for compliance with the specification, are outside the scope of this specification(for example, PCI, PCI EXpress and PC-×) 1.4 Theory of Operation NVM Express is a scalable host controller interface designed to address the needs of Enterprise and client systems that utilize PCI Express based solid state drives. The interface provides optimized command submission and completion paths. It includes support for parallel operation by supporting up to 65,535 /0 Queues with up to 64K outstanding commands per l/O Queue. Additionally, support has been added for NVM Express 1.3 many Enterprise capabilities like end-to-end data protection(compatible with SCSI Protection Information commonly known as T10 DIF, and SNIA DIX standards), enhanced error reporting, and virtualization The interface has the following key attributes Does not require uncacheable MMio register reads in the command submission or completion path A maximum of one MMIO register write is necessary in the command submission path Support for up to 65, 535 I0 queues, with each l/0 queue supporting up to 64K outstanding commands Priority associated with each l/o queue with well-defined arbitration mechanism All information to complete a 4KB read request is included in the 64B command itself, ensuring efficient small l/O operation Efficient and streamlined command set Support for MSI/MSI-X and interrupt aggregation Support for multiple namespaces Efficient support for I/o virtualization architectures like SR-lOV Robust error reporting and management capabilities Support for multi-path I/O and namespace sharing This specification defines a streamlined set of registers whose functionality includes Indication of controller capabilities Status for controller failures (command status is processed via cQ directly) Admin Queue configuration(I/O Queue configuration processed via Admin commands Doorbell registers for scalable number of Submission and completion Queues An NVM Express controller is associated with a single pcl function the capabil ities and settings that apply to the entire controller are indicated in the Controller Capabilities(CAP) register and the Identify Controller data structure A namespace is a quantity of non-volatile memory that may be formatted into logical blocks. An NVM Express controller may support multiple namespaces that are referenced using a namespace ID Namespaces may be created and deleted using the Namespace Management and Namespace Attachment commands. The identify namespace data structure indicates capabilities and settings that are specific to a particular namespace. The capabilities and settings that are common to all namespaces are reported by the Identify Namespace data structure for namespace ID FFFFFFFFh NVM Express is based on a paired Submission and Completion Queue mechanism. Commands are placed by host software into a Submission Queue Completions are placed into the associated Completion Queue by the controller. Multiple Submission Queues may utilize the same completion Queue. Submission and Completion Queues are allocated in memory An Admin Submission and associated Completion Queue exist for the purpose of controller management and control(e. g, creation and deletion of o Submission and Completion Queues, aborting commands etc. ) Only commands that are part of the Admin command set may be submitted to the Admin Submission An l/0 Command Set is used with an Io queue pair. This specification defines one 1/0 Command Set, named the NVM Command Set. The host selects one O Command Set that is used for all lo queue pairs Host software creates queues, up to the maximum supported by the controller. Typically the number of command queues created is based on the system configuration and anticipated workload. For example, on a four core processor based system, there may be a queue pair per core to avoid locking and ensure data structures are created in the appropriate processor core's cache. Figure 1 provides a graphical representation of the queue pair mechanism, showing a 1: 1 mapping between Submission Queues and Completion Queues. Figure 2 shows an example where multiple O Submission Queues utilize the same 7 NVM E 1/0 Completion Queue on Core B. Figure 1 and Figure 2 show that there is always a 1: 1 mapping between the Admin Submission Queue and Admin Completion Queue Figure 1: Queue Pair Example, 1: 1 Mapping Host Controller Mgmt Core 0 Core 1 Core N-1 Admin Admin I/O I/O I/O I/O I/O I/O Submission Completion Submission Completion Submission Completion Submission Completion Queue Queue Queue 1 Queue 1 Queue 2 Queue 2 Queue N Queue N Contro∥er Figure 2: Queue Pair Example, n: 1 Mapping Host Controller Mgmt Core A Core B Admin Admin 1/O I/O Submission Completion Submission Completion Submission Submission Submission Completion Queue Queue Queue M Queue N Queue X Queue y Queue Z Controller A Submission Queue(sQ)is a circular buffer with a fixed slot size that the host software uses to submit commands for execution by the controller. The host software updates the appropriate sQ tail doorbell register when there are one to n new commands to execute. The previous sQ tail value is overwritten ir the controller when there is a new doorbell register write. The controller fetches sQ entries in order from the Submission Queue, however, it may then execute those commands in any order Each Submission Queue entry is a command. Commands are 64 bytes in size. The physical memory locations in memory to use for data transfers are specified using Physical Region Page(PRP)entries or Scatter Gather Lists. Each command may include two PRP entries or one Scatter Gather List (SGL segment. If more than two PRP entries are necessary to describe the data buffer, then a pointer to a PrP List that describes a list of PRP entries is provided. If more than one SGl segment is necessary to describe the data buffer, then the SGL segment provides a pointer to the next SGL segment A Completion Queue(CQ) is a circular buffer with a fixed slot size used to post status for completed commands. A completed command is uniquely identified by a combination of the associated sQ identifier NVM Express 1.3 and command identifier that is assigned by host software. Multiple Submission Queues may be associated with a single Completion Queue. This feature may be used where a single worker thread processes all command completions via one Completion Queue even when those commands originated from multiple Submission Queues. The CQ Head pointer is updated by host software atter it has processed completion queue entries indicating the last free CQ slot. a Phase Tag(P)bit is defined in the completion queue entry to indicate whether an entry has been newly posted without consulting a register. This enables host software to determine whether the new entry was posted as part of the previous or current round of completion notifications. Specifically, each round through the Completion Queue entries, the controller verts the Phase Tag bit 1.4.1 Multi-Path l/O and Namespace Sharing This section provides an overview of multi-path O and namespace sharing. Multi-path l/0 refers to two or more completely independent PCI Express paths between a single host and a namespace while namespace sharing refers to the ability for two or more hosts to access a common shared namespace using different NVM Express controllers. Both multi-path /0 and namespace sharing require that the nvm subsystem contain two or more controllers. Concurrent access to a shared namespace by two or more hosts requires some form of coordination between hosts. The procedure used to coordinate these hosts is outside the scope of this specification Figure 3 shows an NVM subsystem that contains a single NvM Express controller and a single PCl Express port. Since this is a single Function PCI Express device, the Nvm Express controller shall be associated with PCI Function 0. A controller may support multiple namespaces. The controller in Figure 3 supports two namespaces labeled NS A and Ns B. Associated with each controller namespace is a namespace ID labeled as NSid 1 and NSID 2, that is used by the controller to reference a specific namespace.The namespace id is distinct from the namespace itself and is the handle a host and controller use to specify a particular namespace in a command The selection of a controller,'s namespace Ids is outside the scope of this specification. In this example namespace id 1 is associated with namespace A and namespace ID 2 is associated with namespace B. Both namespaces are private to the controller and this configuration supports neither multi-path O nor namespace sharing Figure 3: NVM Express Controller with Two Namespaces PCle port PCI Function o i NVM Express Controller NSID 1 NSID 2 NS A B igure 4 shows a multi-Function NVM Subsystem with a single PCI Express port containing two controllers one controller is associated with pcl function o and the other controller is associated with pcl function 1 Each controller supports a single private namespace and access to shared namespace B. The namespace iD shall be the same in all controllers that have access to a particular shared namespace In this example both controllers use namespace id 2 to access shared namespace B NVM Express 1.3 Figure 4: NVM Subsystem with Two Controllers and One Port PCle port cl Function 0 cl Function 1 NVMe controller NVMe controller NSID 1 NSID 2 NSID 3 NSID 2 NS C There is a unique Identify Controller data structure for each controller and a unique Identify Namespace data structure for each namespace Controllers with access to a shared namespace return the Identify Namespace data structure associated with that shared namespace (i. e, the same data structure contents are returned by all controllers with access to the same shared namespace). There is a globally unique mgy型码要:队从而避兔同步问 题。 Controllers associated with a shared namespace may operate on the namespace concurrently. Operations performed by individual controllers are atomic to the shared namespace at the write atomicity level of the controller to which the command was submitted (refer to section 6. 4). The write atomicity level is not required to be the same across controllers that share a namespace. If there are any ordering requirements between commands issued to different controllers that access a shared namespace, then host software or an associated application, is required to enforce these ordering requirements Figure 5 illustrates an NVM Subsystem with two PCI Express ports, each with an associated controller Both controllers map to PCI Function O of the corresponding port. Each PCI Express port in this example is completely independent and has its own PCI Express Fundamental Reset and reference clock input. A reset of a port only affects the controller associated with that port and has no impact on the other controller, shared namespace, or operations performed by the other controller on the shared namespace. the functional behavior of this example is otherwise the same as that illustrated in Figure 4 注释∶每个 PCI Express端口都是完全独立的,并且具有自己的 PCI Express基本复位和参考时钟输入。即使 复位操作也与其他的相互不影响 10 【实例截图】
【核心代码】
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