JESD 204B 协议规范

【实例简介】
随着转换器分辨率和速度的提高，对更高效率接口的需求也随之增长。JESD204接口可提供这种高效率，较之CMOS和LVDS接口产品在速度、尺寸和成本上更有优势。采用JESD204的设计具有更高的接口速率，能支持转换器的更高采样速率。此外，引脚数量的减少使得封装尺寸更小且布线数量更少，这些都让电路板更容易设计并且整体系统成本更低。该标准可以方便地调整，从而满足未来需求. 2006年4月，JESD204最初版本发布。该版本描述了转换器和接收器（通常是FPGA或ASIC）之间几个G比特的串行数据链路。
PLEASE DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact JEDEC Solid State Technology Association 3103 North 1oth street Suite 240 South Arlington, VA 22201-2107 orrefertowww.jedec.orgunderStandardsandDocuments for alternative contact information JEDEC Standard No 204B P age (From JEDEC Board Ballot JCB-08-01 and JCB-11-47, formulated under the cognizance of JC-16 Committee on Interface Technology. This specification describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification Informative annexes are included to clarify and exemplify the specification Due to the range of applications involved, the intention of the document is to completely specify only the serial data interface and the link protocol Certain signals common to both the interface and the function of the device, such as device clocks and control interfaces, have application-dependent requirements Devices may also have application-dependent modes, such as a low power/ shutdown mode that will affect the interface. In these instances, the specification merely constrains other device properties as they relate to the interface, and leaves the specific implementation up to the designer Revision a of the standard was expanded to support serial data interfaces consisting of single or multiple lanes per converter device. In addition, converter functionality (ADC or DAc) can be distributed over multiple devices All parallel running devices are implemented or specified to run synchronously with each other using the same data format Normally this means that they are part of the same product family Revision b of the standard now supports the following additional functions Mechanism for achieving repeatable, programmable deterministic delay across the JESD204 link Support for serial data rates up to 12.5 Gbps Transition from using frame clock as the main clock source to using device clock as the main clock source. Device clock frequency requirements offer much more flex i bility compared to requiring a frame clock input The logic device(e.g. ASIC or FPGA)is always assumed to be a single device Figure 1 compares the scope of the original JESD204 specification and its revisions JEDEC Standard no 204B Page 2 Although not illustrated in the figure, it is possible to apply multiple, independent instances of the JESD204 standard to the same device JEDEC Standard No 204B P age 3 The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to applies 1. IEEE Std 802.3-2008, Part 3, Section Three, Local and metropolitan area networks -CSMa/CD accessmethodsandPhysicalLayerspecifications2008.http://standards.ieee.org/getieee802/ 2. JEDEC JESD99, Terms, Definitions, and Letter Symbols for Microelectronic Devices 3. OIF-SxI-5-01.0, System Interface Level 5(Sxl-5 ): Common Electrical Characteristics for 2. 488 3. 125Gbps Parallel Interfaces, Optical Internetworking Forum, October 2002 www.oiforum.com/public/documents/oif-sxi5-01.0.pdf 4. OIF-CEI-02.0, Common Electrical 1/O-Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+ bps l/o, Optical Internetworking Forum, February 2005 www.oiforum.com/public/documents/oifCei02.0.pdf The following standards contain provisions that, through references in the text, are informative in this standard 5.AnsiT1.523-2001,AtisTElecomGlossary2000,February2001.http://www.atis.org/tg2k/ 6. IEEE Std 802.3-200&R, Part 3, Section Four, Local and metropolitan area networks -CSMA/CD accessmethodsandPhysicalLayerspecifications2008.http:standardsieeeorg/getieee802, 7. ANSI/EEE Std 91a-1991, Graphic symbols for logic functions, IEEE 1991, ANSI 1994. Summary availableate.g.http://en.wikipediaorg/wikiLogicgate 8. INCITS 450-2009, Information technology Fibre Channel- Physical Interface-4(FC-PI-4), availablefromhttp://webstore.ansi.org 9. INCITS TR-35-2004(R2009), Fibre Channel- Methodologies for Jitter and Signal Quality pecification(fc-mjsq),availablefromhttp://webstore.ansi.org JEDEC Standard No 204B Page 4 For the purposes of this standard, the terms and definitions given in JESD99(reference 2)and the following apply A DC-balanced octet-oriented data encoding specified in reference 1, clause 36.2. 4.(Ref. IEEE802.3) The smallest integer greater than or equal to x A symbol produced by 8B/10B encoding of an octet NoTE 1 While all octets can be encoded as data characters certain octets can also be encoded as control characters notE 2 The same character may exist as two different code groups, depending on running disparity A signal used for sequencing the 8B/10B characters or octets A circuit used to generate synchronous, phase aligned device clocks to various devices in the JESD204B system note A clock generator circuit can include one or more clock generator devices, but they must use a common source clock A set of ten bits that, when representing data, conveys an octet. Ref. IEEE 802.3) An application-specific interface used to pass information(usually status and control information) between a converter device and a logic device and/or between a device and a higher layer application level note The details of the control interface are outside the scope of the serial interface described by this standard A signal used to define the analog sampling moments in a converter NOTE Usually the conversion clock is the same as the sample clock, except in case of interpolating DaCs or decimating adCs, where the conversion clock is faster than the sample clock In all cases, the conversion clock is derived from the device clock An analog-to-digital converter(ADC)or digital-to-analog converter (DaC) NOTE In this standard, a converter is assumed to inter face via a single stream of digital samples A component package containing one or more converters NOtE This standard specifies the interactions between one logic device and one or more converter devices JEDEC Standard No 204B Page 5 An assembly, consisting of parts of two devices and the interconnecting data circuit, that is controlled by a link protocol enabling data to be transferred from a data source to a data sink. (" terminal replaced by"device"in ANSI T I. 523-2001 The inverse of a scrambler. (Ref. ANSI T1. 523-2001) NotE The descrambler output is a signal restored to the state that it had when it entered the associated scrambler, provided that no errors have occurred A master clock signal from which a device must generate its local clocks The greatest integer less than or equal to x a set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signaL (Adapted from ANSI T1.523-2001) NoTE 1 The frame alignment signal does not necessarily occur in each frame NoTE 2 In JESD204, a frame consists of octets and is transmitted over a single lane A signal used for sequencing frames or monitoring their alignment One period of the frame clock, i. e. the duration of one frame NOtE During one frame period, one frame is transmitted over each lane of a multilane link An operating mode used for a converter that is not currently sampling data The transmission path along which a signal propagates (Synonym for"medium"in ANSI T1.523-2001.) A code group that is not found in the proper column of the 8B/10B decoding tables according to the current running disparity. (Ref. IEEE 802.3 A differential signal pair for data transmission in one direction A signal used for sequencing the serial bits on an electrical interface Synonym for“ data link a clock derived inside a device from the device clock and used in the implementation of the JESD204B link within the device NOTE 1 It is possible to align a local clock to an external signal, e.g. SYSREF NOTE 2 An internal copy of the device clock is not a local clock JEDEC Standard no 204B Page 6 A component package containing exclusively or primarily digital logic; e.g,, an ASiC or FPGA notE This standard specifies the interactions between one logic device and one or more converter devices The largest of x and y The smallest of x and y The remainder after dividing x by y (x modulo y) A set of consecutive frames in which the position of each frame can be identified b reference to a multiframe alignment signal. (Ref. ANSI TI. 523-200l) NOTE 1 The multiframe alignment signal does not necessarily occur in each multiframe NoTE 2 In JESD204, a multiframe consists of frames and is transmitted over a single lane A signal used for sequencing multiframes or monitoring their alignment a data communications link that interconnects three or more devices (terminal replaced by“ device” in ansi t1.523-2001.) A group of four data bits. (Ref. IEEE 802.3) A group of eight adjacent binary digits, serving as the input to an 8B/10B encoder or the output of an 8B/10B decoder A circuit attached to a lane for reconstructing a serial bit stream into time-aligned frames NOTE A receiver consists of one physical layer block and one link layer block. The combination of the receiver transport layer and all receiver link layer and physical layer blocks connected to a link a component package containing one or more receiver blocks The simultaneous transitions that occur when signal(P changes from the low logic level to the high logic level and signal(N changes from the high logic level to the low logic level a binary parameter having a value of or, representing the imbalance between the number of ones and zeros in a sequence of 8B/10B code-groups. ( Ref. IEEE 802.3) The instantaneous value of a signal measured or determined at a discrete time(Adapted from ANSI TI.523-2001, "sampled data,) NOTE In the context of JESD204, a sample is always the digital representation of a signal 【实例截图】
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