实例介绍
【实例简介】
PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0
PCI LOCAL BUS SPECIFICATION, REV.3.0 Contents PREFACE SPECIFICATION.……13 INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS) 1查音音鲁垂音音 13 DOCUMENT CONVENTIONS.………14 l. INTRODUCTION…15 1.1. SPECIFICATION CONTENTS ······ 15 1.2. MOTIVATION…… 15 1.3. PCI LOCAL BUS APPLICATIONS 1. 4. PCI LOCAL BUS OVERVIEW 17 1.5. PCI LOCAL BUS FEATURES AND BENEFITS……18 1. 6. ADMINISTRATION …………………20 2. SIGNAL DEFINITION m...mn.. 21 2.1 SIGNAL TYPE DEFINITION 22 2.2. PIN FUNCTIONAL GROUPS..…………22 2.2.1. System Pins……,…,…,,…,… 23 2.2.2. Address and data pins 24 2.2.3. Interface Control Pins........................25 2.2.4. Arbitration Pins(Bus Masters Only) 27 2.2.5. Error Reporting Pins.... 垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂 27 2.2.6. Interrupt Pins( Optional)…… 28 2.2.7. Additional signals 31 2.2.8.64- Bit bus extension pins( Optiona)…,,……………………………33 2.2.9. TAG/Boundary scan Pins(Optional).......34 2. 10. System Management Bus Interface Pins(Optional) 35 2. 3. SIDEBAND SIGNALS 36 2. 4. CENTRAL RESOURCE FUNCTIONS .····:·····.············· 36 3. BUS OPERATION 37 3.1 BUS COMMANDS 37 3.1. Command definition 37 3. 1.2. Command Usage rules 39 3.2. PCI PROTOCOL FUNDAMENTALS 42 3.2.1. Basic Transfer Control ····:············.················ 43 3.2.2. Addressing.............14 3.2.3. Byle lane and Byte enable usage…… 56 3.2.4. Bus Driving and Turnaround 非音垂垂·非 57 3.2.5. Transaction Ordering and posting ….58 3. 2.6. Combining Merging, and Collapsing 。。音垂。音 62 PCI LOCAL BUS SPECIFICATION, REV.3.0 3.3. BUS TRANSACTIONS……64 3.3.1. Read transaction……………65 3.3.2. Write transaction 3.3.3. Transaction termination.………….67 3.4. ARBItRAtION 音垂 3.4.1. Arbitration Signaling protoco1..…………………89 3.4.2. Fast Back-to-Back Transactions. .........................................................9 3.4.3. Arbitration Parking………………………………………9 3.5 LATENCY 95 3.5.1. Target Latency …….95 3.5.2. Master Data latency……….….…….,….….…..……..….,98 3.5.3. Memory Write Maximum Completion Time limit 3.5.4. Arbitration Latency 3.6. OTHER BUS OPERATIONS…… ·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非 110 3.6.1. Device selection…....…,10 3.6.2. Special cycle........... 3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,… 113 3.6.4. Interrupt acknowledg 3.7. ERROR FUNCTIONS 春音·。音垂 115 3.7.. Parity ger 115 3.7.2. Parity Checking...........………,16 3.7.3. Address parity errors…...…,…16 3.7.4. Error Reporting… 1717 3.7.5. Delayed Transactions and Data Parity Errors.......... 20 3.7.6. Error Recovery.............,21 3. 8. 64-BIT BUS EXTENSION 123 3.8.1. Determining bus Width during System initialization.…….…,126 3.9.64- BIT ADDRESSING…..…………………………………………127 3.10 SPECIAL DESIGN CONSIDERATIONS .130 4. ELECTRICAL SPECIFICATION.. m.m.9.137 4.1. OVERVIEW …137 4.1.1. Transition Road Map…… 137 4.1.2. Dynamic vs Static Drive specificalion …138 4.2. COMPONENT SPECIFICATION.……,………………,1…………………139 4.2.1. 5V Signaling environment 140 4.2.2. 33V Signaling environment 鲁鲁·垂垂 146 4.2.3. Timing specification 150 4.2.4.1 determinate Inputs and metastable作,………… 155 4.2.5. Vendor provided specification..,..…,.…………….………1756 4.2.6. Pinout recommendation 157 PCI LOCAL BUS SPECIFICATION. REV.3.0 4.3. SYSTEM BOARD SPECIFICATION.………158 4.3.1. Clock skew,…………………158 4.3.2.R ·· 158 4.3.3. Pull-ups :····.················:····· …161 4.3.4 Power 163 4.3.5. System Timing Budget. ...........164 4.3.6. Physical requirements............………67 4.3.7. Connector Pin assignments…… /68 44. ADD-IN CARD SPECIFICATION 171 4.4.1.Add- in Card Pin Assignment..,.,.,………………,171 4.4.2. Power Requirements….,.,.,.,.,.,.,,.….,76 4.4.3. Physical requirements.........178 5. MECHANICAL SPECIFICATION 181 5.1. OVERVIEW 181 2. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........182 5.3. CONNECTOR PHYSICAL DESCRIPTION…………………195 4. CONNECTOR PHYSICAL REQUIREMENTS. ...............................205 5. CONNECTOR PERFORMANCE SPECIFICATION……………,… 206 6. SYSTEM BOARD IMPLEMENTATION……………207 6. CONFIGURATION SPACE b●看●鲁D鲁0e● 213 6. 1. CONFIGURATION SPACE ORGANIZATION 音垂垂D·垂看垂 …213 6.2. CONFIGURATION SPACE FUNCTIONS .......................216 6.2.1. Device ldentification 鲁垂垂 216 6.2.2. Device Control 鲁着鲁D垂 217 6.2.3. Device status 219 6. 2.4. Miscellaneous registers ·······:········:···:·:··:·:······:··············4······:···· 221 6.2.5. Base addresses……………………….224 63. PCI EXPANSION ROMS 228 6.4. VITAL PRODUCT DATA .229 6.5. DEVICE DRIVERS 229 6.6. SYSTEM RESET.…………………………230 6.7. CAPABILITIES LIST 230 8. MESSAGE SIGNALED INTERRUPTS ...................................................................231 6.8.1. MSI Capability Structure..............232 6.8.2. MSl-X Capability and Table structures……………….……..238 6.8.3. MSI and Msi-X Operation 246 7. 66 MHZ PCI SPECIFICATION 255 7. 1. INTRODUCTION 255 7.2. SCOPE 7. 3. DEVICE IMPI TION CONSIDERATIONS 7.3.1. Configuration space.......255 7. 4. AGENT ARCHITECTURE 256 PCI LOCAL BUS SPECIFICATION, REV.3.0 7.5. PROTOCOL.……256 7.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,256 7.52 Latency..-..-.- 257 7.6. ELECTRICAL SPECIFICATION…………… 257 7.6.. Overview ·.·······.·· 257 7.6.2. Transition roadmap to 66 MHz PCI ·········· .257 7.6.3. Signaling Environment.......... 258 7.6.4. Timing specification.……259 7.6.5. Vendor provided specification. 26.5 7.6.6. Recommendations ·.·························:············:······:········.:·········· 265 7.7. SYSTEM BOARD SPECIFICATION.………,…,……………266 7.7.1. Clock Uncertainty ......266 7.7.2. Reset 267 7.7.3. Pullups..267 7.7.4. Power ..······.·.·::··· ··布鲁····音D鲁番。是。音垂看····非D ∴267 7.7.5. System Timing Budget 7.7.6. Physical requirements 268 7.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,269 7.8. ADD-IN CARD SPECIFICATIONS 春音·。音垂 269 8. SYSTEM SUPPORT FOR SMBUS n271 8. 1. SMBUS SYSTEM REQUIREMENTS 271 8.1.1. Power………27 8. 2. Physical and Logical sMBi 27l 8.1.3. Bus connectivit 272 8.1.4. Master and slave support....….….…..…..…..,273 8.1.5. Addressing and Configuration 273 8.1.6.Ele 274 8.1.7. SMBus behavior on Pcl reset.........................274 8.2.ADD- IN CARD SMBUS REQUIREMENTS…………275 8.2.7 Connection 275 8.2.2. Master and Slave Support...,.…..…….…,...….,275 8.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,275 8. 2. 4. Power 275 8. 2.5. Electrical .········.···························· 275 A. SPECIAL CYCLE MESSAGES ●鲁●e鲁 277 A 1. MESSAGE ENCODINGS 277 A,2. USE OF SPECIFIC ENCODINGS ................................................277 B. STATE MACHINES 279 B. 1. TARGET LOCK MACHINE ·;.···.:..···:...···:··.·:···· 281 B.2. MASTER SEQUENCER MACHINE 283 B 3. MASTER 6 PCI LOCAL BUS SPECIFICATION. REV.3.0 C. OPERATING RULES 289 C 1. WHEN SIGNALS ARE STABLE ..·····.:·.·.::···:·; 289 C.2. MASTER SIGNALS… 音·。·看 290 C.3. TARGET SIGNALS… 291 C.4. DATA PHASES… 292 C.5. ARBITRATION.……………………………………292 C.6. LATeNCY ······:“······· 293 C.7. DEVICE SELECTION……………,……………………………293 C 8. PARITY 垂垂垂D·垂 294 D. CLASS CODES D 1. BASE CLASS OOH...w.w...296 D 2. BASE CLASS OlH 296 D. 3. BASE CLASS O2H ·· 297 D 4. BASE CLASS O3H 297 D.5. BASE CLASS04H.………………………298 D. 6. BASE CLASS OSH 298 D.7. BASE CLASS06H...………….…………………299 D 8. BASE CLASS OZH ,300 D 9. BASE CLASS OSH .301 D.10. BASE CLASS C9H.……………………………………………….301 D.11. BASE CLASS OAH.…………………302 D 12. BASE CLASS OBH 302 D. 13. BASE CLASS OCH 303 D.14. BASE CLASS ODH….… 304 D. 15. BASE CLASS OEH 304 D. 16. BASE CLASS OFH ·····.····;····:·;:······· 304 D.17. BASE CLASS JOH.……………………………………………1305 D, 18. BASE CLASS 11H 305 E. SYSTEM TRANSACTION ORDERING E.I. PRODUCER- CONSUMER ORDERING MODEL 308 E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS 310 E.3. ORDERING OF REQUESTS........................................311 E.4. ORDERING OF DELAYED TRANSACTIONS…………312 E.5. DELAYED TRANSACTIONS AND LOCK# .317 E.6. ERROR CONDⅠ TIONS…… 318 . EXCLUSIVE ACCESSES..m.msn0..319 F.1. EXCLUSIVE ACCESSES ON PCI F 2. STARTING AN EXCLUSIVE ACCESS 321 F.3. CONTINUING AN EXCLUSIVE ACCESS 323 F 4. ACCESSING A LOCKED AGENT 324 F 5. COMPLETING AN EXCLUSIVE ACCESS 325 F. 6. COMPLETE BUS LOCK ......................................................................325 IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327 PCI LOCAL BUS SPECIFICATION, REV.3.0 CAPABILITY IDS。,0329 I. VITAL PRODUCT DATA 331 VPD FORMAT 3 I.2 COMPATIBILITY……………………… ……334 L.3. VPD DEFINITIONS 334 1.3.1. VPD Large and small resource Data Tags...... ·D垂看 334 1.3.2. VPD Example… 337 8 PCI LOCAL BUS SPECIFICATION. REV.3.0 Fiqures FIGURE -I: PCI LOCAL BUS APPLICATIONS 春D FIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM 17 FIGURE2-1: PCI PIN LIST.…………..………… 21 figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48 Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50 Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONS ADDRESS PHASE 51 FIGURE3-4: CONFIGURATION READ…………156 FIGURE3-5: BASIC READ OPERATION………………………65 FIGURE 3-6: BASIC WRITE OPERATION 66 FIGure 3-7: MASTER INITIATED TERMINATION........................ 68 FIGURE3-8: MASTER- ABORT TERMINATION…………69 Figure 3-9: RETRY. ..........................................................................................................73 FiGure 3-10: DISCONNECT WITH DATA. ........................74 FiGure 3-11: MASTER COMPLETION TERMINATION :·:····:··.·4····.··· …75 FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION ····· 76 Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION 76 FiGure 3-14: TARGET-ABORT …177 figure 3-15: BASIC ARBITRATION FIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS …94 FiGurE 3-17: DEVSEL# AsSERTION ·····:···.·:·· 110 Figure 3-1 8: IDSEL STEPPING 114 FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114 FIGURE3-20: PARITY OPERATION……… 116 FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER 125 FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126 FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE 129 FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138 FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.………………… 143 FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling 145 FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING 148 FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150 FIGURE 4-6: CLOCK WAVEFORMS 151 FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS .··4·:······.· 154 FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154 FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT ···“···:.···.····:········· 157 FIGURE4-10: CLOCK SKEW DIAGRAM………158 FIGURE 4-1: RESET TIMING 16l FIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166 FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT). 183 FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184 FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185 FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186 PCI LOCAL BUS SPECIFICATION, REV.3.0 FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187 FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88 FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V) 189 FIGURE 5-8: PCI STANDARD BRACKET ………190 FIGuRE 5-9: PCI LOW PROFILE BRACKET 191 FIGURE 5-10: PCI STANDARD RETAINER ··· 192 FIGURE5-11: IO WINDOW HEIGHT∴………………193 FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194 FIGURE 5-13: 32-BIT CONNECTOR 196 FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197 FIGURE5-15:3.3V/64-BIT CONNECTOR 198 FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199 FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES 2( 垂D ·。垂,音着垂。着音D。。着。D音着音垂。音着音 FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES….201 FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES………………………………202 FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES 203 FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204 FIGURE5-22: CONNECTOR CONTACT DETAIL………………205 FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD 208 FIGURE5-24:32- BIT PCI RISER CONNECTOR……209 FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT 210 FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR 211 FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212 FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER 215 FIGURE 6-2: COMMAND REGISTER LAYOUT 217 FIGURE6-3: STATUS REGISTER LAYOUT……………………………219 FIGURE 6-4: BIST REGISTER LAYOUT 222 FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225 FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O 225 鲁着D音看 FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228 FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231 FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233 FIGURE 6-10: MSI-X CAPABILITY STRUCTURE 238 FIGurE 6-11: MSI-X TABLE STRUCTURE 翻音。音 239 FIGurE 6-12: MSI-X PBA STRUCTURE …239 FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING ······:·················· 257 FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259 FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS 263 FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS 263 FIGURE75:TvAL(MAX) RISING EDGE………… 264 FIGURE 7-6: TVAL(MAX) FALLING EDGE · 265 FIGURE77:TVAL(MIN) AND SLEW RATE…… 265 10 【实例截图】
【核心代码】
PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0
PCI LOCAL BUS SPECIFICATION, REV.3.0 Contents PREFACE SPECIFICATION.……13 INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS) 1查音音鲁垂音音 13 DOCUMENT CONVENTIONS.………14 l. INTRODUCTION…15 1.1. SPECIFICATION CONTENTS ······ 15 1.2. MOTIVATION…… 15 1.3. PCI LOCAL BUS APPLICATIONS 1. 4. PCI LOCAL BUS OVERVIEW 17 1.5. PCI LOCAL BUS FEATURES AND BENEFITS……18 1. 6. ADMINISTRATION …………………20 2. SIGNAL DEFINITION m...mn.. 21 2.1 SIGNAL TYPE DEFINITION 22 2.2. PIN FUNCTIONAL GROUPS..…………22 2.2.1. System Pins……,…,…,,…,… 23 2.2.2. Address and data pins 24 2.2.3. Interface Control Pins........................25 2.2.4. Arbitration Pins(Bus Masters Only) 27 2.2.5. Error Reporting Pins.... 垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂 27 2.2.6. Interrupt Pins( Optional)…… 28 2.2.7. Additional signals 31 2.2.8.64- Bit bus extension pins( Optiona)…,,……………………………33 2.2.9. TAG/Boundary scan Pins(Optional).......34 2. 10. System Management Bus Interface Pins(Optional) 35 2. 3. SIDEBAND SIGNALS 36 2. 4. CENTRAL RESOURCE FUNCTIONS .····:·····.············· 36 3. BUS OPERATION 37 3.1 BUS COMMANDS 37 3.1. Command definition 37 3. 1.2. Command Usage rules 39 3.2. PCI PROTOCOL FUNDAMENTALS 42 3.2.1. Basic Transfer Control ····:············.················ 43 3.2.2. Addressing.............14 3.2.3. Byle lane and Byte enable usage…… 56 3.2.4. Bus Driving and Turnaround 非音垂垂·非 57 3.2.5. Transaction Ordering and posting ….58 3. 2.6. Combining Merging, and Collapsing 。。音垂。音 62 PCI LOCAL BUS SPECIFICATION, REV.3.0 3.3. BUS TRANSACTIONS……64 3.3.1. Read transaction……………65 3.3.2. Write transaction 3.3.3. Transaction termination.………….67 3.4. ARBItRAtION 音垂 3.4.1. Arbitration Signaling protoco1..…………………89 3.4.2. Fast Back-to-Back Transactions. .........................................................9 3.4.3. Arbitration Parking………………………………………9 3.5 LATENCY 95 3.5.1. Target Latency …….95 3.5.2. Master Data latency……….….…….,….….…..……..….,98 3.5.3. Memory Write Maximum Completion Time limit 3.5.4. Arbitration Latency 3.6. OTHER BUS OPERATIONS…… ·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非 110 3.6.1. Device selection…....…,10 3.6.2. Special cycle........... 3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,… 113 3.6.4. Interrupt acknowledg 3.7. ERROR FUNCTIONS 春音·。音垂 115 3.7.. Parity ger 115 3.7.2. Parity Checking...........………,16 3.7.3. Address parity errors…...…,…16 3.7.4. Error Reporting… 1717 3.7.5. Delayed Transactions and Data Parity Errors.......... 20 3.7.6. Error Recovery.............,21 3. 8. 64-BIT BUS EXTENSION 123 3.8.1. Determining bus Width during System initialization.…….…,126 3.9.64- BIT ADDRESSING…..…………………………………………127 3.10 SPECIAL DESIGN CONSIDERATIONS .130 4. ELECTRICAL SPECIFICATION.. m.m.9.137 4.1. OVERVIEW …137 4.1.1. Transition Road Map…… 137 4.1.2. Dynamic vs Static Drive specificalion …138 4.2. COMPONENT SPECIFICATION.……,………………,1…………………139 4.2.1. 5V Signaling environment 140 4.2.2. 33V Signaling environment 鲁鲁·垂垂 146 4.2.3. Timing specification 150 4.2.4.1 determinate Inputs and metastable作,………… 155 4.2.5. Vendor provided specification..,..…,.…………….………1756 4.2.6. Pinout recommendation 157 PCI LOCAL BUS SPECIFICATION. REV.3.0 4.3. SYSTEM BOARD SPECIFICATION.………158 4.3.1. Clock skew,…………………158 4.3.2.R ·· 158 4.3.3. Pull-ups :····.················:····· …161 4.3.4 Power 163 4.3.5. System Timing Budget. ...........164 4.3.6. Physical requirements............………67 4.3.7. Connector Pin assignments…… /68 44. ADD-IN CARD SPECIFICATION 171 4.4.1.Add- in Card Pin Assignment..,.,.,………………,171 4.4.2. Power Requirements….,.,.,.,.,.,.,,.….,76 4.4.3. Physical requirements.........178 5. MECHANICAL SPECIFICATION 181 5.1. OVERVIEW 181 2. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........182 5.3. CONNECTOR PHYSICAL DESCRIPTION…………………195 4. CONNECTOR PHYSICAL REQUIREMENTS. ...............................205 5. CONNECTOR PERFORMANCE SPECIFICATION……………,… 206 6. SYSTEM BOARD IMPLEMENTATION……………207 6. CONFIGURATION SPACE b●看●鲁D鲁0e● 213 6. 1. CONFIGURATION SPACE ORGANIZATION 音垂垂D·垂看垂 …213 6.2. CONFIGURATION SPACE FUNCTIONS .......................216 6.2.1. Device ldentification 鲁垂垂 216 6.2.2. Device Control 鲁着鲁D垂 217 6.2.3. Device status 219 6. 2.4. Miscellaneous registers ·······:········:···:·:··:·:······:··············4······:···· 221 6.2.5. Base addresses……………………….224 63. PCI EXPANSION ROMS 228 6.4. VITAL PRODUCT DATA .229 6.5. DEVICE DRIVERS 229 6.6. SYSTEM RESET.…………………………230 6.7. CAPABILITIES LIST 230 8. MESSAGE SIGNALED INTERRUPTS ...................................................................231 6.8.1. MSI Capability Structure..............232 6.8.2. MSl-X Capability and Table structures……………….……..238 6.8.3. MSI and Msi-X Operation 246 7. 66 MHZ PCI SPECIFICATION 255 7. 1. INTRODUCTION 255 7.2. SCOPE 7. 3. DEVICE IMPI TION CONSIDERATIONS 7.3.1. Configuration space.......255 7. 4. AGENT ARCHITECTURE 256 PCI LOCAL BUS SPECIFICATION, REV.3.0 7.5. PROTOCOL.……256 7.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,256 7.52 Latency..-..-.- 257 7.6. ELECTRICAL SPECIFICATION…………… 257 7.6.. Overview ·.·······.·· 257 7.6.2. Transition roadmap to 66 MHz PCI ·········· .257 7.6.3. Signaling Environment.......... 258 7.6.4. Timing specification.……259 7.6.5. Vendor provided specification. 26.5 7.6.6. Recommendations ·.·························:············:······:········.:·········· 265 7.7. SYSTEM BOARD SPECIFICATION.………,…,……………266 7.7.1. Clock Uncertainty ......266 7.7.2. Reset 267 7.7.3. Pullups..267 7.7.4. Power ..······.·.·::··· ··布鲁····音D鲁番。是。音垂看····非D ∴267 7.7.5. System Timing Budget 7.7.6. Physical requirements 268 7.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,269 7.8. ADD-IN CARD SPECIFICATIONS 春音·。音垂 269 8. SYSTEM SUPPORT FOR SMBUS n271 8. 1. SMBUS SYSTEM REQUIREMENTS 271 8.1.1. Power………27 8. 2. Physical and Logical sMBi 27l 8.1.3. Bus connectivit 272 8.1.4. Master and slave support....….….…..…..…..,273 8.1.5. Addressing and Configuration 273 8.1.6.Ele 274 8.1.7. SMBus behavior on Pcl reset.........................274 8.2.ADD- IN CARD SMBUS REQUIREMENTS…………275 8.2.7 Connection 275 8.2.2. Master and Slave Support...,.…..…….…,...….,275 8.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,275 8. 2. 4. Power 275 8. 2.5. Electrical .········.···························· 275 A. SPECIAL CYCLE MESSAGES ●鲁●e鲁 277 A 1. MESSAGE ENCODINGS 277 A,2. USE OF SPECIFIC ENCODINGS ................................................277 B. STATE MACHINES 279 B. 1. TARGET LOCK MACHINE ·;.···.:..···:...···:··.·:···· 281 B.2. MASTER SEQUENCER MACHINE 283 B 3. MASTER 6 PCI LOCAL BUS SPECIFICATION. REV.3.0 C. OPERATING RULES 289 C 1. WHEN SIGNALS ARE STABLE ..·····.:·.·.::···:·; 289 C.2. MASTER SIGNALS… 音·。·看 290 C.3. TARGET SIGNALS… 291 C.4. DATA PHASES… 292 C.5. ARBITRATION.……………………………………292 C.6. LATeNCY ······:“······· 293 C.7. DEVICE SELECTION……………,……………………………293 C 8. PARITY 垂垂垂D·垂 294 D. CLASS CODES D 1. BASE CLASS OOH...w.w...296 D 2. BASE CLASS OlH 296 D. 3. BASE CLASS O2H ·· 297 D 4. BASE CLASS O3H 297 D.5. BASE CLASS04H.………………………298 D. 6. BASE CLASS OSH 298 D.7. BASE CLASS06H...………….…………………299 D 8. BASE CLASS OZH ,300 D 9. BASE CLASS OSH .301 D.10. BASE CLASS C9H.……………………………………………….301 D.11. BASE CLASS OAH.…………………302 D 12. BASE CLASS OBH 302 D. 13. BASE CLASS OCH 303 D.14. BASE CLASS ODH….… 304 D. 15. BASE CLASS OEH 304 D. 16. BASE CLASS OFH ·····.····;····:·;:······· 304 D.17. BASE CLASS JOH.……………………………………………1305 D, 18. BASE CLASS 11H 305 E. SYSTEM TRANSACTION ORDERING E.I. PRODUCER- CONSUMER ORDERING MODEL 308 E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS 310 E.3. ORDERING OF REQUESTS........................................311 E.4. ORDERING OF DELAYED TRANSACTIONS…………312 E.5. DELAYED TRANSACTIONS AND LOCK# .317 E.6. ERROR CONDⅠ TIONS…… 318 . EXCLUSIVE ACCESSES..m.msn0..319 F.1. EXCLUSIVE ACCESSES ON PCI F 2. STARTING AN EXCLUSIVE ACCESS 321 F.3. CONTINUING AN EXCLUSIVE ACCESS 323 F 4. ACCESSING A LOCKED AGENT 324 F 5. COMPLETING AN EXCLUSIVE ACCESS 325 F. 6. COMPLETE BUS LOCK ......................................................................325 IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327 PCI LOCAL BUS SPECIFICATION, REV.3.0 CAPABILITY IDS。,0329 I. VITAL PRODUCT DATA 331 VPD FORMAT 3 I.2 COMPATIBILITY……………………… ……334 L.3. VPD DEFINITIONS 334 1.3.1. VPD Large and small resource Data Tags...... ·D垂看 334 1.3.2. VPD Example… 337 8 PCI LOCAL BUS SPECIFICATION. REV.3.0 Fiqures FIGURE -I: PCI LOCAL BUS APPLICATIONS 春D FIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM 17 FIGURE2-1: PCI PIN LIST.…………..………… 21 figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48 Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50 Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONS ADDRESS PHASE 51 FIGURE3-4: CONFIGURATION READ…………156 FIGURE3-5: BASIC READ OPERATION………………………65 FIGURE 3-6: BASIC WRITE OPERATION 66 FIGure 3-7: MASTER INITIATED TERMINATION........................ 68 FIGURE3-8: MASTER- ABORT TERMINATION…………69 Figure 3-9: RETRY. ..........................................................................................................73 FiGure 3-10: DISCONNECT WITH DATA. ........................74 FiGure 3-11: MASTER COMPLETION TERMINATION :·:····:··.·4····.··· …75 FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION ····· 76 Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION 76 FiGure 3-14: TARGET-ABORT …177 figure 3-15: BASIC ARBITRATION FIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS …94 FiGurE 3-17: DEVSEL# AsSERTION ·····:···.·:·· 110 Figure 3-1 8: IDSEL STEPPING 114 FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114 FIGURE3-20: PARITY OPERATION……… 116 FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER 125 FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126 FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE 129 FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138 FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.………………… 143 FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling 145 FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING 148 FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150 FIGURE 4-6: CLOCK WAVEFORMS 151 FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS .··4·:······.· 154 FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154 FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT ···“···:.···.····:········· 157 FIGURE4-10: CLOCK SKEW DIAGRAM………158 FIGURE 4-1: RESET TIMING 16l FIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166 FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT). 183 FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184 FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185 FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186 PCI LOCAL BUS SPECIFICATION, REV.3.0 FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187 FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88 FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V) 189 FIGURE 5-8: PCI STANDARD BRACKET ………190 FIGuRE 5-9: PCI LOW PROFILE BRACKET 191 FIGURE 5-10: PCI STANDARD RETAINER ··· 192 FIGURE5-11: IO WINDOW HEIGHT∴………………193 FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194 FIGURE 5-13: 32-BIT CONNECTOR 196 FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197 FIGURE5-15:3.3V/64-BIT CONNECTOR 198 FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199 FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES 2( 垂D ·。垂,音着垂。着音D。。着。D音着音垂。音着音 FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES….201 FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES………………………………202 FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES 203 FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204 FIGURE5-22: CONNECTOR CONTACT DETAIL………………205 FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD 208 FIGURE5-24:32- BIT PCI RISER CONNECTOR……209 FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT 210 FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR 211 FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212 FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER 215 FIGURE 6-2: COMMAND REGISTER LAYOUT 217 FIGURE6-3: STATUS REGISTER LAYOUT……………………………219 FIGURE 6-4: BIST REGISTER LAYOUT 222 FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225 FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O 225 鲁着D音看 FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228 FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231 FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233 FIGURE 6-10: MSI-X CAPABILITY STRUCTURE 238 FIGurE 6-11: MSI-X TABLE STRUCTURE 翻音。音 239 FIGurE 6-12: MSI-X PBA STRUCTURE …239 FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING ······:·················· 257 FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259 FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS 263 FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS 263 FIGURE75:TvAL(MAX) RISING EDGE………… 264 FIGURE 7-6: TVAL(MAX) FALLING EDGE · 265 FIGURE77:TVAL(MIN) AND SLEW RATE…… 265 10 【实例截图】
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