CSR8635芯片规格书

【实例截图】

【核心代码】

Contents
Ordering Information ........................................................................................................................................... 2
Contacts ..................................................................................................................................................... 2
CSR8635 Stereo ROM Solution Development Kit Ordering Information ................................................... 2
Device Details ..................................................................................................................................................... 3
CSR8635 Stereo ROM Solution Details .............................................................................................................. 4
Functional Block Diagram .................................................................................................................................. 5
1 Package Information ......................................................................................................................................... 13
1.1 Pinout Diagram ........................................................................................................................................ 13
1.2 Device Terminal Functions ....................................................................................................................... 14
1.3 Package Dimensions ............................................................................................................................... 20
1.4 PCB Design and Assembly Considerations ............................................................................................. 21
1.5 Typical Solder Reflow Profile ................................................................................................................... 21
2 Bluetooth Modem .............................................................................................................................................. 22
2.1 RF Ports ................................................................................................................................................... 22
2.1.1 BT_RF ........................................................................................................................................ 22
2.2 RF Receiver ............................................................................................................................................. 22
2.2.1 Low Noise Amplifier .................................................................................................................... 22
2.2.2 RSSI Analogue to Digital Converter ........................................................................................... 22
2.3 RF Transmitter ......................................................................................................................................... 22
2.3.1 IQ Modulator ............................................................................................................................... 22
2.3.2 Power Amplifier .......................................................................................................................... 23
2.4 Bluetooth Radio Synthesiser .................................................................................................................... 23
2.5 Baseband ................................................................................................................................................. 23
2.5.1 Burst Mode Controller ................................................................................................................. 23
2.5.2 Physical Layer Hardware Engine ............................................................................................... 23
3 Clock Generation ............................................................................................................................................... 24
3.1 Crystal ...................................................................................................................................................... 24
3.1.1 Negative Resistance Model ........................................................................................................ 25
3.1.2 Crystal Specification ................................................................................................................... 25
3.1.3 Crystal Calibration ...................................................................................................................... 25
3.2 Non-crystal Oscillator ............................................................................................................................... 26
3.2.1 XTAL_IN Impedance in Non-crystal Mode ................................................................................. 27
4 Bluetooth Stack Microcontroller ......................................................................................................................... 28
4.1 VM Accelerator ......................................................................................................................................... 28
5 Kalimba DSP ..................................................................................................................................................... 29
6 Memory Interface and Management ................................................................................................................. 30
6.1 Memory Management Unit ....................................................................................................................... 30
6.2 System RAM ............................................................................................................................................ 30
6.3 Kalimba DSP RAM ................................................................................................................................... 30
6.4 Internal ROM ............................................................................................................................................ 30
6.5 Serial Flash Interface ............................................................................................................................... 30
7 Serial Interfaces ................................................................................................................................................ 31
7.1 USB Interface ........................................................................................................................................... 31
7.2 UART Interface ........................................................................................................................................ 31
7.3 Programming and Debug Interface .......................................................................................................... 33
7.3.1 Multi-slave Operation .................................................................................................................. 33
7.4 I²C EEPROM Interface ............................................................................................................................. 34
8 Interfaces ........................................................................................................................................................... 35
8.1 Programmable I/O Ports, PIO .................................................................................................................. 35
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8.2 Analogue I/O Ports, AIO ........................................................................................................................... 35
8.3 LED Drivers .............................................................................................................................................. 35
9 Audio Interface .................................................................................................................................................. 37
9.1 Audio Input and Output ............................................................................................................................ 37
9.2 Audio Codec Interface .............................................................................................................................. 38
9.2.1 Audio Codec Block Diagram ....................................................................................................... 38
9.2.2 ADC ............................................................................................................................................ 38
9.2.3 ADC Sample Rate Selection ...................................................................................................... 38
9.2.4 ADC Audio Input Gain ................................................................................................................ 39
9.2.5 ADC Pre-amplifier and ADC Analogue Gain .............................................................................. 39
9.2.6 ADC Digital Gain ........................................................................................................................ 39
9.2.7 ADC Digital IIR Filter .................................................................................................................. 40
9.2.8 DAC ............................................................................................................................................ 40
9.2.9 DAC Sample Rate Selection ...................................................................................................... 40
9.2.10 DAC Digital Gain ........................................................................................................................ 40
9.2.11 DAC Analogue Gain ................................................................................................................... 40
9.2.12 DAC Digital FIR Filter ................................................................................................................. 41
9.2.13 Microphone Input ........................................................................................................................ 41
9.2.14 Line Input .................................................................................................................................... 42
9.2.15 Output Stage .............................................................................................................................. 42
9.2.16 Mono Operation .......................................................................................................................... 43
9.2.17 Side Tone ................................................................................................................................... 43
9.2.18 Integrated Digital IIR Filter .......................................................................................................... 45
9.3 PCM1 Interface ........................................................................................................................................ 46
9.3.1 PCM Interface Master/Slave ....................................................................................................... 46
9.3.2 Long Frame Sync ....................................................................................................................... 47
9.3.3 Short Frame Sync ....................................................................................................................... 47
9.3.4 Multi-slot Operation .................................................................................................................... 48
9.3.5 GCI Interface .............................................................................................................................. 48
9.3.6 Slots and Sample Formats ......................................................................................................... 48
9.3.7 Additional Features ..................................................................................................................... 49
9.3.8 PCM Timing Information ............................................................................................................. 49
9.3.9 PCM_CLK and PCM_SYNC Generation .................................................................................... 53
9.3.10 PCM Configuration ..................................................................................................................... 53
9.4 Digital Audio Interface (I²S) ...................................................................................................................... 53
10 Power Control and Regulation .......................................................................................................................... 57
10.1 1.8V Switch-mode Regulator ................................................................................................................... 59
10.2 1.35V Switch-mode Regulator ................................................................................................................. 60
10.3 1.8V and 1.35V Switch-mode Regulators Combined ............................................................................... 61
10.4 Bypass LDO Linear Regulator ................................................................................................................. 62
10.5 Low-voltage VDD_DIG Linear Regulator ................................................................................................. 63
10.6 Low-voltage VDD_AUX Linear Regulator ................................................................................................ 63
10.7 Low-voltage VDD_ANA Linear Regulator ................................................................................................ 63
10.8 Voltage Regulator Enable ........................................................................................................................ 63
10.9 External Regulators and Power Sequencing ........................................................................................... 63
10.10Reset, RST# ............................................................................................................................................. 63
10.10.1 Digital Pin States on Reset ......................................................................................................... 64
10.10.2 Status After Reset ...................................................................................................................... 64
10.11Automatic Reset Protection ...................................................................................................................... 64
11 Battery Charger ................................................................................................................................................. 65
11.1 Battery Charger Hardware Operating Modes ........................................................................................... 65
11.1.1 Disabled Mode ............................................................................................................................ 66
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11.1.2 Trickle Charge Mode .................................................................................................................. 66
11.1.3 Fast Charge Mode ...................................................................................................................... 66
11.1.4 Standby Mode ............................................................................................................................ 66
11.1.5 Error Mode .................................................................................................................................. 66
11.2 Battery Charger Trimming and Calibration ............................................................................................... 66
11.3 VM Battery Charger Control ..................................................................................................................... 66
11.4 Battery Charger Firmware and PS Keys .................................................................................................. 66
11.5 External Mode .......................................................................................................................................... 67
12 Example Application Schematic ........................................................................................................................ 68
13 Electrical Characteristics ................................................................................................................................... 70
13.1 Absolute Maximum Ratings ..................................................................................................................... 70
13.2 Recommended Operating Conditions ...................................................................................................... 71
13.3 Input/Output Terminal Characteristics ...................................................................................................... 72
13.3.1 Regulators: Available For External Use ...................................................................................... 72
13.3.2 Regulators: For Internal Use Only .............................................................................................. 74
13.3.3 Regulator Enable ........................................................................................................................ 75
13.3.4 Battery Charger .......................................................................................................................... 75
13.3.5 USB ............................................................................................................................................ 77
13.3.6 Stereo Codec: Analogue to Digital Converter ............................................................................. 78
13.3.7 Stereo Codec: Digital to Analogue Converter ............................................................................. 79
13.3.8 Digital .......................................................................................................................................... 80
13.3.9 LED Driver Pads ......................................................................................................................... 80
13.3.10 Auxiliary ADC ............................................................................................................................. 81
13.3.11 Auxiliary DAC ............................................................................................................................. 81
13.4 ESD Protection ......................................................................................................................................... 82
13.4.1 USB Electrostatic Discharge Immunity ....................................................................................... 82
14 Power Consumption .......................................................................................................................................... 84
15 CSR Green Semiconductor Products and RoHS Compliance .......................................................................... 87
16 Software ............................................................................................................................................................ 88
16.1 CSR8635 Stereo ROM Solution ............................................................................................................... 88
16.1.1 Advanced Multipoint Support ...................................................................................................... 89
16.1.2 A2DP Multipoint Support ............................................................................................................ 89
16.1.3 Wired Audio Mode ...................................................................................................................... 89
16.1.4 USB Modes Including USB Audio Mode .................................................................................... 89
16.1.5 Smartphone Applications (Apps) ................................................................................................ 90
16.1.6 Programmable Audio Prompts ................................................................................................... 90
16.1.7 CSR’s Intelligent Power Management ........................................................................................ 91
16.1.8 Proximity Pairing ......................................................................................................................... 91
16.1.9 Proximity Connection .................................................................................................................. 91
16.2 6th Generation 1-mic CVC ENR Technology for Hands-free and Audio Enhancements ......................... 92
16.2.1 Acoustic Echo Cancellation ........................................................................................................ 92
16.2.2 Noise Suppression with Wind Noise Reduction ......................................................................... 93
16.2.3 Non-linear Processing (NLP) ...................................................................................................... 93
16.2.4 Howling Control (HC) .................................................................................................................. 93
16.2.5 Comfort Noise Generator ........................................................................................................... 93
16.2.6 Equalisation ................................................................................................................................ 93
16.2.7 Automatic Gain Control .............................................................................................................. 93
16.2.8 Packet Loss Concealment .......................................................................................................... 93
16.2.9 Adaptive Equalisation (AEQ) ...................................................................................................... 94
16.2.10 Auxiliary Stream Mix ................................................................................................................... 94
16.2.11 Clipper ........................................................................................................................................ 94
16.2.12 Noise Dependent Volume Control .............................................................................................. 94
Production Information
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Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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CSR8635 QFN Data Sheet
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16.2.13 Input Output Gains ..................................................................................................................... 94
16.3 Music Enhancements ............................................................................................................................... 95
16.3.1 Audio Decoders .......................................................................................................................... 95
16.3.2 Configurable EQ ......................................................................................................................... 95
16.3.3 Stereo Widening (S3D) ............................................................................................................... 95
16.3.4 Volume Boost ............................................................................................................................. 96
16.4 CSR8635 Stereo ROM Solution Development Kit ................................................................................... 96
17 Tape and Reel Information ................................................................................................................................ 97
17.1 Tape Orientation ...................................................................................................................................... 97
17.2 Tape Dimensions ..................................................................................................................................... 98
17.3 Reel Information ....................................................................................................................................... 99
17.4 Moisture Sensitivity Level ......................................................................................................................... 99
18 Document References ..................................................................................................................................... 100
Terms and Definitions .............................................................................................................................................. 101
List of Figures
Figure 1.1 Device Pinout ....................................................................................................................................... 13
Figure 2.1 Simplified Circuit BT_RF ...................................................................................................................... 22
Figure 3.1 Crystal Oscillator Overview .................................................................................................................. 24
Figure 5.1 Kalimba DSP Interface to Internal Functions ....................................................................................... 29
Figure 6.1 Serial Flash Interface ........................................................................................................................... 30
Figure 7.1 Universal Asynchronous Receiver ....................................................................................................... 32
Figure 7.2 Example I²C EEPROM Connection ..................................................................................................... 34
Figure 8.1 LED Equivalent Circuit ......................................................................................................................... 36
Figure 9.1 Audio Interface ..................................................................................................................................... 37
Figure 9.2 Audio Codec Input and Output Stages ................................................................................................ 38
Figure 9.3 Audio Input Gain .................................................................................................................................. 39
Figure 9.4 Microphone Biasing ............................................................................................................................. 41
Figure 9.5 Differential Input ................................................................................................................................... 42
Figure 9.6 Single-ended Input ............................................................................................................................... 42
Figure 9.7 Speaker Output .................................................................................................................................... 43
Figure 9.8 Side Tone ............................................................................................................................................ 44
Figure 9.9 PCM Interface Master .......................................................................................................................... 46
Figure 9.10 PCM Interface Slave ............................................................................................................................ 47
Figure 9.11 Long Frame Sync (Shown with 8-bit Companded Sample) ................................................................. 47
Figure 9.12 Short Frame Sync (Shown with 16-bit Sample) ................................................................................... 47
Figure 9.13 Multi-slot Operation with 2 Slots and 8-bit Companded Samples ........................................................ 48
Figure 9.14 GCI Interface ....................................................................................................................................... 48
Figure 9.15 16-bit Slot Length and Sample Formats .............................................................................................. 49
Figure 9.16 PCM Master Timing Long Frame Sync ................................................................................................ 50
Figure 9.17 PCM Master Timing Short Frame Sync ............................................................................................... 51
Figure 9.18 PCM Slave Timing Long Frame Sync .................................................................................................. 52
Figure 9.19 PCM Slave Timing Short Frame Sync ................................................................................................. 53
Figure 9.20 Digital Audio Interface Modes .............................................................................................................. 54
Figure 9.21 Digital Audio Interface Slave Timing .................................................................................................... 55
Figure 9.22 Digital Audio Interface Master Timing .................................................................................................. 56
Figure 10.1 1.80V and 1.35V Dual-supply Switch-mode System Configuration ..................................................... 58
Figure 10.2 1.80V Parallel-supply Switch-mode System Configuration .................................................................. 59
Figure 10.3 1.8V Switch-mode Regulator Output Configuration ............................................................................. 60
Figure 10.4 1.35V Switch-mode Regulator Output Configuration ........................................................................... 61
Figure 10.5 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration ........................................... 62
Production Information
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CSR8635 QFN Data Sheet
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Figure 11.1 Battery Charger Mode-to-Mode Transition Diagram ............................................................................ 65
Figure 11.2 Battery Charger External Mode Typical Configuration ........................................................................ 67
Figure 12.1 Single Microphone and Stereo Line Input ............................................................................................ 68
Figure 12.2 Dual/Stereo Line Input ......................................................................................................................... 69
Figure 16.1 Programmable Audio Prompts in External SPI Flash .......................................................................... 90
Figure 16.2 Programmable Audio Prompts in External I²C EEPROM .................................................................... 91
Figure 16.3 1-mic CVC Block Diagram ................................................................................................................... 92
Figure 16.4 Configurable EQ GUI with Drag Points ................................................................................................ 95
Figure 16.5 Volume Boost GUI with Drag Points .................................................................................................... 96
Figure 17.1 CSR8635 QFN Tape Orientation ......................................................................................................... 97
Figure 17.2 Reel Dimensions .................................................................................................................................. 99
List of Tables
Table 3.1 Typical On-chip Capacitance Values .................................................................................................... 24
Table 3.2 Transconductance and On-chip Parasitic Capacitance ........................................................................ 25
Table 3.3 Crystal Specification ............................................................................................................................. 25
Table 3.4 External Clock Specifications ............................................................................................................... 27
Table 7.1 PS Keys for UART/PIO Multiplexing ..................................................................................................... 31
Table 7.2 Possible UART Settings ....................................................................................................................... 32
Table 7.3 Standard Baud Rates ........................................................................................................................... 33
Table 8.1 Alternative PIO Functions ..................................................................................................................... 35
Table 9.1 Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface .................................. 37
Table 9.2 ADC Audio Input Gain Rate .................................................................................................................. 39
Table 9.3 DAC Digital Gain Rate Selection .......................................................................................................... 40
Table 9.4 DAC Analogue Gain Rate Selection ..................................................................................................... 41
Table 9.5 Side Tone Gain ..................................................................................................................................... 44
Table 9.6 PCM Master Timing .............................................................................................................................. 49
Table 9.7 PCM Slave Timing ................................................................................................................................ 52
Table 9.8 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface .................................... 54
Table 9.9 Digital Audio Interface Slave Timing ..................................................................................................... 55
Table 9.10 I²S Slave Mode Timing ......................................................................................................................... 55
Table 9.11 Digital Audio Interface Master Timing ................................................................................................... 56
Table 9.12 I²S Master Mode Timing Parameters, WS and SCK as Outputs .......................................................... 56
Table 10.1 Recommended Configurations for Power Control and Regulation ....................................................... 57
Table 10.2 Pin States on Reset .............................................................................................................................. 64
Table 11.1 Battery Charger Operating Modes Determined by Battery Voltage and Current .................................. 65
Table 13.1 ESD Handling Ratings .......................................................................................................................... 82
Table 13.2 USB Electrostatic Discharge Protection Level ...................................................................................... 83
List of Equations
Equation 3.1 Negative Resistance ............................................................................................................................ 25
Equation 3.2 Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET .................................................................. 26
Equation 7.1 Baud Rate ............................................................................................................................................ 32
Equation 8.1 LED Current ......................................................................................................................................... 36
Equation 8.2 LED PAD Voltage ................................................................................................................................ 36
Equation 9.1 IIR Filter Transfer Function, H(z) ......................................................................................................... 45
Equation 9.2 IIR Filter Plus DC Blocking Transfer Function, HDC(z) ...................................................................