实例介绍
【实例截图】
【核心代码】
OpenRISC 1000
1
Architecture Manual
April 5, 2006
Table of Contents
1 ABOUT THIS MANUAL ....................................................................................................... 10
1.1
INTRODUCTION.......................................................................................................... 10
1.2
AUTHORS.................................................................................................................... 10
1.3
REVISION HISTORY ................................................................................................... 11
1.4
WORK IN PROGRESS ................................................................................................ 12
1.5
FONTS IN THIS MANUAL ........................................................................................... 12
1.6
CONVENTIONS ........................................................................................................... 13
1.7
NUMBERING ............................................................................................................... 13
2 ARCHITECTURE OVERVIEW............................................................................................. 14
2.1
FEATURES .................................................................................................................. 14
2.2
INTRODUCTION.......................................................................................................... 14
3 ADDRESSING MODES AND OPERAND CONVENTIONS................................................ 16
3.1
MEMORY ADDRESSING MODES .............................................................................. 16
3.1.1 Register Indirect with Displacement.................................................................... 16
3.1.2 PC Relative ............................................................................................................. 17
3.2
MEMORY OPERAND CONVENTIONS....................................................................... 17
3.2.1 Bit and Byte Ordering............................................................................................ 18
3.2.2 Aligned and Misaligned Accesses ....................................................................... 19
4 REGISTER SET ................................................................................................................... 20
4.1
FEATURES .................................................................................................................. 20
4.2
OVERVIEW .................................................................................................................. 20
4.3
SPECIAL-PURPOSE REGISTERS ............................................................................. 20
4.4
GENERAL-PURPOSE REGISTERS (GPRS).............................................................. 24
4.5
SUPPORT FOR CUSTOM NUMBER OF GPRS......................................................... 25
4.6
SUPERVISION REGISTER (SR)................................................................................. 25
4.7
EXCEPTION PROGRAM COUNTER REGISTERS (EPCR0 - EPCR15) ................... 27
4.8
EXCEPTION EFFECTIVE ADDRESS REGISTERS (EEAR0-EEAR15)..................... 27
4.9
EXCEPTION SUPERVISION REGISTERS
(ESR0-ESR15) .............................. 28
4.10 NEXT AND PREVIOUS PROGRAM COUNTER (NPC AND PPC)............................. 28
4.11 FLOATING POINT CONTROL STATUS REGISTER (FPCSR) .................................. 28
5 INSTRUCTION SET ............................................................................................................. 31
5.1
FEATURES .................................................................................................................. 31
5.2
OVERVIEW .................................................................................................................. 31
5.3
ORBIS32/64 ................................................................................................................. 33
6 EXCEPTION MODEL......................................................................................................... 252
6.1
INTRODUCTION........................................................................................................ 252
6.2
EXCEPTION CLASSES............................................................................................. 252
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OpenRISC 1000 Architecture Manual
April 5, 2006
6.3
EXCEPTION PROCESSING ..................................................................................... 254
6.4
FAST CONTEXT SWITCHING (OPTIONAL) ............................................................ 255
6.4.1 Changing Context in Supervisor Mode ............................................................. 255
6.4.2 Context Switch Caused by Exception ............................................................... 256
6.4.3 Accessing Other Contexts’ Registers ............................................................... 257
7 MEMORY MODEL ............................................................................................................. 258
7.1
MEMORY ................................................................................................................... 258
7.2
MEMORY ACCESS ORDERING............................................................................... 258
7.2.1 Memory Synchronize Instruction ....................................................................... 258
7.2.2 Pages Designated as Weakly-Ordered-Memory ............................................... 258
8 MEMORY MANAGEMENT ................................................................................................ 260
8.1
MMU FEATURES....................................................................................................... 260
8.2
MMU OVERVIEW ...................................................................................................... 260
8.3
MMU EXCEPTIONS................................................................................................... 262
8.4
MMU SPECIAL-PURPOSE REGISTERS.................................................................. 262
8.4.1 Data MMU Control Register (DMMUCR) ............................................................ 264
8.4.2 Data MMU Protection Register (DMMUPR)........................................................ 264
8.4.3 Instruction MMU Control Register (IMMUCR) ................................................... 265
8.4.4 Instruction MMU Protection Register (IMMUPR) .............................................. 266
8.4.5 Instruction/Data TLB Entry Invalidate Registers (xTLBEIR)............................ 267
8.4.6 Instruction/Data Translation Lookaside Buffer Way y Match Registers
(xTLBWyMR0-xTLBWyMR127) ........................................................................................ 268
8.4.7 Data Translation Lookaside Buffer Way y Translate Registers (DTLBWyTR0-
DTLBWyTR127)................................................................................................................. 270
8.4.8 Instruction Translation Lookaside Buffer Way y Translate Registers
(ITLBWyTR0-ITLBWyTR127)............................................................................................ 271
8.4.9 Instruction/Data Area Translation Buffer Match Registers (xATBMR0-
xATBMR3).......................................................................................................................... 272
8.4.10
Data Area Translation Buffer Translate Registers (DATBTR0-DATBTR3). 274
8.4.11
Instruction Area Translation Buffer Translate Registers (IATBTR0-IATBTR3)
275
8.5
ADDRESS TRANSLATION MECHANISM IN 32-BIT IMPLEMENTATIONS ............ 276
8.6
ADDRESS TRANSLATION MECHANISM IN 64-BIT IMPLEMENTATIONS ............ 280
8.7
MEMORY PROTECTION MECHANISM ................................................................... 283
8.8
PAGE TABLE ENTRY DEFINITION .......................................................................... 284
8.9
PAGE TABLE SEARCH OPERATION....................................................................... 286
8.10 PAGE HISTORY RECORDING ................................................................................. 286
8.11 PAGE TABLE UPDATES........................................................................................... 286
9 CACHE MODEL & CACHE COHERENCY ....................................................................... 288
9.1
CACHE SPECIAL-PURPOSE REGISTERS.............................................................. 288
9.1.1 Data Cache Control Register .............................................................................. 289
9.1.2 Instruction Cache Control Register ................................................................... 289
9.2
CACHE MANAGEMENT............................................................................................ 290
9.2.1 Data Cache Block Prefetch (Optional) ............................................................... 290
9.2.2 Data Cache Block Flush...................................................................................... 291
9.2.3 Data Cache Block Invalidate............................................................................... 292
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