RTL8211FS_V18.pdf

【实例简介】RTL8211FS_V18.pdf
【实例截图】

【核心代码】
说明：RTL8211FS-CG，RTL8211FS-VS-CG，RTL8211FSI-CG，RTL8211FSI-VS-CG（48PIN规格），DataSheet，真实有效，V1.8版本

Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2. FEATURES ......................................................................................................................................................................... 2
3. SYSTEM APPLICATIONS ............................................................................................................................................... 3
3.1. UTP (UTPRGMII; UTPSGMII) A PPLICATION D IAGRAM ............................................................................ 4
3.2. F IBER (FIBERRGMII) A PPLICATION D IAGRAM .................................................................................................. 4
3.3. UTP/F IBER TO RGMII (UTP/FIBER M EDIA A UTO D ETECTION RGMII) A PPLICATION D IAGRAM ..................... 5
3.4. SGMII TO RGMII (SGMIIRGMII B RIDGE M ODE ) A PPLICATION D IAGRAM ....................................................... 5
3.5. F IBER TO UTP (UTPFIBER M EDIA C ONVERTER ) A PPLICATION D IAGRAM ......................................................... 6
3.6. PTP AND S YNC E THERNET A PPLICATION D IAGRAM (RTL8211FS(I)-VS O NLY ) ........................................................ 6
4. BLOCK DIAGRAM ........................................................................................................................................................... 7
5. PIN ASSIGNMENTS ......................................................................................................................................................... 8
5.1. RTL8211FS(I) P IN A SSIGNMENTS ............................................................................................................................... 8
5.2. P ACKAGE I DENTIFICATION ........................................................................................................................................... 8
5.3. RTL8211FS(I)-VS P IN A SSIGNMENTS ........................................................................................................................ 9
5.4. P ACKAGE I DENTIFICATION ........................................................................................................................................... 9
6. PIN DESCRIPTIONS ...................................................................................................................................................... 10
6.1. T RANSCEIVER I NTERFACE .......................................................................................................................................... 10
6.2. C LOCK ....................................................................................................................................................................... 10
6.3. RGMII ....................................................................................................................................................................... 11
6.4. S ER D ES ...................................................................................................................................................................... 11
6.5. R ESET ........................................................................................................................................................................ 11
6.6. M ODE S ELECTION (H ARDWARE C ONFIGURATION ) .................................................................................................... 12
6.7. LED D EFAULT S ETTINGS ........................................................................................................................................... 12
6.8. R EGULATOR AND R EFERENCE .................................................................................................................................... 13
6.9. P OWER AND G ROUND ................................................................................................................................................ 13
6.10. M ANAGEMENT AND PTP A PPLICATION I NTERFACE ................................................................................................... 14
7. FUNCTION DESCRIPTION .......................................................................................................................................... 15
7.1. T RANSMITTER ............................................................................................................................................................ 15
7.1.1. 1000Mbps Mode ................................................................................................................................................... 15
7.1.2. 100Mbps Mode ..................................................................................................................................................... 15
7.1.3. 10Mbps Mode ....................................................................................................................................................... 15
7.2. R ECEIVER ................................................................................................................................................................... 15
7.2.1. 1000Mbps Mode ................................................................................................................................................... 15
7.2.2. 100Mbps Mode ..................................................................................................................................................... 15
7.2.3. 10Mbps Mode ....................................................................................................................................................... 15
7.3. P RECISION T IME P ROTOCOL (PTP) (RTL8211FS(I)-VS O NLY ) ................................................................................. 16
7.3.1. Synchronized PTP Clock ...................................................................................................................................... 16
7.3.2. Packet Time Stamping .......................................................................................................................................... 17
7.3.3. Time Application Interface (TAI) ......................................................................................................................... 17
7.4. S YNCHRONOUS E THERNET (S YNC -E)......................................................................................................................... 18
7.5. E NERGY E FFICIENT E THERNET (EEE) ........................................................................................................................ 18
7.6. W AKE -O N -LAN (WOL) ............................................................................................................................................ 18
7.7. I NTERRUPT ................................................................................................................................................................. 19
7.8. INTB/PMEB P IN U SAGE ........................................................................................................................................... 20
7.9. MDI I NTERFACE ........................................................................................................................................................ 20
7.10. H ARDWARE C ONFIGURATION .................................................................................................................................... 20
7.11. LED AND PHY A DDRESS /LDO C ONFIGURATION ...................................................................................................... 22
RTL8211FS(I)(-VS)
Datasheet
Integrated 10/100/1000M Ethernet Precision Transceiver vi Track ID: JATR-8275-15 Rev. 1.8
7.12. G REEN E THERNET (1000/100M BPS M ODE O NLY ) ..................................................................................................... 22
7.12.1. Cable Length Power Saving ............................................................................................................................ 22
7.12.2. Register Setting ................................................................................................................................................ 23
7.13. MAC/PHY I NTERFACE .............................................................................................................................................. 24
7.13.1. RGMII .............................................................................................................................................................. 24
7.13.2. SGMII .............................................................................................................................................................. 24
7.13.3. Management Interface ..................................................................................................................................... 24
7.13.4. Change Page .................................................................................................................................................... 25
7.13.5. Access to MDIO Manageable Device (MMD) ................................................................................................. 26
7.14. A UTO -N EGOTIATION .................................................................................................................................................. 26
7.14.1. Auto-Negotiation Priority Resolution .............................................................................................................. 29
7.14.2. Auto-Negotiation Master/Slave Resolution ...................................................................................................... 30
7.14.3. Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution ........................................................................ 30
7.15. C ROSSOVER D ETECTION AND A UTO -C ORRECTION .................................................................................................... 31
7.16. LED C ONFIGURATION ............................................................................................................................................... 32
7.16.1. Customized LED Function ............................................................................................................................... 32
7.16.2. EEE LED Function .......................................................................................................................................... 34
7.17. P OLARITY C ORRECTION ............................................................................................................................................. 35
7.18. P OWER ....................................................................................................................................................................... 35
7.19. PHY R ESET (H ARDWARE R ESET ) .............................................................................................................................. 35
8. REGISTER DESCRIPTIONS ......................................................................................................................................... 36
8.1. UTP R EGISTER M APPING AND D EFINITIONS .............................................................................................................. 36
8.2. UTP MMD R EGISTER M APPING AND D EFINITION ..................................................................................................... 37
8.3. F IBER R EGISTER M APPING AND D EFINITIONS ............................................................................................................ 37
8.4. SERDES R EGISTERS M APPING AND D EFINITIONS ..................................................................................................... 38
8.5. SERDES R EGISTERS I NDIRECT A CCESS M ETHOD ..................................................................................................... 38
8.6. R EGISTER T ABLES ...................................................................................................................................................... 39
8.6.1. BMCR (Basic Mode Control Register, Address 0x00) ......................................................................................... 39
8.6.2. BMSR (Basic Mode Status Register, Address 0x01) ............................................................................................. 40
8.6.3. PHYID1 (PHY Identifier Register 1, Address 0x02) ............................................................................................. 41
8.6.4. PHYID2 (PHY Identifier Register 2, Address 0x03) ............................................................................................. 41
8.6.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04) ............................................................................ 42
8.6.6. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) ......................................................... 42
8.6.7. ANER (Auto-Negotiation Expansion Register, Address 0x06) ............................................................................. 43
8.6.8. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07) ......................................................... 43
8.6.9. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08) ........................................................... 44
8.6.10. GBCR (1000Base-T Control Register, Address 0x09) ..................................................................................... 44
8.6.11. GBSR (1000Base-T Status Register, Address 0x0A) ........................................................................................ 45
8.6.12. MACR (MMD Access Control Register, Address 0x0D) ................................................................................. 45
8.6.13. MAADR (MMD Access Address Data Register, Address 0x0E) ...................................................................... 46
8.6.14. GBESR (1000Base-T Extended Status Register, Address 0x0F)...................................................................... 46
8.6.15. INER (Interrupt Enable Register, Page 0xa42, Address 0x12) ....................................................................... 47
8.6.16. PHYCR1 (PHY Specific Control Register 1, Page 0xa43, Address 0x18) ....................................................... 48
8.6.17. PHYCR2 (PHY Specific Control Register 2, Page 0xa43, Address 0x19) ....................................................... 49
8.6.18. PHYSR (PHY Specific Status Register, Page 0xa43, Address 0x1A) ............................................................... 50
8.6.19. INSR (Interrupt Status Register, Page 0xa43, Address 0x1D) ......................................................................... 50
8.6.20. PAGSR (Page Select Register, Page 0xa43, Address 0x1F) ............................................................................ 51
8.6.21. PHYCR3 (PHY Specific Control Register 3, Page 0xa44, Address 0x11) ....................................................... 51
8.6.22. PHYSCR (PHY Special Config Register, Page 0xa46, Address 0x14) ............................................................ 51
8.6.23. PHYSR2 (PHY Specific Status Register 2, Page 0xa4b, Address 0x10) .......................................................... 52
8.6.24. LCR (LED Control Register, Page 0xd04, Address 0x10) ............................................................................... 52
8.6.25. EEELCR (EEE LED Control Register, Page 0xd04, Address 0x11) ............................................................... 52
8.6.26. FLCR (Fiber LED Control Register, Page 0xd04, Address 0x12)................................................................... 53
8.6.27. MIICR1 (MII Control Register 1, Page 0xd08, Address 0x11) ........................................................................ 53
RTL8211FS(I)(-VS)
Datasheet
Integrated 10/100/1000M Ethernet Precision Transceiver vii Track ID: JATR-8275-15 Rev. 1.8
8.6.28. MIICR2 (MII Control Register 2, Page 0xd08, Address 0x15) ........................................................................ 53
8.6.29. INTBCR (INTB Pin Control Register, Page 0xd40, Address 0x16) ................................................................. 54
8.6.30. PTP_CTL (PTP Control Register, Page 0xe40, Address 0x10) ....................................................................... 54
8.6.31. PTP_INER (PTP Interrupt Enable Register, Page 0xe40, Address 0x11) ....................................................... 55
8.6.32. PTP_INSR (PTP Interrupt Status Register, Page 0xe40, Address 0x12) ......................................................... 55
8.6.33. SYNCE_CTL (Sync-E Control Register, Page 0xe40, Address 0x13) .............................................................. 55
8.6.34. PTP_CLK_CFG (PTP Clock Config Register, Page 0xe41, Address 0x10).................................................... 56
8.6.35. PTP_CFG_NS_LO (PTP Time Config Nano-Sec Low Register, Page 0xe41, Address 0x11) ........................ 56
8.6.36. PTP_CFG_NS_HI (PTP Time Config Nano-Sec High Register, Page 0xe41, Address 0x12) ........................ 57
8.6.37. PTP_CFG_S_LO (PTP Time Config Sec Low Register, Page 0xe41, Address 0x13) ..................................... 57
8.6.38. PTP_CFG_S_MI (PTP Time Config Sec Mid Register, Page 0xe41, Address 0x14) ...................................... 57
8.6.39. PTP_ CFG_S_HI (PTP Time Config Sec High Register, Page 0xe41, Address 0x15) .................................... 57
8.6.40. PTP_TAI_CFG (PTP Application I/F Config Register, Page 0xe42, Address 0x10) ...................................... 58
8.6.41. PTP_TRIG_CFG (PTP Trigger Config Register, Page 0xe42, Address 0x11) ............................................... 59
8.6.42. PTP_TAI_STA (PTP Application I/F Status Register, Page 0xe42, Address 0x12) ........................................ 59
8.6.43. PTP_TAI_TS_NS_LO (PTP TAI Timestamp Nano-Sec Low Register, Page 0xe42, Address 0x13) ................ 60
8.6.44. PTP_TAI_TS_NS_HI (PTP TAI Timestamp Nano-Sec High Register, Page 0xe42, Address 0x14) ............... 60
8.6.45. PTP_TAI_TS_S_LO (PTP TAI Timestamp Sec Low Register, Page 0xe42, Address 0x15) ............................ 60
8.6.46. PTP_TAI_TS_S_HI (PTP TAI Timestamp Sec High Register, Page 0xe42, Address 0x16) ............................ 60
8.6.47. PTP_TRX_TS_STA (PTP TxRx Timestamp Status Register, Page 0xe43, Address 0x10) ............................... 61
8.6.48. PTP_TRX_TS_INFO (PTP TxRx Timestamp Info Register, Page 0xe44, Address 0x10) ................................ 61
8.6.49. PTP_TRX_TS_SH (PTP TxRx Timestamp Source Hash Register, Page 0xe44, Address 0x11) ...................... 62
8.6.50. PTP_TRX_TS_SID (PTP TxRx Timestamp Seq ID Register, Page 0xe44, Address 0x12) .............................. 62
8.6.51. PTP_ TRX_TS NS_LO (PTP TxRx Timestamp Nano-Sec Low Register, Page 0xe44, Address 0x13) ............ 62
8.6.52. PTP_ TRX_TS NS_HI (PTP TxRx Timestamp Nano-Sec High Register, Page 0xe44, Address 0x14) ............ 62
8.6.53. PTP_ TRX_TS S_LO (PTP TxRx Timestamp Sec Low Register, Page 0xe44, Address 0x15) ......................... 62
8.6.54. PTP_ TRX_TS S_MI (PTP TxRx Timestamp Sec Mid Register, Page 0xe44, Address 0x16) .......................... 63
8.6.55. PTP_ TRX_TS S_HI (PTP TxRx Timestamp Sec High Register, Page 0xe44, Address 0x17) ......................... 63
8.6.56. PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) .................................................................... 63
8.6.57. PS1R (PCS Status1 Register, MMD Device 3, Address 0x01) ......................................................................... 63
8.6.58. EEECR (EEE Capability Register, MMD Device 3, Address 0x14) ................................................................ 64
8.6.59. EEEWER (EEE Wake Error Register, MMD Device 3, Address 0x16) ........................................................... 64
8.6.60. EEEAR (EEE Advertisement Register, MMD Device 7, Address 0x3c) .......................................................... 64
8.6.61. EEELPAR (EEE Link Partner Ability Register, MMD Device 7, Address 0x3d) ............................................ 64
8.6.62. Fiber BMCR (Fiber Basic Mode Control Register, Address 0x00) ................................................................. 65
8.6.63. Fiber BMSR (Basic Mode Status Register, Address 0x01) .............................................................................. 66
8.6.64. 1000Base-X ANAR (1000Base-X Auto-Negotiation Advertising Register, Address 0x04) .............................. 67
8.6.65. 1000Base-X ANLPAR (1000Base-X Auto-Negotiation Link Partner Ability Register, Address 0x05) ............ 67
8.6.66. Fiber ESR (Fiber Extended Status Register, Address 0x0F) ........................................................................... 68
8.6.67. SERDES INER (SERDES Interrupt Enable Register, Page 0xde1, Address 0x11,
Indirect Access Address 0xde12) ..................................................................................................................... 69
8.6.68. SERDES INSR (SERDES Interrupt Status Register, Page 0xde1, Address 0x12,
Indirect Access Address 0xde14) ..................................................................................................................... 70
8.6.69. SGMII ANARSEL (SGMII Auto-Negotiation Advertising Register Select, Page 0xd08, Address 0x14) ......... 70
8.6.70. SGMII ANAR (SGMII Auto-Negotiation Advertising Register, Page 0xd08, Address 0x10)........................... 71
8.6.71. SGMII ANLPAR (SGMII Auto-Negotiation Link Partner Ability Register, Page 0xdc0, Address 0x15,
Indirect Access Address 0xdc0a) ..................................................................................................................... 71
8.6.72. SERDES ANSCR(SERDES Auto-Negotiation Specific Control Register, Page 0xdc8, Address 0x14,
Indirect Access Address 0xdc88) ..................................................................................................................... 72
8.6.73. SERDES SSR (SERDES Specific Status Register, Page 0xdf0, Address 0x10,
Indirect Access Address 0xdf00) ...................................................................................................................... 72
9. SWITCHING REGULATOR .......................................................................................................................................... 73
9.1. P OWER S EQUENCE ..................................................................................................................................................... 73
RTL8211FS(I)(-VS)
Datasheet
Integrated 10/100/1000M Ethernet Precision Transceiver viii Track ID: JATR-8275-15 Rev. 1.8
10. CHARACTERISTICS...................................................................................................................................................... 75
10.1. A BSOLUTE M AXIMUM R ATINGS ................................................................................................................................ 75
10.2. R ECOMMENDED O PERATING C ONDITIONS ................................................................................................................. 75
10.3. C RYSTAL R EQUIREMENTS .......................................................................................................................................... 76
10.4. O SCILLATOR /E XTERNAL C LOCK R EQUIREMENTS ...................................................................................................... 76
10.5. DC C HARACTERISTICS ............................................................................................................................................... 77
10.6. SGMII C HARACTERISTICS ......................................................................................................................................... 78
10.6.1. SGMII Differential Transmitter Characteristics.............................................................................................. 78
10.6.2. SGMII Differential Receiver Characteristics .................................................................................................. 79
10.7. 1000B ASE -X C HARACTERISTICS ................................................................................................................................ 80
10.7.1. 1000Base-X Differential Transmitter Characteristics ..................................................................................... 80
10.7.2. 1000Base-X Differential Receiver Characteristics .......................................................................................... 81
10.8. AC C HARACTERISTICS ............................................................................................................................................... 82
10.8.1. MDC/MDIO Timing......................................................................................................................................... 82
10.8.2. RGMII Timing Modes ...................................................................................................................................... 83
10.8.3. SGMII Timing Modes ...................................................................................................................................... 86
11. MECHANICAL DIMENSIONS...................................................................................................................................... 88
11.1. M ECHANICAL D IMENSIONS N OTES ............................................................................................................................ 88
12. ORDERING INFORMATION ........................................................................................................................................ 89
List of Tables
T ABLE 1. T RANSCEIVER I NTERFACE ............................................................................................................................................ 10
T ABLE 2. C LOCK ......................................................................................................................................................................... 10
T ABLE 3. RGMII ......................................................................................................................................................................... 11
T ABLE 4. S ER D ES ........................................................................................................................................................................ 11
T ABLE 5. R ESET ........................................................................................................................................................................... 11
T ABLE 6. M ODE S ELECTION ........................................................................................................................................................ 12
T ABLE 7. LED D EFAULT S ETTINGS ............................................................................................................................................. 12
T ABLE 8. R EGULATOR AND R EFERENCE ...................................................................................................................................... 13
T ABLE 9. P OWER AND G ROUND ................................................................................................................................................... 13
T ABLE 10. M ANAGEMENT AND PTP A PPLICATION I NTERFACE ..................................................................................................... 14
T ABLE 11. CONFIG P INS VS . C ONFIGURATION R EGISTER ............................................................................................................ 20
T ABLE 12. C ONFIGURATION R EGISTER D EFINITIONS .................................................................................................................... 21
T ABLE 13. M ANAGEMENT F RAME F ORMAT .................................................................................................................................. 24
T ABLE 14. M ANAGEMENT F RAME D ESCRIPTION ........................................................................................................................... 24
T ABLE 15. 1000B ASE -T B ASE AND N EXT P AGE B IT A SSIGNMENTS .............................................................................................. 27
T ABLE 16. LED D EFAULT D EFINITIONS ........................................................................................................................................ 32
T ABLE 17. LED R EGISTER T ABLE ................................................................................................................................................. 32
T ABLE 18. LED C ONFIGURATION T ABLE 1 – M ODE A .................................................................................................................. 33
T ABLE 19. LED C ONFIGURATION T ABLE 2 – M ODE B .................................................................................................................. 33
T ABLE 20. LED C ONFIGURATION T ABLE 3 ................................................................................................................................... 34
T ABLE 21. R EGISTER A CCESS T YPES ............................................................................................................................................ 36
T ABLE 22. UTP R EGISTER M APPING AND D EFINITIONS ................................................................................................................ 36
T ABLE 23. MMD R EGISTER M APPING AND D EFINITION ............................................................................................................... 37
T ABLE 24. F IBER R EGISTERS M APPING AND D EFINITIONS ............................................................................................................ 37
T ABLE 25. SERDES R EGISTERS M APPING AND D EFINITIONS ....................................................................................................... 38
T ABLE 26. BMCR (B ASIC M ODE C ONTROL R EGISTER , A DDRESS 0 X 00) ...................................................................................... 39
T ABLE 27. BMSR (B ASIC M ODE S TATUS R EGISTER , A DDRESS 0 X 01) .......................................................................................... 40
RTL8211FS(I)(-VS)
Datasheet
Integrated 10/100/1000M Ethernet Precision Transceiver ix Track ID: JATR-8275-15 Rev. 1.8
T ABLE 28. PHYID1 (PHY I DENTIFIER R EGISTER 1, A DDRESS 0 X 02) ........................................................................................... 41
T ABLE 29. PHYID2 (PHY I DENTIFIER R EGISTER 2, A DDRESS 0 X 03) ........................................................................................... 41
T ABLE 30. ANAR (A UTO -N EGOTIATION A DVERTISING R EGISTER , A DDRESS 0 X 04) .................................................................... 42
T ABLE 31. ANLPAR (A UTO -N EGOTIATION L INK P ARTNER A BILITY R EGISTER , A DDRESS 0 X 05) ............................................... 42
T ABLE 32. ANER (A UTO -N EGOTIATION E XPANSION R EGISTER , A DDRESS 0 X 06)........................................................................ 43
T ABLE 33. ANNPTR (A UTO -N EGOTIATION N EXT P AGE T RANSMIT R EGISTER , A DDRESS 0 X 07) ................................................. 43
T ABLE 34. ANNPRR (A UTO -N EGOTIATION N EXT P AGE R ECEIVE R EGISTER , A DDRESS 0 X 08) ................................................... 44
T ABLE 35. GBCR (1000B ASE -T C ONTROL R EGISTER , A DDRESS 0 X 09) ....................................................................................... 44
T ABLE 36. GBSR (1000B ASE -T S TATUS R EGISTER , A DDRESS 0 X 0A) .......................................................................................... 45
T ABLE 37. MACR (MMD A CCESS C ONTROL R EGISTER , A DDRESS 0 X 0D) .................................................................................. 45
T ABLE 38. MAADR (MMD A CCESS A DDRESS D ATA R EGISTER , A DDRESS 0 X 0E) ...................................................................... 46
T ABLE 39. GBESR (1000B ASE -T E XTENDED S TATUS R EGISTER , A DDRESS 0 X 0F) ...................................................................... 46
T ABLE 40. INER (I NTERRUPT E NABLE R EGISTER , P AGE 0 XA 42, A DDRESS 0 X 12) ........................................................................ 47
T ABLE 41. PHYCR1 (PHY S PECIFIC C ONTROL R EGISTER 1, P AGE 0 XA 43, A DDRESS 0 X 18) ........................................................ 48
T ABLE 42. PHYCR2 (PHY S PECIFIC C ONTROL R EGISTER 2, P AGE 0 XA 43, A DDRESS 0 X 19) ........................................................ 49
T ABLE 43. PHYSR (PHY S PECIFIC S TATUS R EGISTER , P AGE 0 XA 43, A DDRESS 0 X 1A) ............................................................... 50
T ABLE 44. INSR (I NTERRUPT S TATUS R EGISTER , P AGE 0 XA 43, A DDRESS 0 X 1D) ........................................................................ 50
T ABLE 45. PAGSR (P AGE S ELECT R EGISTER , P AGE 0 XA 43, A DDRESS 0 X 1F) .............................................................................. 51
T ABLE 46. PHYSCR (PHY S PECIAL C ONFIG R EGISTER , P AGE 0 XA 46, A DDRESS 0 X 14) .............................................................. 51
T ABLE 47. PHYSR2 (PHY S PECIFIC S TATUS R EGISTER 2, P AGE 0 XA 4 B , A DDRESS 0 X 10) ........................................................... 52
T ABLE 48. LCR (LED C ONTROL R EGISTER , P AGE 0 XD 04, A DDRESS 0 X 10) ................................................................................. 52
T ABLE 49. EEELCR (EEE LED C ONTROL R EGISTER , P AGE 0 XD 04, A DDRESS 0 X 11) ................................................................. 52
T ABLE 50. FLCR (F IBER LED C ONTROL R EGISTER , P AGE 0 XD 04, A DDRESS 0 X 12)..................................................................... 53
T ABLE 51. MIICR1 (MII C ONTROL R EGISTER 1, P AGE 0 XD 08, A DDRESS 0 X 11) .......................................................................... 53
T ABLE 52. MIICR2 (MII C ONTROL R EGISTER 2, P AGE 0 XD 08, A DDRESS 0 X 15) .......................................................................... 53
T ABLE 53. INTBCR (INTB P IN C ONTROL R EGISTER , P AGE 0 XD 40, A DDRESS 0 X 16) .................................................................. 54
T ABLE 54. PTP_CTL (PTP C ONTROL R EGISTER , P AGE 0 XE 40, A DDRESS 0 X 10) ......................................................................... 54
T ABLE 55. PTP_INER (PTP I NTERRUPT E NABLE R EGISTER , P AGE 0 XE 40, A DDRESS 0 X 11) ........................................................ 55
T ABLE 56. PTP_INSR (PTP I NTERRUPT S TATUS R EGISTER , P AGE 0 XE 40, A DDRESS 0 X 12) ........................................................ 55
T ABLE 57. SYNCE_CTL (S YNC -E C ONTROL R EGISTER , P AGE 0 XE 40, A DDRESS 0 X 13) ............................................................. 55
T ABLE 58. PTP_CLK_CFG (PTP C LOCK C ONFIG R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 10) ...................................................... 56
T ABLE 59. PTP_CFG_NS_LO (PTP T IME C ONFIG N ANO -S EC L OW R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 11)........................... 56
T ABLE 60. PTP_CFG_NS_HI (PTP T IME C ONFIG N ANO -S EC H IGH R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 12) ........................... 57
T ABLE 61. PTP_CFG_S_LO (PTP T IME C ONFIG S EC L OW R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 13) ........................................ 57
T ABLE 62. PTP_CFG_S_MI (PTP T IME C ONFIG S EC M ID R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 14) .......................................... 57
T ABLE 63. PTP_S_HI (PTP T IME C ONFIG S EC H IGH R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 15) .................................................. 57
T ABLE 64. PTP_TAI_CFG (PTP A PPLICATION I/F C ONFIG R EGISTER , P AGE 0 XE 42, A DDRESS 0 X 10) ........................................ 58
T ABLE 65. PTP_TRIG_CFG (PTP T RIGGER C ONFIG R EGISTER , P AGE 0 XE 42, A DDRESS 0 X 11) .................................................. 59
T ABLE 66. PTP_TAI_STA (PTP A PPLICATION I/F S TATUS R EGISTER , P AGE 0 XE 42, A DDRESS 0 X 12) ........................................ 59
T ABLE 67. PTP_TAI_TS_NS_LO (PTP TAI T IMESTAMP N ANO -S EC L OW R EGISTER , P AGE 0 XE 42, A DDRESS 0 X 13) ................ 60
T ABLE 68. PTP_TAI_TS_NS_HI (PTP TAI T IMESTAMP N ANO -S EC H IGH R EGISTER , P AGE 0 XE 42, A DDRESS 0 X 14) ................ 60
T ABLE 69. PTP_S_LO (PTP T IME C ONFIG S EC L OW R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 13) .................................................. 60
T ABLE 70. PTP_S_MI (PTP T IME C ONFIG S EC M ID R EGISTER , P AGE 0 XE 41, A DDRESS 0 X 14) ................................................... 60
T ABLE 71. PTP_TRX_TS_STA (PTP T X R X T IMESTAMP S TATUS R EGISTER , P AGE 0 XE 43, A DDRESS 0 X 10) .............................. 61
T ABLE 72. PTP_TRX_TS_INFO (PTP T X R X T IMESTAMP I NFO R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 10) ................................. 61
T ABLE 73. PTP_TRX_TS_SH (PTP T X R X T IMESTAMP S OURCE H ASH R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 11) ...................... 62
T ABLE 74. PTP_TRX_TS_SID (PTP T X R X T IMESTAMP S EQ ID R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 12) ................................ 62
T ABLE 75. PTP_ TRX_TS NS_LO (PTP T X R X T IMESTAMP N ANO -S EC L OW R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 13) ............ 62
T ABLE 76. PTP_ TRX_TS NS_HI (PTP T X R X T IMESTAMP N ANO -S EC H IGH R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 14) ............ 62
T ABLE 77. PTP_ TRX_TS S_LO (PTP T X R X T IMESTAMP S EC L OW R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 15) .......................... 62
T ABLE 78. PTP_ TRX_TS S_MID (PTP T X R X T IMESTAMP S EC M ID R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 16) ........................ 63
T ABLE 79. PTP_ TRX_TS S_LO (PTP T X R X T IMESTAMP S EC H IGH R EGISTER , P AGE 0 XE 44, A DDRESS 0 X 17) ......................... 63
T ABLE 80. PC1R (PCS C ONTROL 1 R EGISTER , MMD D EVICE 3, A DDRESS 0 X 00) ....................................................................... 63
T ABLE 81. PS1R (PCS S TATUS 1 R EGISTER , MMD D EVICE 3, A DDRESS 0 X 01) ........................................................................... 63
T ABLE 82. EEECR (EEE C APABILITY R EGISTER , MMD D EVICE 3, A DDRESS 0 X 14) ................................................................... 64
RTL8211FS(I)(-VS)
Datasheet
Integrated 10/100/1000M Ethernet Precision Transceiver x Track ID: JATR-8275-15 Rev. 1.8
T ABLE 83. EEEWER (EEE W AKE E RROR R EGISTER , MMD D EVICE 3, A DDRESS 0 X 16) ............................................................. 64
T ABLE 84. EEEAR (EEE A DVERTISEMENT R EGISTER , MMD D EVICE 7, A DDRESS 0 X 3 C ) ........................................................... 64
T ABLE 85. EEELPAR (EEE L INK P ARTNER A BILITY R EGISTER , MMD D EVICE 7, A DDRESS 0 X 3 D ) ........................................... 64
T ABLE 86. F IBER BMCR (F IBER B ASIC M ODE C ONTROL R EGISTER , A DDRESS 0 X 00) .................................................................. 65
T ABLE 87. F IBER BMSR (F IBER B ASIC M ODE S TATUS R EGISTER , A DDRESS 0 X 01) ..................................................................... 66
T ABLE 88. 1000B ASE -X ANAR (A UTO -N EGOTIATION A DVERTISING R EGISTER , A DDRESS 0 X 04) .............................................. 67
T ABLE 89. 1000B ASE -X ANLPAR (A UTO -N EGOTIATION L INK P ARTNER A BILITY R EGISTER , A DDRESS 0 X 05).......................... 67
T ABLE 90. F IBER ESR (F IBER E XTENDED S TATUS R EGISTER , A DDRESS 0 X 0F) ............................................................................ 68
T ABLE 91. SERDES INER (SERDES I NTERRUPT E NABLE R EGISTER , P AGE 0 XDE 1, A DDRESS 0 X 11) ......................................... 69
T ABLE 92. SERDES INSR (SERDES I NTERRUPT S TATUS R EGISTER , P AGE 0 XDE 1, A DDRESS 0 X 12) ......................................... 70
T ABLE 93. SGMII ANARSEL (SGMII A UTO -N EGOTIATION A DVERTISING R EGISTER S ELECT , P AGE 0 XD 08, A DDRESS 0 X 14) .. 70
T ABLE 94. SGMII ANAR (SGMII A UTO -N EGOTIATION A DVERTISING R EGISTER , P AGE 0 XD 08, A DDRESS 0 X 10)...................... 71
T ABLE 95. SGMII ANLPAR (SGMII A UTO -N EGOTIATION L INK P ARTNER A BILITY R EGISTER , P AGE 0 XDC 0, A DDRESS 0 X 15) . 71
T ABLE 96. SERDES ANSCR(SERDES A UTO -N EGOTIATION S PECIFIC C ONTROL R EGISTER , P AGE 0 XDC 8, A DDRESS 0 X 14) ..... 72
T ABLE 97. SERDES SSR (SERDES S PECIFIC S TATUS R EGISTER , P AGE 0 XDF 0, A DDRESS 0 X 10) ............................................... 72
T ABLE 98. P OWER S EQUENCE P ARAMETERS ................................................................................................................................. 74
T ABLE 99. A BSOLUTE M AXIMUM R ATINGS .................................................................................................................................. 75
T ABLE 100. R ECOMMENDED O PERATING C ONDITIONS ................................................................................................................. 75
T ABLE 101. C RYSTAL R EQUIREMENTS .......................................................................................................................................... 76
T ABLE 102. O SCILLATOR /E XTERNAL C LOCK R EQUIREMENTS ...................................................................................................... 76
T ABLE 103. DC C HARACTERISTICS ............................................................................................................................................... 77
T ABLE 104. SGMII D IFFERENTIAL T RANSMITTER C HARACTERISTICS .......................................................................................... 78
T ABLE 105. SGMII D IFFERENTIAL R ECEIVER C HARACTERISTICS ................................................................................................ 79
T ABLE 106. 1000B ASE -X D IFFERENTIAL T RANSMITTER C HARACTERISTICS ................................................................................ 80
T ABLE 107. 1000B ASE -X D IFFERENTIAL R ECEIVER C HARACTERISTICS ....................................................................................... 81
T ABLE 108. MDC/MDIO M ANAGEMENT T IMING P ARAMETERS .................................................................................................. 82
T ABLE 109. RGMII T IMING P ARAMETERS .................................................................................................................................... 85
T ABLE 110. D IFFERENTIAL T RANSMITTER O UTPUT AC T IMING ................................................................................................... 87
T ABLE 111. D IFFERENTIAL R ECEIVER I NPUT AC T IMING ............................................................................................................. 87
T ABLE 112. O RDERING I NFORMATION .......................................................................................................................................... 89
RTL8211FS(I)(-VS)
Datasheet
Integrated 10/100/1000M Ethernet Precision Transceiver xi Track ID: JATR-8275-15 Rev. 1.8
List of Figures
F IGURE 1. UTP (UTPRGMII; UTPSGMII) A PPLICATION D IAGRAM ............................................................................. 4
F IGURE 2. F IBER (FIBERRGMII) A PPLICATION D IAGRAM ................................................................................................... 4
F IGURE 3. UTP/F IBER TO RGMII (UTP/FIBER M EDIA A UTO D ETECTION RGMII) A PPLICATION D IAGRAM ....................... 5
F IGURE 4. SGMII TO RGMII (SGMIIRGMII B RIDGE M ODE ) A PPLICATION D IAGRAM ........................................................ 5
F IGURE 5. F IBER TO UTP (UTPFIBER M EDIA C ONVERTER ) A PPLICATION D IAGRAM .......................................................... 6
F IGURE 6. PTP AND S YNC E THERNET A PPLICATION D IAGRAM ..................................................................................................... 6
F IGURE 7. B LOCK D IAGRAM .......................................................................................................................................................... 7
F IGURE 8. RTL8211FS(I) P IN A SSIGNMENTS (48-P IN QFN) ......................................................................................................... 8
F IGURE 9. RTL8211FS(I)-VS P IN A SSIGNMENTS (48-P IN QFN) .................................................................................................. 9
F IGURE 10. LED AND PHY A DDRESS /LDO C ONFIGURATION ....................................................................................................... 22
F IGURE 11. MDC/MDIO R EAD T IMING ........................................................................................................................................ 25
F IGURE 12. MDC/MDIO W RITE T IMING ...................................................................................................................................... 25
F IGURE 13. EEE LED B EHAVIOR .................................................................................................................................................. 34
F IGURE 14. PHY R ESET T IMING ................................................................................................................................................... 35
F IGURE 15. P OWER S EQUENCE ...................................................................................................................................................... 73
F IGURE 16. SGMII D IFFERENTIAL T RANSMITTER E YE D IAGRAM ................................................................................................. 78
F IGURE 17. SGMII D IFFERENTIAL R ECEIVER E YE D IAGRAM ....................................................................................................... 79
F IGURE 18. 1000B ASE -X D IFFERENTIAL T RANSMITTER E YE D IAGRAM ....................................................................................... 80
F IGURE 19. 1000B ASE -X D IFFERENTIAL R ECEIVER E YE D IAGRAM .............................................................................................. 81
F IGURE 20. MDC/MDIO S ETUP , H OLD T IME , AND V ALID FROM MDC R ISING E DGE T IME D EFINITIONS .................................... 82
F IGURE 21. MDC/MDIO M ANAGEMENT T IMING P ARAMETERS ................................................................................................... 82
F IGURE 22. RGMII T IMING M ODES (F OR TXC) ........................................................................................................................... 83
F IGURE 23. RGMII T IMING M ODES (F OR RXC) ........................................................................................................................... 84
F IGURE 24. SGMII T IMING M ODES ............................................................................................................................................... 86