IMX214软件应用手册与寄存器配置

【实例简介】IMX214软件应用手册与寄存器配置

IMX214是具有正方形像素阵列的对角5.876（类型1/3.06）13兆像素CMOS有源像素型堆叠图像传感器。它采用Exmore RSTM技术，通过列并行ADC电路实现高速图像采集和高灵敏度、低噪声图像。

【核心代码】

Preliminary
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Index
REVISION HISTORY.............................................................................................................. 2
INDEX ..................................................................................................................................... 3
TABLE INDEX ........................................................................................................................ 8
FIGURE INDEX ..................................................................................................................... 11
1. SYSTEM OUTLINE ....................................................................................................... 15
2. CONTROL REGISTER SETTINGS BY SERIAL COMMUNICATION ......................... 15
2.1. 2- WIRE SERIAL COMMUNICATION OPERATION SPECIFICATIONS ................................... 15
2.2. C OMMUNICATION PROTOCOL .................................................................................... 16
2.3. D EFAULT CCI SLAVE ADDRESS CONFIGURATION ....................................................... 17
2.3.1. Change slave address after power ON .......................................................... 17
2.3.2. Second CCI slave address for synchronous dual sensor operation .............. 18
2.4. S PECIFICATION OF COMMUNICATION BUS STATE ........................................................ 18
2.4.1. Idle state ......................................................................................................... 18
2.4.2. Issue “Start condition” ..................................................................................... 18
2.4.3. Issue “Stop condition” ..................................................................................... 18
2.4.4. Issue “Repeated start condition” .................................................................... 19
2.4.5. Issue acknowledge/negative acknowledge .................................................... 19
2.5. R EAD / WRITE OPERATION OF 2- WIRE SERIAL COMMUNICATION ................................... 20
2.5.1. CCI single read from random location ............................................................ 20
2.5.2. CCI single read from current location ............................................................. 21
2.5.3. CCI sequential read starting from random location ........................................ 22
2.5.4. CCI sequential read starting from current location ......................................... 22
2.5.5. CCI single write to random location ................................................................ 23
2.5.6. CCI sequential write starting from random location ....................................... 24
2.6. 2- WIRE SERIAL COMMUNICATION REGISTER UPDATE TIMING ....................................... 24
2.7. G ROUPED PARAMETER HOLD FUNCTION ................................................................... 25
3. IMAGE SIGNAL INTERFACE ...................................................................................... 27
3.1. MIPI TRANSMITTER .................................................................................................. 27
3.1.1. CSI lane mode ............................................................................................... 27
3.1.2. CSI data format ............................................................................................... 28
3.1.3. CSI-2 bus ........................................................................................................ 28
3.1.3.1. Comp6 ........................................................................................................... 28
Preliminary
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3.1.3.2. Comp8/RAW8 ............................................................................................... 29
3.1.3.3. RAW10 .......................................................................................................... 30
3.1.4. Global timing setting ....................................................................................... 31
3.1.5. CLK mode during V-blank .............................................................................. 33
4. IMAGE READOUT OPERATION ................................................................................. 35
4.1. P HYSICAL ALIGNMENT OF IMAGING PIXEL ARRAY ....................................................... 35
4.2. I MAGING AREA DETERMINATION ................................................................................ 36
4.3. C OLOR CODING AND ORDER OF READING IMAGE DATA ............................................... 36
4.4. R EADOUT START POSITION ....................................................................................... 37
4.5. F RAME STRUCTURE ................................................................................................. 38
4.5.1. Registers that determine frame size ............................................................... 40
4.6. O UTPUT IMAGE FORMAT ........................................................................................... 40
4.6.1. STATS data control ......................................................................................... 41
4.6.2. Contents of packet header ............................................................................. 42
4.6.3. Data type ........................................................................................................ 43
4.6.4. Embedded data line control ............................................................................ 43
4.6.5. Short packet & long packet............................................................................. 45
5. OPERATION MODE SETTING..................................................................................... 46
5.1. C LOCK GENERATION AND PLL ................................................................................. 46
5.1.1. Clock system diagram .................................................................................... 46
5.1.2. Supplemental description of operation clocks ................................................ 48
5.1.2.1. VTCK, OPCK: PLL output(PLL single mode) ........................................... 48
5.1.2.2. VTCK, OPCK: PLL output (PLL dual mode) ............................................. 48
5.1.2.3. Clock frequency configuration examples (PLL single mode) ................ 49
5.1.3. VTPXCK Clock ............................................................................................... 49
5.1.4. OPPXCK Clock ............................................................................................... 50
5.2. D ESCRIPTION OF MODE OPERATION .......................................................................... 51
5.2.1. Image size of mode ........................................................................................ 51
5.2.2. HDR mode settings ........................................................................................ 52
5.2.3. Binning mode settings .................................................................................... 52
5.2.4. Image size related functions ........................................................................... 53
5.3. F RAME RATE CALCULATION FORMULA ...................................................................... 55
5.4. E LECTRONIC SHUTTER AND INTEGRATION TIME SETTINGS .......................................... 55
5.4.1. Registers related to integration time (electronic shutter setting) .................... 55
Preliminary
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5.4.2. Integration time calculation ............................................................................. 55
5.5. O PTICAL BLACK LEVEL CLAMP ................................................................................. 57
5.5.1. Default setting (normal usage) ....................................................................... 57
5.5.2. Test mode setting ........................................................................................... 57
5.6. G AIN SETTING .......................................................................................................... 57
5.6.1. Analog gain settings ....................................................................................... 57
5.6.2. Digital gain settings ........................................................................................ 62
5.6.3. Change in output pixel level depending on binning mode ............................. 64
5.7. I MAGE COMPENSATION FUNCTION SETTING ............................................................... 64
5.7.1. Defect pixel correction .................................................................................... 64
5.7.1.1. Static Defect Correction ................................................................................ 64
5.7.1.2. Dynamic Defect Correction ........................................................................... 65
5.7.2. Chroma noise reduction (CNR) ...................................................................... 67
5.7.3. Luminance noise reduction (LNR) .................................................................. 67
6. POWER ON/OFF SEQUENCE ..................................................................................... 68
6.1. P OWER ON SEQUENCE ............................................................................................ 68
6.1.1. Power ON reset .............................................................................................. 68
6.1.2. Power ON sequence ...................................................................................... 68
6.1.2.1. Start up sequence with 2-wire serial communication ............................. 68
6.1.3. Constraints of XCLR ....................................................................................... 71
6.2. P OWER DOWN SEQUENCE ........................................................................................ 71
6.2.1. Power down sequence with 2-wire serial communication.............................. 71
6.2.2. Constraints of XCLR ....................................................................................... 73
7. MODE TRANSITION SEQUENCE AND REGISTER UPDATE TIMING ..................... 76
7.1. P OWER ON SEQUENCE (SW STANDBY TO STREAMING ) ............................................. 76
7.1.1. Start streaming sequence with 2 wire serial communication ......................... 76
7.1.2. Regular image output sequence .................................................................... 77
7.2. M ODE TRANSITION ................................................................................................... 78
7.2.1. Change sequence of corrupted frame related registers................................. 78
7.2.2. Mode transition sequence for avoiding corrupted frame ................................ 79
7.2.3. Software standby mode transition .................................................................. 80
7.2.4. Fast software standby mode transition .......................................................... 81
7.2.5. Normal mode transition .................................................................................. 83
7.2.6. Fast mode transition ....................................................................................... 84
Preliminary
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7.3. A UTOMATIC EXPOSURE (AE) .................................................................................... 85
7.3.1. Integration time change sequence ................................................................. 85
7.3.2. Gain change sequence ................................................................................... 86
7.3.3. Auto exposure bracketing (AEB) .................................................................... 90
8. SETTINGS RELATED TO HDR MODE PICTURE QUALITY ...................................... 96
8.1. I NTEGRATION TIME AND GAIN SETTING ...................................................................... 96
8.2. D EFECT PIXEL CORRECTION (DPC) .......................................................................... 98
8.3. C HROMA NOISE REDUCTION (CNR) .......................................................................... 98
8.3.1. Control registers for CNR ............................................................................... 99
8.3.2. Operation sequence of CNR ........................................................................ 100
8.3.3. Tuning of CNR .............................................................................................. 102
8.4. L UMINANCE N OISE R EDUCTION (LNR) ................................................................... 102
8.4.1. Control registers for LNR .............................................................................. 103
8.4.2. About tuning of LNR ..................................................................................... 104
8.5. L ENS S HADING C ORRECTION (LSC)....................................................................... 104
8.5.1. LSC control registers .................................................................................... 105
8.5.2. Operation sequence of LSC ......................................................................... 106
8.5.3. Details of LSC system .................................................................................. 106
8.6. STATS .................................................................................................................. 109
8.6.1. Outline of STATS operation ......................................................................... 109
8.6.2. Control registers for STATS ........................................................................... 110
8.6.3. Operation sequence ...................................................................................... 110
8.6.4. Details of STATS ............................................................................................ 111
8.6.4.1. About detection area ................................................................................. 111
8.6.4.2. STATS DATA output (MIPI) ......................................................................... 112
8.6.4.3. STATS data output (I2C) ............................................................................. 115
8.6.4.4. Issues on communication of STATS data using I2C and
countermeasure ........................................................................................................... 117
8.7. A DAPTIVE TONE CURVE REPRODUCTION (ATR) ........................................................ 118
8.7.1. ATR control registers ..................................................................................... 119
8.7.2. Operation sequence of ATR ......................................................................... 120
8.7.3. Details of ATR ............................................................................................... 123
9. MISCELLANEOUS FUNCTION ................................................................................. 124
9.1. T HERMAL METER ................................................................................................... 124
Preliminary
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9.1.1. Thermal meter related registers ................................................................... 124
9.1.2. Thermal meter operation sequence ............................................................. 125
9.1.3. Acquisition of higher accuracy temperature ................................................. 126
9.2. T EST PATTERN OUTPUT ( TYPES OF TEST PATTERNS ) ................................................ 126
9.2.1. Types of test patterns ................................................................................... 126
9.3. L ONG EXPOSURE ................................................................................................... 128
9.4. F LASH LIGHT CONTROL SEQUENCE ......................................................................... 129
9.5. O NE TIME PROGRAMMABLE (OTP) MEMORY ........................................................... 131
10. REGISTER MAP ......................................................................................................... 131
APPENDIX ......................................................................................................................... 132
A-1. E MBEDDED DATA LINES .......................................................................................... 132
Preliminary
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Table index
Table 2-1 Description of 2-wire serial communication pins ........................................ 16
Table 2-2 Specifications of register address map for 2-wire serial communication ... 16
Table 2-3 R/W bit ........................................................................................................ 17
Table 2-4 CCI slave address control register ............................................................. 17
Table 2-5 Operations supported by 2-wire serial communication .............................. 20
Table 2-6 Grouped parameter hold function ............................................................... 25
Table 3-1 CSI lane mode register ............................................................................... 27
Table 3-2 MIPI transmitter .......................................................................................... 27
Table 3-3 CSI data format registers............................................................................ 28
Table 3-4 Packet size constraint for RAW6 ................................................................ 28
Table 3-5 Packet size constraints for RAW8 packet .................................................. 29
Table 3-6 Packet size constraint for RAW10 packets ................................................ 30
Table 3-7 Global timing setting ................................................................................... 32
Table 3-8 CLK mode setting register during Frame Blanking .................................... 33
Table 4-1 Imaging area determining registers ............................................................ 36
Table 4-2 Vertical flip and horizontal mirror ................................................................ 37
Table 4-3 Registers that determine frame size .......................................................... 40
Table 4-4 STATS data output control .......................................................................... 41
Table 4-5 Data Identifier ............................................................................................. 42
Table 4-6 Image pixel area and data type .................................................................. 43
Table 4-7 Embedded data line control ........................................................................ 43
Table 4-8 Embedded data line tag.............................................................................. 44
Table 5-1 PLL pre divider & multiplier setting (PLL single mode) .............................. 47
Table 5-2 PLL pre divider & multiplier setting (PLL dual mode) ................................. 47
Table 5-3 PLL mode select ......................................................................................... 48
Table 5-4 PLL frequency table .................................................................................... 49
Table 5-5 VTPXCK divider setting .............................................................................. 50
Table 5-6 OPPXCK divider setting ............................................................................. 50
Table 5-7 OPPXCK clock division ratio ...................................................................... 51
Table 5-8 Modes and image sizes .............................................................................. 52
Table 5-9 HDR mode setting (when ATR is used) ...................................................... 52
Table 5-10 Binning mode settings .............................................................................. 52
Table 5-11 Electronic shutter setting register ............................................................. 55
Table 5-12 Integration time setting register ................................................................ 56
Preliminary
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Table 5-13 Integration time setting ............................................................................. 56
Table 5-14 Optical black level clamp related registers and descriptions ................... 57
Table 5-15 Variables of analog gain settings .............................................................. 58
Table 5-16 Analog gain setting reference [0 to 349] .................................................. 59
Table 5-17 Analog gain setting reference [350 to 480] .............................................. 61
Table 5-18 Digital gain setting .................................................................................... 62
Table 5-19 Digital gain setting reference .................................................................... 63
Table 5-20 Output pixel level according to binning modes ........................................ 64
Table 5-21 Binning mode determining registers ......................................................... 64
Table 5-22 Defect correction register ......................................................................... 66
Table 6-1 Start up sequence timing constraints (2-wire serial communication mode
with external reset) ................................................................................................. 69
Table 6-2 Start up sequence timing constraints (2-wire serial communication mode
with power ON reset) ............................................................................................. 70
Table 6-3 Power down sequence timing constraints (2-wire serial communication
mode with external reset) ...................................................................................... 72
Table 6-4 Power down sequence timing constraints (2-wire serial communication
mode with power ON reset) ................................................................................... 73
Table 7-1 Initialization sequence with XCLR .............................................................. 76
Table 7-2 Initialization sequence with power ON reset .............................................. 77
Table 7-3 List of corrupted frame causing registers ................................................... 78
Table 7-4 List of available mode transitions (possibility of occurrence of corrupt
frames, and other precautions) .............................................................................. 80
Table 7-5 SW standby related register ....................................................................... 81
Table 7-6 Fast SW standby related registers ............................................................. 82
Table 7-7 Normal mode transition related register ..................................................... 84
Table 7-8 Fast mode transition related register .......................................................... 85
Table 7-9 Integration time setting register .................................................................. 86
Table 7-10 Gain setting register ................................................................................. 87
Table 7-11 Register for enabling change of both exposure time and gain settings for
every frame ............................................................................................................ 90
Table 7-12 AE bracketing related registers ................................................................ 91
Table 8-1 Integration time control and analogue gain control for HDR mode ............ 97
Table 8-2 Analogue gain control ................................................................................. 98
Table 8-3 CNR setting register ................................................................................... 99
Table 8-4 LNR setting register .................................................................................. 103
Preliminary
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Table 8-5 LSC setting register .................................................................................. 105
Table 8-6 STATS related registers ............................................................................. 110
Table 8-7 Luminance data address (RG_STATSMODE=0 : 16*16) ......................... 115
Table 8-8 Luminance data address (RG_STATSMODE=1 : 8*8) ............................. 116
Table 8-9 Luminance data address (RG_STATSMODE=2 : 4*4) ............................. 116
Table 8-10 Luminance data address (RG_STATSMODE=3 : 1*1) ........................... 117
Table 8-11 Comparison of Fixed Tone Curve Mode with ATR Mode ........................ 118
Table 8-12 ATR control registers ............................................................................... 119
Table 8-13 ATR tone curve control at mode transition ............................................. 122
Table 9-1 Thermal meter register setting ................................................................. 124
Table 9-2 Thermal meter working in standby ........................................................... 125
Table 9-3 Thermal meter working in streaming ........................................................ 126
Table 9-4 Test pattern related registers and description .......................................... 126
Table 9-5 Long exposure mode related registers ..................................................... 128
Table 9-6 Set for long exposure ............................................................................... 128
Table 9-7 Long exposure time related registers ....................................................... 129
Table 9-8 Flash light control setting register............................................................. 129
Table 10-1 EBD LINE0 ............................................................................................. 132
Table 10-2 EBD LINE1 ............................................................................................. 136
Table 10-3 EBD LINE2 ............................................................................................. 140
Table 10-4 EBD LINE3 ............................................................................................. 144
Preliminary
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Figure index
Figure 1-1 System block diagram ............................................................................... 15
Figure 2-1 2-wire serial communication ..................................................................... 15
Figure 2-2 2-wire serial communication protocol ....................................................... 16
Figure 2-3 CCI (I2C) Slave address ........................................................................... 17
Figure 2-4 Start condition ........................................................................................... 18
Figure 2-5 Stop condition ........................................................................................... 19
Figure 2-6 Repeated start condition ........................................................................... 19
Figure 2-7 Acknowledge and negative acknowledge................................................. 19
Figure 2-8 CCI single read from random location ...................................................... 21
Figure 2-9 CCI single read from current location ....................................................... 22
Figure 2-10 CCI sequential read starting from random location ................................ 22
Figure 2-11 CCI sequential read starting from current location ................................. 23
Figure 2-12 CCI single write to random location ........................................................ 23
Figure 2-13 CCI sequential write starting from random location ................................ 24
Figure 2-14 2-wire serial communication register update timing diagram ................. 24
Figure 2-15 Grouped parameter hold function timing diagram .................................. 25
Figure 3-1 RAW6 transmission................................................................................... 28
Figure 3-2 RAW6 Data transmission on CSI-2 bus bitwise illustration ...................... 29
Figure 3-3 RAW6 format ............................................................................................. 29
Figure 3-4 RAW8 transmission................................................................................... 30
Figure 3-5 RAW8 data transmission on CSI-2 bus bitwise illustration ....................... 30
Figure 3-6 RAW8 frame format .................................................................................. 30
Figure 3-7 RAW10 transmission................................................................................. 31
Figure 3-8 RAW10 data transmission on CSI-2 bus bitwise illustration..................... 31
Figure 3-9 RAW10 frame format ................................................................................ 31
Figure 3-10 CLK mode during Frame Blanking (CLBLANKSTOP=0) ....................... 34
Figure 3-11 CLK mode during Frame Blanking (CLBLANKSTOP=1) ........................ 34
Figure 4-1 Physical alignment of imaging pixel array ................................................ 35
Figure 4-2 Color coding alignment ............................................................................. 36
Figure 4-3 Readout start position ............................................................................... 37
Figure 4-4 Read out image for each combination of flip and mirror .......................... 38
Figure 4-5 4-lane/2-lane frame format of serial image output 1 ................................. 39
Figure 4-6 4Lane/2Lane frame format of serial image output 2................................. 39
Figure 4-7 4-lane/2-lane frame format of serial image output 3 ................................. 40
Preliminary
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Figure 4-8 Full pixel output mode data structure ....................................................... 41
Figure 4-9 Configuration of Data ID ........................................................................... 42
Figure 4-10 Embedded data lines alignment in COMP6 mode ................................. 43
Figure 4-11 Embedded data lines alignment in RAW8/COMP8 mode ...................... 44
Figure 4-12 Embedded data lines alignment in RAW10 mode .................................. 44
Figure 4-13 Short packets & long packets ................................................................. 45
Figure 5-1 Clock system diagram (PLL single mode) ................................................ 46
Figure 5-2 Clock system diagram (PLL dual mode) ................................................... 47
Figure 5-3 Image size parameter definition ................................................................ 51
Figure 5-4 Image size related functions ..................................................................... 54
Figure 5-5 Dynamic Defect Correction model figure .................................................. 65
Figure 5-6 Defect correction flow chart ...................................................................... 66
Figure 6-1 Start up sequence with 2-wire serial communication (external reset) ...... 68
Figure 6-2 Start up sequence with 2-wire serial communication (power ON reset) .. 70
Figure 6-3 Constrains of XCLR in start up sequence ................................................ 71
Figure 6-4 Power down sequence with 2-wire serial communication (external reset)72
Figure 6-5 Power down sequence with 2-wire serial communication (power ON
reset) ...................................................................................................................... 73
Figure 6-6 Constraints of XCKR in power down sequence ....................................... 74
Figure 6-7 Software standby transition pattern 1 ....................................................... 74
Figure 6-8 Software standby transition pattern 2 ....................................................... 75
Figure 6-9 Software standby transition pattern 3 (Fast SW standby) ........................ 75
Figure 7-1 Start streaming sequence with 2-wire serial communication (external
reset) ...................................................................................................................... 76
Figure 7-2 Start streaming sequence with 2-wire serial communication (power ON
reset) ...................................................................................................................... 77
Figure 7-3 Regular image output ................................................................................ 78
Figure 7-4 Vertical direction mode change sequence ................................................ 79
Figure 7-5 SW standby mode transition (available for with/without clock change) ... 81
Figure 7-6 Fast SW standby mode transition ............................................................. 82
Figure 7-7 Normal mode transition (without clock change) ....................................... 83
Figure 7-8 Fast mode transition ................................................................................. 84
Figure 7-9 Integration time change sequence ........................................................... 85
Figure 7-10 Gain change sequence (without CIT change) ........................................ 87
Figure 7-11 Gain change sequence (With CIT change) ............................................. 88
Figure 7-12 Gain change sequence (With CIT change) ............................................ 89
Preliminary
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Figure 7-13 Gain change sequence (With CIT change) ............................................ 90
Figure 7-14 AE bracketing - without use of LUT ........................................................ 91
Figure 7-15 AE bracketing - with use of LUT ............................................................. 91
Figure 7-16 AE bracketing sequence timing chart (example of single AEB) ............. 93
Figure 7-17 AE bracketing sequence flow chart ........................................................ 94
Figure 7-18 AE bracketing sequence (example of 2-repeat mode) ........................... 94
Figure 7-19 AE bracketing sequence (example of 2-repeat mode) ........................... 95
Figure 8-1 IMX214 HDR data flow ............................................................................. 96
Figure 8-2 Effect image CNR (LNR is OFF) ............................................................... 99
Figure 8-3 CNR operation procedure ....................................................................... 100
Figure 8-4 CNR sequence ........................................................................................ 101
Figure 8-5 CNR in mode change as snapshot mode ............................................... 102
Figure 8-6 Combination in CNR mode transition ..................................................... 102
Figure 8-7 Effect image of LNR (CNR is set to minimum) ....................................... 103
Figure 8-8 LNR Operation Procedure ...................................................................... 104
Figure 8-9 LSC abstract block diagram .................................................................... 105
Figure 8-10 LSC Operation Procedure .................................................................... 106
Figure 8-11 Knot point information setting and reflection timing .............................. 106
Figure 8-12 LSC schematic block diagram .............................................................. 107
Figure 8-13 Location of knot points 9x7 ................................................................... 107
Figure 8-14 Knot point DATA structure (u2.8) .......................................................... 108
Figure 8-15 Lens Shading Correction - Method2 ..................................................... 108
Figure 8-16 STATS data out flow chart ..................................................................... 110
Figure 8-17 Target area of STATS detection area ..................................................... 111
Figure 8-18 Division of detection area ...................................................................... 112
Figure 8-19 STATS data MIPI output structure (RG_STATSMODE=0: 16*16) ........ 113
Figure 8-20 STATS data MIPI output structure (RG_STATSMODE=1 : 8*8) ........... 113
Figure 8-21 STATS data MIPI output structure (RG_STATSMODE=2 : 4*4) ........... 114
Figure 8-22 STATS data MIPI output structure (RG_STATSMODE=3 : 1*1) ........... 114
Figure 8-23 STATS data structure ............................................................................. 114
Figure 8-24 STATS data structure at MIPI output ..................................................... 115
Figure 8-25 STATS data structure at I2C readout ..................................................... 115
Figure 8-26 I2C based STATS communication using CCI STATS hold .................... 117
Figure 8-27 I2C based STATS communication –STATS can be read every frame .. 118
Figure 8-28 ATR operation flow chart ....................................................................... 120
Figure 8-29 ATR in standby to streaming ................................................................. 121
Preliminary
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Figure 8-30 ATR mode change – Hold mode ........................................................... 122
Figure 9-1 Thermal meter working in standby (thermal mode) ................................ 125
Figure 9-2 Thermal meter working in streaming ...................................................... 125
Figure 9-3 FSTROBE output timing during HDR mode ........................................... 131