See MIPS Run.pdf

【实例截图】

【核心代码】

Contents
Foreword v
Preface xv
Style and Limits xviii
Conventions xviii
Acknowledgments xix
Chapter 1 RISCs and MIPS Architectures 1
1.1 Pipelines 2
1.1.1 What Makes a Pipeline Inefficient? 3
1.1.2 The Pipeline and Caching 4
1.2 The MIPS Five-Stage Pipeline 5
1.3 RISC and CISC 7
1.4 Great MIPS Chips of the Past and Present 8
1.4.1 R2000 to R3000 Processors 8
1.4.2 The R6000 Processor: A Diversion 9
1.4.3 The First CPU Cores 11
1.4.4 The R4000 Processor: A Revolution 12
1.4.5 The Rise and Fall of the ACE Consortium 12
1.4.6 SGI Acquires MIPS 13
1.4.7 QED: Fast MIPS Processors for Embedded Systems 13
1.4.8 The R10000 Processor and its Successors 14
1.4.9 MIPS Processors in Consumer Electronics 15
1.4.10 MIPS in Network Routers and Laser Printers 15
1.4.11 MIPS Processors in Modern Times 17
1.4.12 The Rebirth of MIPS Technologies 20
1.4.13 The Present Day 21
1.5 MIPS Compared with CISC Architectures 23
1.5.1 Constraints on MIPS Instructions 23
1.5.2 Addressing and Memory Accesses 24
1.5.3 Features You Won’t Find 25
1.5.4 Programmer-Visible Pipeline Effects 27
vii
viii Contents
Chapter 2 MIPS Architecture 29
2.1 A Flavor of MIPS Assembly Language 33
2.2 Registers 34
2.2.1 Conventional Names and Uses of General-Purpose Registers 35
2.3 Integer Multiply Unit and Registers 38
2.4 Loading and Storing: Addressing Modes 39
2.5 Data Types in Memory and Registers 39
2.5.1 Integer Data Types 39
2.5.2 Unaligned Loads and Stores 40
2.5.3 Floating-Point Data in Memory 41
2.6 Synthesized Instructions in Assembly Language 42
2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions 43
2.7.1 To 64 Bits 45
2.7.2 Who Needs 64 Bits? 45
2.7.3 Regarding 64 Bits and No Mode Switch: Data in Registers 46
2.8 Basic Address Space 47
2.8.1 Addressing in Simple Systems 49
2.8.2 Kernel versus User Privilege Level 49
2.8.3 The Full Picture: The 64-Bit View of the Memory Map 50
2.9 Pipeline Visibility 50
Chapter 3 Coprocessor 0: MIPS Processor Control 53
3.1 CPU Control Instructions 55
3.2 Which Registers Are Relevant When? 58
3.3 CPU Control Registers and Their Encoding 59
3.3.1 Status Register (SR) 60
3.3.2 Cause Register 64
3.3.3 Exception Restart Address (EPC) Register 65
3.3.4 Bad Virtual Address (BadVAddr) Register 67
3.3.5 Count/Compare Registers: The On-CPU Timer 68
3.3.6 Processor ID (PRId) Register 68
3.3.7 Config Registers: CPU Resource Information and Configuration 69
3.3.8 EBase and IntCtl: Interrupt and Exception Setup 73
3.3.9 SRSCtl and SRSMap: Shadow Register Setup 74
3.3.10 Load-Linked Address (LLAddr) Register 75
3.4 CP0 Hazards—A Trap for the Unwary 75
3.4.1 Hazard Barrier Instructions 76
3.4.2 Instruction Hazards and User Hazards 77
3.4.3 Hazards between CP0 Instructions 77
Chapter 4 How Caches Work on MIPS Processors 79
4.1 Caches and Cache Management 79
4.2 How Caches Work 80
4.3 Write-Through Caches in Early MIPS CPUs 83
Contents ix
4.4 Write-Back Caches in MIPS CPUs 84
4.5 Other Choices in Cache Design 84
4.6 Managing Caches 86
4.7 L2 and L3 Caches 88
4.8 Cache Configurations for MIPS CPUs 88
4.9 Programming MIPS32/64 Caches 90
4.9.1 The Cache Instruction 91
4.9.2 Cache Initialization and Tag/Data Registers 92
4.9.3 CacheErr, ERR, and ErrorEPC Registers: Memory/Cache Error
Handling 94
4.9.4 Cache Sizing and Figuring Out Configuration 95
4.9.5 Initialization Routines 96
4.9.6 Invalidating or Writing Back a Region of Memory in the Cache 97
4.10 Cache Efficiency 98
4.11 Reorganizing Software to Influence Cache Efficiency 100
4.12 Cache Aliases 102
Chapter 5 Exceptions, Interrupts, and Initialization 105
5.1 Precise Exceptions 107
5.1.1 Nonprecise Exceptions—The Multiplier in Historic MIPS CPUs 108
5.2 When Exceptions Happen 109
5.3 Exception Vectors: Where Exception Handling Starts 109
5.4 Exception Handling: Basics 113
5.5 Returning from an Exception 114
5.6 Nesting Exceptions 114
5.7 An Exception Routine 115
5.8 Interrupts 115
5.8.1 Interrupt Resources in MIPS CPUs 116
5.8.2 Implementing Interrupt Priority in Software 118
5.8.3 Atomicity and Atomic Changes to SR 120
5.8.4 Critical Regions with Interrupts Enabled: Semaphores the
MIPS Way 121
5.8.5 Vectored and EIC Interrupts in MIPS32/64 CPUs 123
5.8.6 Shadow Registers 124
5.9 Starting Up 124
5.9.1 Probing and Recognizing Your CPU 126
5.9.2 Bootstrap Sequences 127
5.9.3 Starting Up an Application 128
5.10 Emulating Instructions 128
Chapter 6 Low-level Memory Management and the TLB 131
6.1 The TLB/MMU Hardware and What It Does 131
6.2 TLB/MMU Registers Described 132
6.2.1 TLB Key Fields—EntryHi and PageMask 134
6.2.2 TLB Output Fields—EntryLo0-1 136
x Contents
6.2.3 Selecting a TLB Entry—Index, Random, and Wired Registers 137
6.2.4 Page-Table Access Helpers—Context and XContext 138
6.3 TLB/MMU Control Instructions 140
6.4 Programming the TLB 141
6.4.1 How Refill Happens 142
6.4.2 Using ASIDs 143
6.4.3 The Random Register and Wired Entries 143
6.5 Hardware-Friendly Page Tables and Refill Mechanism 143
6.5.1 TLB Miss Handling 145
6.5.2 XTLB Miss Handler 146
6.6 Everyday Use of the MIPS TLB 147
6.7 Memory Management in a Simpler OS 149
Chapter 7 Floating-Point Support 151
7.1 A Basic Description of Floating Point 151
7.2 The IEEE 754 Standard and Its Background 152
7.3 How IEEE Floating-Point Numbers Are Stored 154
7.3.1 IEEE Mantissa and Normalization 155
7.3.2 Reserved Exponent Values for Use with Strange Values 155
7.3.3 MIPS FP Data Formats 156
7.4 MIPS Implementation of IEEE 754 158
7.4.1 Need for FP Trap Handler and Emulator in All MIPS CPUs 159
7.5 Floating-Point Registers 159
7.5.1 Conventional Names and Uses of Floating-Point Registers 160
7.6 Floating-Point Exceptions/Interrupts 161
7.7 Floating-Point Control: The Control/Status Register 161
7.8 Floating-Point Implementation Register 165
7.9 Guide to FP Instructions 166
7.9.1 Load/Store 167
7.9.2 Move between Registers 168
7.9.3 Three-Operand Arithmetic Operations 169
7.9.4 Multiply-Add Operations 170
7.9.5 Unary (Sign-Changing) Operations 170
7.9.6 Conversion Operations 170
7.9.7 Conditional Branch and Test Instructions 171
7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE 173
7.10.1 Exceptions on Paired-Single Instructions 174
7.10.2 Paired-Single Three-Operand Arithmetic, Multiply-Add,
Sign-Changing, and Nonconditional Move Operations 174
7.10.3 Paired-Single Conversion Operations 175
7.10.4 Paired-Single Test and Conditional Move Instructions 176
7.10.5 MIPS-3D Instructions 176
7.11 Instruction Timing Requirements 179
7.12 Instruction Timing for Speed 179
7.13 Initialization and Enabling on Demand 180
7.14 Floating-Point Emulation 181
Contents xi
Chapter 8 Complete Guide to the MIPS Instruction Set 183
8.1 A Simple Example 183
8.2 Assembly Instructions and What They Mean 185
8.2.1 U and Non-U Mnemonics 186
8.2.2 Divide Mnemonics 187
8.2.3 Inventory of Instructions 188
8.3 Floating-Point Instructions 210
8.4 Differences in MIPS32/64 Release 1 216
8.4.1 Regular Instructions Added in Release 2 216
8.4.2 Privileged Instructions Added in Release 2 218
8.5 Peculiar Instructions and Their Purposes 218
8.5.1 Load Left/Load Right: Unaligned Load and Store 218
8.5.2 Load-Linked/Store-Conditional 223
8.5.3 Conditional Move Instructions 224
8.5.4 Branch-Likely 225
8.5.5 Integer Multiply-Accumulate and Multiply-Add Instructions 226
8.5.6 Floating-Point Multiply-Add Instructions 227
8.5.7 Multiple FP Condition Bits 228
8.5.8 Prefetch 228
8.5.9 Sync: A Memory Barrier for Loads and Stores 229
8.5.10 Hazard Barrier Instructions 231
8.5.11 Synci: Cache Management for Instruction Writers 232
8.5.12 Read Hardware Register 232
8.6 Instruction Encodings 233
8.6.1 Fields in the Instruction Encoding Table 233
8.6.2 Notes on the Instruction Encoding Table 251
8.6.3 Encodings and Simple Implementation 251
8.7 Instructions by Functional Group 252
8.7.1 No-op 252
8.7.2 Register/Register Moves 252
8.7.3 Load Constant 253
8.7.4 Arithmetical/Logical 253
8.7.5 Integer Multiply, Divide, and Remainder 255
8.7.6 Integer Multiply-Accumulate 256
8.7.7 Loads and Stores 257
8.7.8 Jumps, Subroutine Calls, and Branches 259
8.7.9 Breakpoint and Trap 260
8.7.10 CP0 Functions 260
8.7.11 Floating Point 261
8.7.12 Limited User-Mode Access to “Under the Hood” Features 261
Chapter 9 Reading MIPS Assembly Language 263
9.1 A Simple Example 264
9.2 Syntax Overview 268
9.2.1 Layout, Delimiters, and Identifiers 268
9.3 General Rules for Instructions 269
xii Contents
9.3.1 Computational Instructions: Three-, Two-, and One-Register 269
9.3.2 Immediates: Computational Instructions with Constants 270
9.3.3 Regarding 64-Bit and 32-Bit Instructions 271
9.4 Addressing Modes 271
9.4.1 Gp-Relative Addressing 273
9.5 Object File and Memory Layout 274
9.5.1 Practical Program Layout, Including Stack and Heap 277
Chapter 10 Porting Software to the MIPS Architecture 279
10.1 Low-Level Software for MIPS Applications: A Checklist of
Frequently Encountered Problems 280
10.2 Endianness: Words, Bytes, and Bit Order 281
10.2.1 Bits, Bytes, Words, and Integers 281
10.2.2 Software and Endianness 284
10.2.3 Hardware and Endianness 287
10.2.4 Bi-endian Software for a MIPS CPU 293
10.2.5 Portability and Endianness-Independent Code 295
10.2.6 Endianness and Foreign Data 295
10.3 Trouble with Visible Caches 296
10.3.1 Cache Management and DMA Data 298
10.3.2 Cache Management and Writing Instructions: Self-Modifying
Code 299
10.3.3 Cache Management and Uncached or Write-Through Data 300
10.3.4 Cache Aliases and Page Coloring 301
10.4 Memory Access Ordering and Reordering 301
10.4.1 Ordering and Write Buffers 304
10.4.2 Implementing wbflush 304
10.5 Writing it in C 305
10.5.1 Wrapping Assembly Code with the GNU C Compiler 305
10.5.2 Memory-Mapped I/O Registers and “Volatile” 307
10.5.3 Miscellaneous Issues When Writing C for MIPS Applications 308
Chapter 11 MIPS Software Standards (ABIs) 311
11.1 Data Representations and Alignment 312
11.1.1 Sizes of Basic Types 312
11.1.2 Sizes of “long” and Pointer Types 313
11.1.3 Alignment Requirements 313
11.1.4 Memory Layout of Basic Types and How It Changes with
Endianness 313
11.1.5 Memory Layout of Structure and Array Types and Alignment 315
11.1.6 Bitfields in Structures 315
11.1.7 Unaligned Data from C 318
11.2 Argument Passing and Stack Conventions for MIPS ABIs 319
11.2.1 The Stack, Subroutine Linkage, and Parameter Passing 320
11.2.2 Stack Argument Structure in o32 320
11.2.3 Using Registers to Pass Arguments 321
Contents xiii
11.2.4 Examples from the C Library 322
11.2.5 An Exotic Example: Passing Structures 323
11.2.6 Passing a Variable Number of Arguments 324
11.2.7 Returning a Value from a Function 325
11.2.8 Evolving Register-Use Standards: SGIs n32 and n64 326
11.2.9 Stack Layouts, Stack Frames, and Helping Debuggers 329
11.2.10 Variable Number of Arguments and stdargs 337
Chapter 12 Debugging MIPS Designs—Debug and Profiling Features 339
12.1 The “EJTAG” On-chip Debug Unit 341
12.1.1 EJTAG History 343
12.1.2 How the Probe Controls the CPU 343
12.1.3 Debug Communications through JTAG 344
12.1.4 Debug Mode 344
12.1.5 Single-Stepping 346
12.1.6 The dseg Memory Decode Region 346
12.1.7 EJTAG CP0 Registers, Particularly Debug 348
12.1.8 The DCR (Debug Control) Memory-Mapped Register 351
12.1.9 EJTAG Breakpoint Hardware 352
12.1.10 Understanding Breakpoint Conditions 355
12.1.11 Imprecise Debug Breaks 356
12.1.12 PC Sampling with EJTAG 356
12.1.13 Using EJTAG without a Probe 356
12.2 Pre-EJTAG Debug Support—Break Instruction and CP0
Watchpoints 358
12.3 PDtrace 359
12.4 Performance Counters 360
Chapter 13 GNU/Linux from Eight Miles High 363
13.1 Components 364
13.2 Layering in the Kernel 368
13.2.1 MIPS CPU in Exception Mode 368
13.2.2 MIPS CPU with Some or All Interrupts off 369
13.2.3 Interrupt Context 370
13.2.4 Executing the Kernel in Thread Context 370
Chapter 14 How Hardware and Software Work Together 371
14.1 The Life and Times of an Interrupt 371
14.1.1 High-Performance Interrupt Handling and Linux 374
14.2 Threads, Critical Regions, and Atomicity 375
14.2.1 MIPS Architecture and Atomic Operations 376
14.2.2 Linux Spinlocks 377
14.3 What Happens on a System Call 378
14.4 How Addresses Get Translated in Linux/MIPS Systems 380
xiv Contents
14.4.1 What’s Memory Translation For? 382
14.4.2 Basic Process Layout and Protection 384
14.4.3 Mapping Process Addresses to Real Memory 385
14.4.4 Paged Mapping Preferred 386
14.4.5 What We Really Want 387
14.4.6 Origins of the MIPS Design 389
14.4.7 Keeping Track of Modified Pages (Simulating “Dirty” Bits) 392
14.4.8 How the Kernel Services a TLB Refill Exception 393
14.4.9 Care and Maintenance of the TLB 397
14.4.10 Memory Translation and 64-Bit Pointers 397
Chapter 15 MIPS Specific Issues in the Linux Kernel 399
15 Explicit Cache Management 399
15.1.1 DMA Device Accesses 399
15.1.2 Writing Instructions for Later Execution 401
15.1.3 Cache/Memory Mapping Problems 401
15.1.4 Cache Aliases 402
15.2 CP0 Pipeline Hazards 403
15.3 Multiprocessor Systems and Coherent Caches 403
15.4 Demon Tweaks for a Critical Routine 406
Chapter 16 Linux Application Code, PIC, and Libraries 409
16.1 How Link Units Get into a Program 411
16.2 Global Offset Table (GOT) Organization 412
Appendix A MIPS Multithreading 415
A.1 What Is Multithreading? 415
A.2 Why Is MT Useful? 417
A.3 How to Do Multithreading for MIPS 417
A.4 MT in Action 421
Appendix B Other Optional Extensions to the MIPS Instruction Set 425
B.1 MIPS16 and MIPS16e ASEs 425
B.1.1 Special Encodings and Instructions in the MIPS16 ASE 426
B.1.2 The MIPS16 ASE Evaluated 427
B.2 The MIPS DSP ASE 428
B.3 The MDMX ASE 429
MIPS Glossary 431
References 477
Books and Articles 477
Online Resources 478
Index 481