实例介绍
【实例简介】VESA DisplayPort Standard
Version 1, Revision 2
January 5, 2010
【实例截图】
【核心代码】
Table of Contents
Preface ...............................................................................................................................................................15
Acknowledgements............................................................................................................................................17
Revision History ................................................................................................................................................20
1 Introduction .................................................................................................................................................21
1.1 DisplayPort Standard Organization ......................................................................................................21
1.2 DisplayPort Objectives .........................................................................................................................21
1.2.1 Key Industry Needs for DisplayPort..............................................................................................................22
1.2.2 DisplayPort Technical Objectives..................................................................................................................22
1.2.3 DisplayPort External Connection Objectives.................................................................................................23
1.2.4 DisplayPort Internal Connection Objectives..................................................................................................24
1.2.5 DisplayPort CE Connection Objectives.........................................................................................................24
1.2.6 Content Protection for DisplayPort................................................................................................................24
1.3 Acronyms..............................................................................................................................................24
1.4 Glossary ................................................................................................................................................27
1.5 Reference Documents ...........................................................................................................................31
1.6 Nomenclature for Bit and Byte Ordering..............................................................................................32
1.6.1 Bit Ordering ...................................................................................................................................................32
1.6.2 Byte Ordering ................................................................................................................................................33
1.7 Overview of DisplayPort ......................................................................................................................34
1.7.1 Make-up of the Main Link.............................................................................................................................34
1.7.2 Make-up of AUX CH.....................................................................................................................................35
1.7.3 Link Configuration and Management ............................................................................................................35
1.7.4 Layered, Modular Architecture......................................................................................................................36
2 Link Layer ...................................................................................................................................................37
2.1 SST Mode Introduction.........................................................................................................................37
2.1.1 Number of Lanes and Per-lane Data Rate (Applicable both in SST and MST Modes) .................................38
2.1.2 Number of Main, Uncompressed Video Streams in SST Mode ....................................................................38
2.1.3 Basic Functions (Applicable both in SST and MST Modes) .........................................................................38
2.1.4 DisplayPort Device Types and Link Topology in SST Mode........................................................................38
2.2 Isochronous Transport Services in SST Mode......................................................................................43
2.2.1 Main Stream to Main Link Lane Mapping in the Source Device ..................................................................43
2.2.2 Stream Reconstruction in the Sink.................................................................................................................71
2.2.3 Stream Clock Recovery .................................................................................................................................72
2.2.4 Main Stream Attribute Data Transport ..........................................................................................................74
2.2.5 Secondary-data Packing Formats...................................................................................................................79
2.2.6 ECC for Secondary-data Packet...................................................................................................................101
2.3 AUX CH States and Arbitration .........................................................................................................107
2.3.1 AUX CH STATES Overview......................................................................................................................107
2.3.2 Link Layer Arbitration Control....................................................................................................................111
2.3.3 Policy Maker AUX CH Management ..........................................................................................................111
2.3.4 Detailed uPacket TX AUX CH State Description .......................................................................................112
2.3.5 Detailed uPacket RX AUX CH State Description .......................................................................................113
2.4 Overview of DP Multi-Stream Transport (MST) Isochronous Transport Service..............................114
2.4.1 Connection-oriented Transport ....................................................................................................................115
2.4.2 Layers of DP Isochronous Transport Service ..............................................................................................117
2.4.3 Sideband CH Communications....................................................................................................................121
2.5 Topology Management Layer.............................................................................................................122
2.5.1 Primitives of MST DP Devices and Device Types ......................................................................................122
2.5.2 MST Topologies ..........................................................................................................................................125
2.5.3 MST Device Identification...........................................................................................................................126
2.5.4 Topology Manager and Topology Assistant ................................................................................................127
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 2 of 5152.5.5 Topology Discovery.....................................................................................................................................128
2.5.6 Topology Maintenance ................................................................................................................................128
2.5.7 Topologies with SST-only Source devices ..................................................................................................129
2.5.8 Loop Handling .............................................................................................................................................129
2.6 Multi-Stream Transport Operation......................................................................................................131
2.6.1 Link Timing Generation Based on Multi-Stream Transport Packet ............................................................135
2.6.2 Symbol Sequence Mapping into VC Payload..............................................................................................136
2.6.3 Time Slot Count Allocation to VC Payload.................................................................................................144
2.6.4 VC Payload Allocation Synchronization Management................................................................................150
2.6.5 ALLOCATE_PAYLOAD Timing Sequence...............................................................................................154
2.6.6 Impacts of Various Events on VC Payload ID Table...................................................................................161
2.6.7 Robustness Requirement..............................................................................................................................164
2.6.8 Control Functions, Control Symbols and K-Code Assignment ...................................................................164
2.6.9 Conversion Between MST and SST Symbol Mapping................................................................................166
2.6.10 MTPH Usages for CP Extension in MST Mode .........................................................................................167
2.7 AUX Transaction Syntax in Manchester Transaction Format............................................................170
2.7.1 Command definition ....................................................................................................................................171
2.7.2 AUX Transaction Response/Reply Time-outs.............................................................................................173
2.7.3 Native AUX Request Transaction Syntax....................................................................................................173
2.7.4 Native AUX Reply Transaction Syntax.......................................................................................................174
2.7.5 I2
C Bus Transaction Mapping onto AUX Syntax ........................................................................................174
2.7.6 Conversion of I2
C Transaction to Native AUX Transaction (Informative) .................................................192
2.7.7 I2
C-overAUX Transaction Clarifications and Implementation Rules..........................................................192
2.8 Transaction Syntax in FAUX Transaction Format .............................................................................202
2.9 AUX CH Services...............................................................................................................................203
2.9.1 Stream Transport Initiation Sequence..........................................................................................................203
2.9.2 Stream Transport Termination Sequence.....................................................................................................204
2.9.3 AUX Link Services......................................................................................................................................205
2.9.4 AUX Device Services ..................................................................................................................................253
2.10 Protocol Differentiation for Embedded DisplayPort (eDP) ................................................................255
2.10.1 Overview.....................................................................................................................................................255
2.10.2 Protocol Differentiation Methods................................................................................................................255
2.10.3 eDP Source Behavior (Informative)............................................................................................................255
2.10.4 Symbol Error Rate Measurement Pattern Output (Informative) .................................................................256
2.11 Messaging AUX Client.......................................................................................................................258
2.11.1 Messaging AUX Client Layers ...................................................................................................................259
2.11.2 Message Transaction Layer.........................................................................................................................260
2.11.3 Sideband MSG Layer..................................................................................................................................268
2.11.4 AUX CH Support for Messaging AUX Client............................................................................................273
2.11.5 RAD (Relative Address) Updated by MST Devices in the Path.................................................................274
2.11.6 Broadcast Message Transactions ................................................................................................................275
2.11.7 Message Delivery........................................................................................................................................276
2.11.8 Error Handling ............................................................................................................................................279
2.11.9 Descriptions of Available Message Transaction Requests..........................................................................281
2.12 Audio-to-Video & Audio-to-Audio Synchronization .........................................................................297
2.12.1 Overview.....................................................................................................................................................297
2.12.2 DisplayPort AV Sync Data Block (AVSDB)..............................................................................................298
2.12.3 Delay Compensation ...................................................................................................................................298
2.13 Global Time Code and Audio Inter-channel Sync..............................................................................304
2.13.1 Global Time Code.......................................................................................................................................304
2.13.2 Application of GTC for Audio Inter-channel Synchronization...................................................................307
3 Physical Layer ...........................................................................................................................................309
3.1 Introduction.........................................................................................................................................309
3.1.1 PHY Functions.............................................................................................................................................309
3.1.2 Link Layer-PHY Interface Signals...............................................................................................................310
3.1.3 PHY-Media Interface Signals ......................................................................................................................311
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 3 of 5153.1.4 Compliance Measurement Points.................................................................................................................312
3.1.5 Electrical Signal Definitions ........................................................................................................................319
3.1.6 Scrambling...................................................................................................................................................323
3.1.7 Symbol Coding and Serialization/De-serialization ......................................................................................324
3.2 DP_PWR for Box-to-Box DisplayPort Connection............................................................................325
3.2.1 DP_PWR User Detection Method ...............................................................................................................326
3.2.2 DP_PWR Wire.............................................................................................................................................326
3.2.3 Inrush Energy...............................................................................................................................................326
3.2.4 Voltage Droop..............................................................................................................................................326
3.2.5 Over-Current Protection...............................................................................................................................326
3.3 Hot Plug/Unplug Detect Circuitry ......................................................................................................327
3.4 AUX Channel......................................................................................................................................329
3.4.1 AUX Channel Logical Sub-block ................................................................................................................329
3.4.2 AUX Channel Electrical Sub-block.............................................................................................................341
3.5 Main Link............................................................................................................................................353
3.5.1 Main Link Logic Sub-block.........................................................................................................................353
3.5.2 Main Link Electrical Sub-Block ..................................................................................................................362
3.5.3 Transmitter and Receiver Electrical Parameters ..........................................................................................362
3.5.4 ESD and EOS Protection .............................................................................................................................378
4 Mechanical ................................................................................................................................................379
4.1 Cable-Connector Assembly Specifications (for box-to-box)..............................................................379
4.1.1 Cable-Connector Assembly Definition........................................................................................................380
4.1.2 Type of Bulk Cable......................................................................................................................................383
4.1.3 Impedance Profile ........................................................................................................................................384
4.1.4 Insertion Loss & Return Loss ......................................................................................................................386
4.1.5 High Bit Rate Cable-Connector Assembly Specification ............................................................................387
4.1.6 Reduced Bit Rate Cable-Connector Assembly Specification ......................................................................397
4.2 Connector Specification......................................................................................................................401
4.2.1 External full-size connector .........................................................................................................................401
4.2.2 Mini DisplayPort External Connector..........................................................................................................413
4.2.3 Panel-side Internal Connector (Informative)................................................................................................438
5 Source/Sink/Branch Device Policy Requirements for Interoperability.....................................................446
5.1 Source Device in SST Mode...............................................................................................................446
5.1.1 Stream Source Requirement.........................................................................................................................446
5.1.2 Source Device Link Configuration Requirement.........................................................................................449
5.1.3 Source Device Behavior on Stream Timing Change....................................................................................449
5.1.4 Source Device Behavior upon HPD Pulse Detection...................................................................................450
5.1.5 Downstream Device uPacket RX Power Management by a Source Device................................................452
5.1.6 Source Device Connected to a Branch Device.............................................................................................452
5.2 Sink Device in SST Mode...................................................................................................................452
5.2.1 Stream Sink Requirement ............................................................................................................................452
5.2.2 Sink Device Link Configuration Requirement.............................................................................................453
5.2.3 Sink Device Behavior on Stream Timing Change .......................................................................................454
5.2.4 Toggling of HPD Signal for Status Change Notification.............................................................................454
5.2.5 Sink Device uPacket RX Power-Save Mode ...............................................................................................454
5.3 Branch Device in SST-only Mode......................................................................................................458
5.3.1 EDID Access Handling Requirement ..........................................................................................................458
5.3.2 Branch Device Link Configuration Requirements.......................................................................................458
5.4 Source Device in MST Mode..............................................................................................................462
5.5 Sink Device in MST Mode .................................................................................................................463
5.6 Branch Device in MST Mode .............................................................................................................463
5.7 Cable-Connector Assembly ................................................................................................................463
5.7.1 Box-to-Box, End-User-Detachable Cable Assembly...................................................................................463
5.7.2 Embedded and Captive Cable Assembly .....................................................................................................464
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 4 of 5156 Appendix A: Audio Transport (Informative).............................................................................................465
6.1 Audio Stream Components .................................................................................................................465
6.2 Association of Three Packet Types via Packet ID ..............................................................................465
6.3 Scheduling of Audio Stream Packet Transmission.............................................................................465
6.3.1 Handling of an Audio Format Change.........................................................................................................466
6.4 Structure of Audio Stream Packet.......................................................................................................467
6.4.1 One or Two Channel Audio.........................................................................................................................467
6.4.2 Three to Eight Channel Audio .....................................................................................................................467
6.5 Channel-to-Speaker Mapping .............................................................................................................468
6.6 Transfer of Sample Frequency Information........................................................................................469
7 Appendix B: Sink Event Notification Example (Informative) ..................................................................470
7.1 Mutual Identification by Source and Sink ..........................................................................................470
7.2 IRQ_HPD Pulse and Sink-Specific IRQ.............................................................................................470
8 Appendix C: Link Quality Management (Informative).............................................................................471
8.1 Marginal Link Quality ........................................................................................................................471
8.2 Analysis...............................................................................................................................................471
8.3 Tolerance to Bit Errors........................................................................................................................471
8.4 Link Re-training..................................................................................................................................472
8.5 Long-term Link Quality Monitoring (Guidelines)..............................................................................472
9 Appendix D: Electrical Specifications (Informative) ................................................................................473
9.1 AUX Parameters .................................................................................................................................473
9.1.1 FAUX Electrical Parameter Background.....................................................................................................474
9.2 Main Link Parameters.........................................................................................................................477
9.3 The Dual-Dirac Jitter Model...............................................................................................................481
10 Appendix E: Scrambler C Code Reference (Informative)........................................................................483
11 Appendix F: Topology Management/Payload Bandwidth Management Usage Examples......................488
12 Appendix G: Link Management During System Initialization (Informative) ..........................................489
12.1 Background.........................................................................................................................................489
12.2 Problem Statements ............................................................................................................................489
12.2.1 Problem #1: Sink Attached and Powered, but HPD Low............................................................................489
12.2.2 Problem #2: Sink HPD Unplug Event Followed by Plug Event .................................................................489
13 Appendix H: Protocol Support for 3D Stereo Display .............................................................................494
13.1 In-band 3D Stereo Signaling Methods................................................................................................494
13.1.1 MSA MISC1 Method..................................................................................................................................494
13.1.2 Video_Stream_Configuration (VSC) Packet Method .................................................................................494
13.2 3D Stereo Display Capability Declaration..........................................................................................500
13.2.1 EDID 3D Stereo Display Capability Declaration........................................................................................500
13.2.2 DisplayID 3D Stereo Display Capability Declaration.................................................................................501
14 Appendix I: QUERY_STREAM_ENCRYPTION_STATUS MESSAGE TRANSACTION in a CP Tree
Topology..........................................................................................................................................................504
14.1 Self-checking by Branch Devices .......................................................................................................504
14.2 Merit of QUERY_STREAM_ENCRYPTION_STATUS Message Transaction ...............................504
14.3 QUERY_STREAM_ENCRYPTION_STATUS Message Transaction Handling in a CP Tree
Topology ......................................................................................................................................................505
14.3.1 IDs Provided by Source Device for QUERY_STREAM_ENCRYPTION_STATUS Request Message
Transaction ...............................................................................................................................................................505
14.3.2 Stream Status in QUERY_STREAM_ENCRYPTION_STATUS Reply Transaction ...............................506
14.3.3 Stream Status Signature in QUERY_STREAM_ENCRYPTION_STATUS Reply Message Transaction 507
14.3.4 Usage of Sink Type in Stream Status by a Source Device..........................................................................507
14.3.5 Status Query................................................................................................................................................507
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 5 of 51514.3.6 Application of QUERY_STREAM_ENCRYPTION _STATUS Message Transaction to HDCP .............509
15 Appendix J: DisplayPort Power (Informative) .........................................................................................510
16 Main Contributor History (Previous Versions) ........................................................................................511
Tables
Table 0-1: Main Contributors ............................................................................................................................17
Table 1-1: List of Acronyms..............................................................................................................................24
Table 1-2: Glossary of Terms ............................................................................................................................27
Table 1-3: Reference Documents.......................................................................................................................31
Table 2-1: Control Symbols for Framing...........................................................................................................48
Table 2-2: Pixel Steering into Main Link Lanes................................................................................................48
Table 2-3: VB-ID Bit Definition........................................................................................................................50
Table 2-4: 30bpp RGB (10 Bits/Component) 1366x768 Packing to a 4-Lane Main Link ................................53
Table 2-5: 24bpp RGB to a 4-Lane Main Link Mapping ..................................................................................54
Table 2-6: 24bpp RGB Mapping to a 2-Lane Main Link ..................................................................................54
Table 2-7: 24bpp RGB Mapping to a 1-Lane Main Link ..................................................................................54
Table 2-8: 18bpp RGB Mapping to a 4-Lane Main Link ..................................................................................55
Table 2-9: 18bpp RGB Mapping to a 2-Lane Main Link ..................................................................................55
Table 2-10: 18bpp RGB Mapping to a 1-Lane Main Link ................................................................................55
Table 2-11: 30bpp RGB Mapping to a 4-Lane Main Link ................................................................................56
Table 2-12: 30bpp RGB Mapping to a 2-Lane Main Link ................................................................................56
Table 2-13: 30bpp RGB Mapping to a 1-Lane Main Link ................................................................................57
Table 2-14: 36 bpp RGB Mapping to a 4-Lane Main Link ...............................................................................57
Table 2-15: 36bpp RGB Mapping to a 2-Lane Main Link ................................................................................58
Table 2-16: 36bpp RGB Mapping to a 1-Lane Main Link ................................................................................58
Table 2-17: 48bpp RGB Mapping to a 4-Lane Main Link ................................................................................59
Table 2-18: 48bpp RGB Mapping to a 2-Lane Main Link ................................................................................59
Table 2-19: 48bpp RGB Mapping to a 1-Lane Main Link ................................................................................60
Table 2-20: 16bpp YCbCr 4:2:2 Mapping to a 4-Lane Main Link.......................................................................60
Table 2-21: 16bpp YCbCr 4:2:2 Mapping to a 2-Lane Main Link .......................................................................60
Table 2-22: 16bpp YCbCr 4:2:2 Mapping to a 1-Lane Main Link .......................................................................61
Table 2-23: 20bpp YCbCr 4:2:2 Mapping to a 4-Lane Main Link.......................................................................61
Table 2-24: 20bpp YCbCr 4:2:2 Mapping to a 2-Lane Main Link .......................................................................62
Table 2-25: 20bpp YCbCr 4:2:2 Mapping to a One Lane Main Link ..................................................................62
Table 2-26: 24bpp YCbCr 4:2:2 Mapping to a 4-Lane Main Link .......................................................................62
Table 2-27: 24bpp YCbCr 4:2:2 Mapping to a 2-Lane Main Link.......................................................................63
Table 2-28: 24bpp YCbCr 4:2:2 Mapping to a 1-Lane Main Link.......................................................................63
Table 2-29: 32bpp YCbCr 4:2:2 Mapping to a 4-Lane Main Link ....................................................................63
Table 2-30: 32bpp YCbCr 4:2:2 Mapping to a 2-Lane Main Link.......................................................................64
Table 2-31: 32bpp YCbCr 4:2:2 Mapping to a 1-Lane Main Link.......................................................................64
Table 2-32: 8bpp Y-only to a 4-Lane Main Link Mapping ...............................................................................64
Table 2-33: 8bpp Y-only Mapping to a 2-Lane Main Link ...............................................................................65
Table 2-34: 8bpp Y-only Mapping to a 1-Lane Main Link ...............................................................................65
Table 2-35: 10bpp Y-only Mapping to a 4-Lane Main Link .............................................................................65
Table 2-36: 10bpp Y-only Mapping to a 2- Lane Main Link ............................................................................65
Table 2-37: 10bpp Y-only Mapping to a 1-Lane Main Link .............................................................................66
Table 2-38: 12bpp Y-only Mapping to a 4-lane Main Link...............................................................................66
Table 2-39: 12bpp Y-only Mapping to a 2-Lane Main Link .............................................................................66
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 6 of 515Table 2-40: 12bpp Y-only Mapping to a 1-Lane Main Link .............................................................................66
Table 2-41: 16bpp Y-only Mapping to a 4-Lane Main Link .............................................................................66
Table 2-42: 16bpp Y-only Mapping to a 2-Lane Main Link .............................................................................67
Table 2-43: 16bpp Y-only Mapping to a 1-Lane Main Link .............................................................................67
Table 2-44: Transfer Unit of 30bpp RGB Video Over a 2.7Gbps per Lane Main Link ....................................69
Table 2-45: MISC0 field for Color Encoding Format Indication ......................................................................78
Table 2-46: Secondary-data Packet Header .......................................................................................................79
Table 2-47: Secondary-data Packet Type ..........................................................................................................79
Table 2-48: Header Bytes of InfoFrame Packet.................................................................................................81
Table 2-49: Header Bytes of Audio_TimeStamp Packet...................................................................................83
Table 2-50: Examples of Maud and Naud Values .............................................................................................83
Table 2-51: Header Bytes of Audio_Stream Packet ..........................................................................................85
Table 2-52: Bit Definition of an Audio_Stream Packet Payload with IEC60958-like Coding .........................88
Table 2-53: Header Bytes of Audio_CopyManagement Packet ........................................................................90
Table 2-54: Header Bytes of ISRC Packet.........................................................................................................92
Table 2-55: Header Bytes of VSC Packet..........................................................................................................94
Table 2-56: VSC Packet Payload.......................................................................................................................94
Table 2-57: Header Bytes of an Extension Packet...........................................................................................101
Table 2-58: uPacket TX AUX CH State and Event Descriptions....................................................................112
Table 2-59: uPacket RX AUX CH State and Event Description .....................................................................113
Table 2-60: Summary of VC Payload Control Symbol Sequence...................................................................139
Table 2-61: VC Payload Bandwidth for One Time Slot per MTP Allocation for Various Link Configurations
.................................................................................................................................................................147
Table 2-62: VC Payload ID Table of uPacket RX Mapped to DPCD Address Space ....................................151
Table 2-63: DPCD Address Map for VC Payload Table Update and ACT Status Verification......................152
Table 2-64: Various Events and Impacts on VC Payload ID Table ................................................................162
Table 2-65: MTP Header Control Functions ...................................................................................................165
Table 2-66: MTP Payload Control Functions ..................................................................................................165
Table 2-67: K-code Scrambled Index Map......................................................................................................166
Table 2-68: Bit/Byte Size of Various Data Types of AUX Transaction Syntax..............................................171
Table 2-69: I2
C Write Transaction Example 1.................................................................................................177
Table 2-70: I2
C Write Transaction Method 1 with a Slow I2
C Bus in the Sink Device ..................................179
Table 2-71: I2
C Write Transaction Method 2 ..................................................................................................183
Table 2-72: I2
C Read Transaction Method 1 ...................................................................................................185
Table 2-73: I2
C Read Transaction Example 2..................................................................................................187
Table 2-74: I2
C Write Followed by an I2
C Read .............................................................................................190
Table 2-75: Address Mapping for DPCD (DisplayPort Configuration Data)..................................................206
Table 2-76: ANSI8B/10B Encoding and Scrambling Rules for Link Management........................................252
Table 2-77: DisplayPort Address Mapping for Device Services .....................................................................254
Table 2-78: Message Transaction Sequence Syntax........................................................................................261
Table 2-79: Message Transaction Request Syntax ..........................................................................................261
Table 2-80: Request Names and Request Identifiers ......................................................................................261
Table 2-81: Request Data................................................................................................................................262
Table 2-82: Message Transaction Reply Syntax..............................................................................................264
Table 2-83: Reply Data....................................................................................................................................264
Table 2-84: Reasons for NAK .........................................................................................................................265
Table 2-85: ACK_DATA ................................................................................................................................267
Table 2-86: Sideband MSG Syntax .................................................................................................................269
Table 2-87: Sideband MSG Header Syntax.....................................................................................................269
Table 2-88: Sideband MSG Body Syntax........................................................................................................272
Table 2-89: ALLOCATE_PAYLOAD Message Syntax.................................................................................282
Table 2-90: CLEAR_PAYLOAD_ID_TABLE Message Syntax....................................................................283
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©Copyright 2007-2010 Video Electronics Standards Association Page 7 of 515Table 2-91: CONNECTION_STATUS_NOTIFY Message Syntax ...............................................................284
Table 2-92: Peer Device Type .........................................................................................................................285
Table 2-93: Peer_ Device_ Type Determination .............................................................................................285
Table 2-94: ENUM_PATH_RESOURCES Message Syntax..........................................................................286
Table 2-95: LINK_ADDRESS Message Syntax .............................................................................................287
Table 2-96: POWER_DOWN_PHY Message Syntax.....................................................................................289
Table 2-97: POWER_UP_PHY Message Syntax............................................................................................290
Table 2-98: QUERY_PAYLOAD Message Syntax ........................................................................................290
Table 2-99: REMOTE_DPCD_READ Message Syntax .................................................................................291
Table 2-100: REMOTE_DPCD_READ Message Syntax ...............................................................................292
Table 2-101: REMOTE_I2
C Message Syntax .................................................................................................293
Table 2-102: REMOTE_I2
C_WRITE Message Syntax...................................................................................295
Table 2-103: RESOURCE_STATUS_NOTIFY Message Syntax ..................................................................296
Table 3-1: Allowed Vdiff_pp - Pre-emphasis Combinations ..........................................................................320
Table 3-2: Post Cursor Tap Coefficients (Informative) ...................................................................................322
Table 3-3: DP_PWR Specification for Box-to-Box DisplayPort Connection .................................................325
Table 3-4: Hot Plug Detect Signal Specification .............................................................................................327
Table 3-5: ANSI 8B/10B Special Characters for DisplayPort Control Symbols.............................................332
Table 3-6: DisplayPort AUX Channel Electrical Specifications .....................................................................341
Table 3-7: FAUX Differential Noise Budget...................................................................................................347
Table 3-8: Mask Vertices for AUX CH for Manchester Transactions at Connector Pins of Transmitting
Device ......................................................................................................................................................348
Table 3-9: Mask Vertices for AUX CH for Manchester Transactions at Connector Pins of Receiving Device
.................................................................................................................................................................348
Table 3-10: FAUX Forward Channel Transmitter Mask Vertices...................................................................350
Table 3-11: FAUX Back Channel Transmitter Mask Vertices........................................................................350
Table 3-12: FAUX Forward Channel Receiver EYE Vertices ........................................................................351
Table 3-13: Table 3-14: FAUX Back Channel Receiver EYE Vertices..........................................................351
Table 3-15: ANSI 8B/10B Special Characters for DisplayPort Control Symbols...........................................353
Table 3-16: Symbol Patterns of Link Training ................................................................................................356
Table 3-17: DisplayPort Main Link Transmitter (Main TX) System Parameters............................................362
Table 3-18: DisplayPort Main Link Transmitter (Main TX) TP2 Parameters.................................................363
Table 3-19: DisplayPort Main Link Transmitter (Main TX) TP3 EQ Parameters ..........................................364
Table 3-20: DisplayPort Main Link Receiver (Main RX) System Parameters................................................364
Table 3-21: DisplayPort Main Link Receiver (Main RX) TP3 Parameters.....................................................365
Table 3-22: DisplayPort Main Link Receiver (Main RX) TP3 EQ Parameters...............................................366
Table 3-23: Differential Noise Budget.............................................................................................................371
Table 3-24: Upstream Device Mask Vertices for High Bit Rate .....................................................................373
Table 3-25: Upstream Device Mask Vertices for Reduced Bit Rate ...............................................................373
Table 3-26: Downstream Device EYE Vertices for TP3_EQ at High Bit Rate...............................................375
Table 3-27: Downstream Device EYE Vertices at TP3 for Reduced Bit Rate ................................................375
Table 3-28: TP3 EYE Mask Vertices at HBR for Embedded Connection (Informative)................................377
Table 3-29: TP3 EYE Mask Vertices for RBR for Embedded Connection (Informative) ..............................378
Table 4-1: Impedance Profile Values for Cable Assembly..............................................................................384
Table 4-2: Impedance Profile Values for Cable Assembly..............................................................................385
Table 4-3: Mixed Mode Differential/Common Relations of S-Parameters .....................................................386
Table 4-4 Downstream Port Connector Pin Assignment .................................................................................401
Table 4-5: Upstream Port Connector Pin Assignment.....................................................................................402
Table 4-6: Mating Sequence Level ..................................................................................................................403
Table 4-7: Connector Mechanical Performance ..............................................................................................404
Table 4-8: Connector Electrical Performance..................................................................................................405
Table 4-9: Connector Environment Performance ............................................................................................406
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©Copyright 2007-2010 Video Electronics Standards Association Page 8 of 515Table 4-10: Downstream Port Mini DisplayPort Connector Pin Assignment .................................................413
Table 4-11: Upstream Port Mini DisplayPort Connector Pin Assignment ......................................................414
Table 4-12: Mini DisplayPort Connector Mechanical Performance Requirements ........................................426
Table 4-13: Mini DisplayPort Connector Electrical Performance Requirements............................................427
Table 4-14: Mini DisplayPort Connector Environment Performance Requirements ......................................428
Table 4-15: Mating Sequence Level ................................................................................................................433
Table 4-16: DisplayPort Panel-side Internal Connector Pin Assignment........................................................439
Table 4-17: Panel-side Connector Mechanical Requirements .........................................................................444
Table 4-18: Panel-side Connector Electrical Requirements ............................................................................445
Table 4-19: Panel-side Connector Environmental Requirements....................................................................445
Table 5-1: DisplayPort Colorimetry Format Support ......................................................................................446
Table 5-2: Required Lane Count for Typical TV Timings at Reduced Bit Rate .............................................453
Table 5-3: Required Lane Count for Typical Data Projector Timings at Reduced Bit Rate ...........................453
Table 5-4: DPCD Parameters Branch Device May Update.............................................................................459
Table 5-5: UP_REQ_EN/MST_EN Setting.....................................................................................................462
Table 6-1: Channel to Speaker Mapping of Three Channel Audio with CA = 04h.........................................468
Table 9-1: FAUX Electrical Parameters at the Transmitting IC Packages Pins (Informative)........................473
Table 9-2: Mask Vertices for AUX CH at Transmitting IC Packages Pins (Informative) ..............................473
Table 9-3: Mask Vertices for AUX CH at Receiving IC Packages Pins (Informative)...................................474
Table 9-4: FAUX Channel Topology Parameters............................................................................................475
Table 9-5: Upstream and Downstream Silicon RJ and DJ Assumptions.........................................................476
Table 9-6: DisplayPort Main Link Transmitter (Main TX) Silicon Parameters (Informative)........................478
Table 9-7: DisplayPort Main Link Transmitter (Main TX) TP1 Package Pin Parameters (Informative)........479
Table 9-8: DisplayPort Main Link Receiver (Main RX) TP4 Package Pin Parameters (Informative)............480
Table 9-9: DisplayPort Main Link Receiver (Main RX) RX Silicon Pads with HBR/RBR (Informative) .....480
Table 9-10: DisplayPort Main Link Receiver (Main RX) RX Silicon Pads with HBR2 (Informative) ..........481
Table 13-1: Header Bytes of VSC Packet........................................................................................................494
Table 13-2: VSC Payload ................................................................................................................................495
Table 13-3: EDID Ver.1.4, 3D Stereo Display Capability Declaration...........................................................500
Table 13-4: DisplayID Ver.1.1, 3D Stereo Display Capability Declaration....................................................501
Table 13-5: 3D Stereo Display Format Supported in DisplayID v1.1.............................................................503
Table 13-6: 3D Stereo Display Format Supported in the Upcoming Version of DisplayID ...........................503
Table 14-1: IDs Provided by the Source Device for QUERY_STREAM_ENCRYPTION_STATUS Request
Message Transaction................................................................................................................................505
Table 14-2: Stream Status Information Replied by the Branch Device...........................................................506
Table 14-3: Stream Status Signature................................................................................................................507
Table 16-1: Main Contributors to Version 1.0.................................................................................................511
Table 16-2: Main Contributors to Version 1.1.................................................................................................512
Table 16-3: Main Contributors to Version 1.1a...............................................................................................514
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 9 of 515Figures
Figure 1-1: DisplayPort Data Transport Channels.............................................................................................34
Figure 1-2: Layered Architecture.......................................................................................................................36
Figure 2-1: Overview of Link Layer Services ...................................................................................................37
Figure 2-2: Single Link DisplayPort Link .........................................................................................................40
Figure 2-3: DisplayPort Source Device to DisplayPort Sink Device via a Repeater.........................................40
Figure 2-4: DisplayPort Source Device to Legacy Sink via DisplayPort-to-Legacy Converter........................40
Figure 2-5: Legacy Source Device to DisplayPort Sink Device via a Legacy-to-DisplayPort Converter.........41
Figure 2-6: Multiple DisplayPort Source Devices to a DisplayPort Sink Device via an Input Switch .............41
Figure 2-7: A DisplayPort Source Device to Multiple DisplayPort Sink Devices via a Replicator ..................42
Figure 2-8: High Level Block Diagram of DP uPacket TX Main Link Data Path ............................................44
Figure 2-9: High Level Block Diagram of DP uPacket RX Main Link Data Path ............................................45
Figure 2-10: Main Video Stream Data Packing Example for a Four Lane Main Link......................................49
Figure 2-11: Link Symbols Over the Main Link without Main Video Stream..................................................51
Figure 2-12: VB-ID, Mvid7:0 and Maud7:0 Packing Over the Main Link .......................................................52
Figure 2-13: Transfer Unit .................................................................................................................................68
Figure 2-14: Secondary-Data Insertion..............................................................................................................70
Figure 2-15: Inter-lane Skewing ........................................................................................................................71
Figure 2-16: Reference Pulse and Feedback Pulse of Stream Clock Recovery Circuit.....................................72
Figure 2-17: M and N Value Determination in Asynchronous Clock Mode.....................................................73
Figure 2-18: Transport of DisplayPort Main Stream Attribute..........................................................................76
Figure 2-19: Interlaced Video Format/Timing for Odd Number of Lines per Frame........................................77
Figure 2-20: Interlaced Video Format/Timing for Even Number of Lines per Frame ......................................77
Figure 2-21: InfoFrame Packet ..........................................................................................................................80
Figure 2-22: Audio_TimeStamp Packet ............................................................................................................82
Figure 2-23: Audio_Stream Packet over the Main Link for One or Two Channel-Layout Audio ....................86
Figure 2-24: Audio_Stream Packet over the Main Link for One or Eight Channel-Layout Audio...................87
Figure 2-25: Data Mapping Within the 4-Byte Payload of an Audio_Stream Packet .......................................88
Figure 2-26: Audio_CopyManagement Packet over the Main Link..................................................................91
Figure 2-27: ISRC Packet over the Main Link ..................................................................................................94
Figure 2-28: Pixel Pattern Representation for Pixel Interleaved Method ..........................................................96
Figure 2-29: Interleave Pattern Corresponding to 2-way Interleaved Stereo where Right Image Pixels are on
Even Lines .................................................................................................................................................97
Figure 2-30: Interleave Pattern Corresponding to 2-way Interleaved Stereo where Right Image Pixels are on
Even Lines .................................................................................................................................................97
Figure 2-31: Interleave Pattern Corresponding to a Checkerboard Pattern with Alternating Left and Right
Image Pixels...............................................................................................................................................98
Figure 2-32: Field Sequential Stereo Format with Left View and Right View Indicated via MISC1 bits 2:1
Field of the MSA .......................................................................................................................................98
Figure 2-33: Stacked Top, Bottom Stereo Format with Left View on Top and Right View on Bottom ...........99
Figure 2-34: VSC Packet Over the Main Link ................................................................................................100
Figure 2-35: Extension Packet Mapping Over the Main Link.........................................................................100
Figure 2-36: Block Diagram of a RS (15:13) Encoder ....................................................................................102
Figure 2-37: ECC Block Nibble-Interleaving for 2- and 4-Lane Main Links .................................................104
Figure 2-38: ECC Block Nibble-Interleaving for a 1-Lane Main Link ...........................................................104
Figure 2-39: ECC Block Nibble-Interleaving for 2- and 4-Lane Main Links (Header) ..................................105
Figure 2-40: ECC Block Nibble-Interleaving for a 1-Lane Main Link (Header) ............................................105
Figure 2-41: Makeup of 15 Nibble Code-Word for Packet Payload................................................................106
Figure 2-42: Makeup of 15 Nibble Code-Word for Packet Header.................................................................106
Figure 2-43: AUX CH uPacket TX State Diagram..........................................................................................108
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 10 of 515Figure 2-44: AUX CH uPacket RX State Diagram .........................................................................................109
Figure 2-45: DisplayPort Data Transport Channels.........................................................................................114
Figure 2-46: DP1.2 Multi-Stream Transport....................................................................................................115
Figure 2-47: Illustration of Link, Path, Virtual Channel..................................................................................116
Figure 2-48: Single Stream Source to Two Stream Sinks (“Dual Display Clone”).........................................116
Figure 2-49: Two Stream Sources to Two Stream Sinks (“Extended Desktop”) ............................................117
Figure 2-50: SST Isochronous Transport Service Layers................................................................................118
Figure 2-51: MST Isochronous Transport Service Layers...............................................................................119
Figure 2-52: Sideband CH Communication Layers.........................................................................................121
Figure 2-53: Branching Unit............................................................................................................................123
Figure 2-54: MST Multi-sink Device with Multiple Main Stream Sinks and SDP Sinks ...............................124
Figure 2-55: MST Sink Device with Single Main Stream Sink and Multiple SDP Sinks...............................124
Figure 2-56: MST Audio-only Sink Device with SDP Sinks ..........................................................................125
Figure 2-57: Example MST (Multi-stream Transport) Topology....................................................................126
Figure 2-58: Example Topology with RAD of Devices Relative to Source Devices ......................................127
Figure 2-59: MST Topology with a Loop and a Parallel Path.........................................................................130
Figure 2-60: Layers Covered in this Section ...................................................................................................131
Figure 2-61: Logical Block Diagram of MST DP Source Device ...................................................................133
Figure 2-62: Logical Block Diagram of MST DP Sink Device.......................................................................134
Figure 2-63: Logical Block Diagram of MST DP Branch Device...................................................................134
Figure 2-64: Logical Block Diagram of SST DP Source Device ....................................................................135
Figure 2-65: Logical Block Diagram of SST DP Sink Device ........................................................................135
Figure 2-66: Link Timing Generation in MST Mode ......................................................................................136
Figure 2-67: Time Slot Allocation to VC Payload...........................................................................................137
Figure 2-68: VC Payload Symbol Generator of a DP Source Device .............................................................138
Figure 2-69: 4-symbol Sequence Unit Mapping to Main Link lanes...............................................................138
Figure 2-70: Repetition of 4-symbol Sequence Unit Example for 1-lane Main Link......................................139
Figure 2-71: AV Stream Mapping in MST Mode After VC Payloads for a Given Main Video Stream are
Concatenated and VC Payload Fill (VCPF) Symbol Sequences Removed .............................................141
Figure 2-72: DP Source Device VC Payload Mapping Logical Block Diagram.............................................142
Figure 2-73: DP Sink Device VC Payload Mapping Logical Block Diagram.................................................142
Figure 2-74: Pass-through DP Branch Device VC Payload Mapping Logical Block Diagram.......................142
Figure 2-75: SDP Splitting...............................................................................................................................144
Figure 2-76: Bandwidth Management by Payload Bandwidth Manager.........................................................145
Figure 2-77: ACT Allocation Change Trigger Sequence ................................................................................152
Figure 2-78: VC Payload Allocation Change ..................................................................................................153
Figure 2-79: Example Time Sequence for Adding a New Payload .................................................................155
Figure 2-80: Timing Sequence for Adding a New Payload with Error ...........................................................156
Figure 2-81: Timing Sequence for Deleting a Payload....................................................................................157
Figure 2-82: Timing Sequence for Deleting a Payload with an Error .............................................................158
Figure 2-83: Timing Sequence for Deleting a Payload with Locally Unrecoverable Error.............................159
Figure 2-84: Timing Sequence for Reducing the VC Payload Allocation.......................................................160
Figure 2-85: Timing Sequence for Increasing the VC Payload Allocation .....................................................161
Figure 2-86: MSTM ECF and LVP Signaling at Link Frame Boundary.........................................................168
Figure 2-87: ECF Immediately Prior to ACT Sequence.................................................................................168
Figure 2-88: Examples of AUX CH Bridging Two I2
C Buses ........................................................................176
Figure 2-89: Action Flow Sequences of the Source upon HPD Event (Informative)......................................204
Figure 2-90: Messaging AUX Client in DP Nodes..........................................................................................258
Figure 2-91: Messaging AUX Client Layers ...................................................................................................259
Figure 2-92: Down Request Message and Down Reply Message ...................................................................260
Figure 2-93: Up Request Message and Up Reply Message.............................................................................260
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 11 of 515Figure 2-94: Mapping Message Transaction to Multiple Sideband MSGs (SB MSG CRC is the
Sideband_MSG_Data_CRC field.)..........................................................................................................269
Figure 2-95: RAD Update Along the Path Using Example Topology.............................................................275
Figure 2-96: AUX CH Error While Delivering a Down Req Message ...........................................................280
Figure 2-97: AUX CH Error While Delivering an Up Req Message ..............................................................281
Figure 2-98: Source Device Delay Aggregation and Introduction of Delay Stamps.......................................298
Figure 2-99: DisplayPort Monitor Connected Through a Repeater Device.....................................................299
Figure 2-100: Delay Compensation for Audio-to-Video Synchronization......................................................300
Figure 2-101: DisplayPort Source Streaming Audio-to-Video Streams to Multiple Monitors .......................301
Figure 2-102: Delay Compensation for Audio-to-Video Sync in a Multi-Monitor Configuration..................302
Figure 2-103: Delay Compensation for Audio-to-Audio Sync........................................................................303
Figure 2-104: GTC Value Measurement Point by GTC Master When AUX CH Running in Manchester
Transaction Format ..................................................................................................................................305
Figure 2-105: Using the C Field of the Audio Sampling Packet for GTC Transmission ................................308
Figure 3-1: DisplayPort Physical Layer...........................................................................................................309
Figure 3-2: Compliance Measurement Points of the Channel .........................................................................312
Figure 3-3: Compliance Test Load ..................................................................................................................312
Figure 3-4: HBR2 Upstream Device Compliance Test Configuration ............................................................313
Figure 3-5: HBR2 Downstream Device Compliance Test Configuration .......................................................314
Figure 3-6: HBR Upstream Device Compliance Test Configuration ..............................................................314
Figure 3-7: HBR Downstream Device Compliance Test Configuration .........................................................315
Figure 3-8: HBR Tethered Downstream Device Compliance Test Configuration ..........................................315
Figure 3-9: RBR Upstream Device Compliance Test Configuration ..............................................................315
Figure 3-10: RBR Downstream Device Compliance Test Configuration........................................................316
Figure 3-11: RBR Tethered Downstream Device Compliance Test Configuration ........................................316
Figure 3-12: FAUX Forward Channel Transmitter Compliance Test Configuration......................................317
Figure 3-13: FAUX Forward Channel Receiver Compliance Test Configuration ..........................................317
Figure 3-14: FAUX Forward Channel Tethered Receiver Compliance Test Configuration ...........................318
Figure 3-15: FAUX Back Channel Transmitter Compliance Test Configuration ...........................................318
Figure 3-16: FAUX Back Channel Receiver Compliance Test Configuration................................................319
Figure 3-17: Definition of Differential Voltage and Differential Voltage Peak-to-Peak.................................319
Figure 3-18: Example of Pre-emphasis............................................................................................................321
Figure 3-19: Feed-Forward Equalizer (FFE) Model........................................................................................322
Figure 3-20: Example of Pre-emphasis with Post Cursor2..............................................................................323
Figure 3-21: Character to Symbol Mapping ....................................................................................................324
Figure 3-22: AUX CH Differential Pair ..........................................................................................................329
Figure 3-23: Self-clocking with Manchester-II Coding...................................................................................329
Figure 3-24: AUX CH SYNC Pattern and STOP Condition ...........................................................................331
Figure 3-25: FAUX Forward Channel Training ..............................................................................................335
Figure 3-26: FAUX Back Channel Training....................................................................................................338
Figure 3-27: FAUX Forward Channel Receiver Jitter Output/Input Tolerance Mask.....................................345
Figure 3-28: FAUX Back Channel Receiver Jitter Output/Input Tolerance Mask..........................................346
Figure 3-29: AUX CH EYE Mask for Manchester Transactions at Connector Pins of Transmitting Device.347
Figure 3-30: AUX CH EYE Mask for Manchester Transactions at Connector Pins of Receiving Device .....348
Figure 3-31: EYE Mask for FAUX Transactions ............................................................................................350
Figure 3-32: Clock Recovery Sequence of Link Training...............................................................................358
Figure 3-33: Channel Equalization Sequence of Link Training ......................................................................360
Figure 3-34: Main Link Differential Pair.........................................................................................................362
Figure 3-35: HBR2 Receiver Jitter Output/Input Tolerance Mask..................................................................368
Figure 3-36: High Bit Rate Jitter Output/Input Tolerance Mask .....................................................................369
Figure 3-37: Reduced Bit Rate Jitter Output/Input Tolerance Mask ...............................................................370
Figure 3-38: EYE Mask at Upstream Device Connector Pins.........................................................................373
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 12 of 515Figure 3-39: Downstream Device Mask at TP3 (RBR) or TP3_EQ (HBR)....................................................374
Figure 3-40: Reference HBR Receiver Equalizer Transfer Function ..............................................................376
Figure 3-41: Reference HBR2 Receiver Equalizer Transfer Function ............................................................377
Figure 4-1: Type C1 Cable Assembly..............................................................................................................380
Figure 4-2: Type C2 Cable Assembly..............................................................................................................380
Figure 4-3: Type C3 Cable Assembly..............................................................................................................380
Figure 4-4: Type A1 Resizing Adaptor............................................................................................................381
Figure 4-5: Type A2 Resizing Adaptor............................................................................................................381
Figure 4-6: Type E1 Extension Cable..............................................................................................................382
Figure 4-7: Bulk Cable Construction (Informative - for Reference Only) ......................................................383
Figure 4-8: Differential Impedance Profile Measurement Data Example .......................................................385
Figure 4-9: Mini DP Differential Impedance Profile Measurement Data Example ........................................386
Figure 4-10: Mixed Mode Differential Insertion Loss for HBR Cable Assembly Type C1, C2 and C3.........387
Figure 4-11: Mixed Mode Differential Insertion Loss for HBR Resizing Adaptor.........................................388
Figure 4-12: Mixed Mode Differential Insertion Loss for Extension Cable....................................................389
Figure 4-13: Mixed Mode Differential RL for HBR Cable Assembly/Adaptor (DP Connector)....................390
Figure 4-14: Mixed Mode Differential RL for HBR Cable Assembly/Adaptor (mDP Connector).................391
Figure 4-15: Near-End Total Noise (peak) for High Bit Rate Cable Assembly ..............................................392
Figure 4-16: Power Sum Equal Level Far-End Total Noise (peak) for High Bit Rate Cable Assembly.........394
Figure 4-17: Intra-Pair Skew Measurement Method .......................................................................................395
Figure 4-18: Inter-Pair Skew Measurement Method .......................................................................................396
Figure 4-19: Mixed Mode Differential Insertion Loss (SDD21) Mask of Reduced Bit Rate Cable ...............397
Figure 4-20: Mixed Mode Differential Return Loss (SDD11) of Reduced Bit Rate Cable.............................398
Figure 4-21: Near-End Total Noise (peak) for Reduced Bit Rate Cable Assembly ........................................399
Figure 4-22: Far-End Total Noise (peak) for Reduced Bit Rate Cable Assembly...........................................400
Figure 4-23: External Cable Connector Assembly Wiring..............................................................................403
Figure 4-24: Connector Mating Levels............................................................................................................404
Figure 4-25: DisplayPort External Connector Drawings.................................................................................407
Figure 4-26: DisplayPort External Cable-Connector Assembly Drawings .....................................................408
Figure 4-27: Recommended Orientation of External Connector .....................................................................409
Figure 4-28: Plug Over-Mold Dimensions for Non-Latch Plug Connector.....................................................409
Figure 4-29: Fully-Mated Condition for DisplayPort External Connectors ....................................................410
Figure 4-30: Recommended PCB Layout for DisplayPort External Connector ..............................................411
Figure 4-31: Reference Design for Four DisplayPort External Connectors on a PCI Card.............................412
Figure 4-32: Panel Cut Out Reference Dimensions.........................................................................................412
Figure 4-33: Mini DisplayPort Cable Connector Assembly Wiring................................................................416
Figure 4-34: Mini DisplayPort-to-DisplayPort Cable Connector Assembly Wiring.......................................418
Figure 4-35: DisplayPort-to-Mini DisplayPort Cable Connector Assembly Wiring.......................................419
Figure 4-36: Mini DisplayPort-to-DisplayPort Adaptor Wiring......................................................................421
Figure 4-37: DisplayPort to Mini DisplayPort Adaptor Wiring ......................................................................423
Figure 4-38: Mini DisplayPort Cable Extender Wiring...................................................................................425
Figure 4-39: Mini DisplayPort Cable-Connector Dimensions – 1...................................................................429
Figure 4-40: Mini DisplayPort Cable-Connector Dimensions – 2...................................................................430
Figure 4-41: Mini DisplayPort Connector Dimensions - 1..............................................................................431
Figure 4-42: Mini DisplayPort Connector Dimensions – 2 .............................................................................432
Figure 4-43: Fully-Mated Mini DisplayPort Connector Showing Mating Levels ...........................................433
Figure 4-44: Recommended Mini DisplayPort Connector PCB Contacts and Mounting ...............................435
Figure 4-45: Reference Design for Four Mini DP Connectors on a Reduced Height PCI Card – 1................436
Figure 4-46: Reference Design for Four Mini DP Connectors on a Reduced Height PCI Card - 2 ................437
Figure 4-47: Panel-side Internal PCB Mount Receptacle Connector with Pin 1 Shown.................................440
Figure 4-48: Panel-side Internal PCB Mount Receptacle Connector (in unit of mm).....................................441
Figure 4-49: PCB Mount Connector Recommended Footprint Layout (in unit of mm) .................................442
VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Ver.1.2
©Copyright 2007-2010 Video Electronics Standards Association Page 13 of 515Figure 4-50: Panel-side Internal Cable Plug Connector (in unit of mm).........................................................442
Figure 4-51: Contact and Mechanical Guide Details (in unit of mm) .............................................................443
Figure 4-52: Mating Condition (Reference) of Panel Side Internal Cable Connector (mm) ...........................444
Figure 5-1: HPD Events...................................................................................................................................451
Figure 5-2: Sink Power State Machine ............................................................................................................456
Figure 5-3: Action Flow upon Addition of Sink Device..................................................................................461
Figure 6-1: Audio Stream Packets Transfer with No Video or During Video Vertical Blanking ...................466
Figure 6-2: Audio Stream Packets Transfer with Video during Video Vertical Active Period.......................466
Figure 9-1: AUX CH EYE Mask at Transmitting IC Package Pins (Informative)..........................................473
Figure 9-2: AUX CH EYE Mask at Receiving IC Package Pins (Informative) ..............................................474
Figure 9-3: FAUX Channel Topology Assumption.........................................................................................475
Figure 9-4: Effects on RX Silicon Eye with Different Aggresspor Setups......................................................477
Figure 12-1: Link Quality Management with Fast Link Training ...................................................................490
Figure 12-2: Link Quality Management Source Safe Mode............................................................................492
Figure 12-3: Link Quality Management Sink Power State Extension.............................................................493
Figure 13-1: Pixel Pattern Representation for Pixel Interleaved Method ........................................................497
Figure 13-2: Interleave Pattern Corresponding to 2-way Interleaved Stereo where Right Image Pixels are on
Even Lines ...............................................................................................................................................497
Figure 13-3: Interleave Pattern Corresponding to 2-way Interleaved Stereo Where Right Image Pixels are on
Even Lines ...............................................................................................................................................498
Figure 13-4: Interleave Pattern Corresponding to a Checker Board Pattern with Alternating Left and Right
Image Pixels.............................................................................................................................................498
Figure 13-5: Field Sequential Stereo Format with Left View and Right View Indicated via MISC1 Bits 2:1
Field of the MSA .....................................................................................................................................499
Figure 13-6: Stacked Top, Bottom Stereo Format with Left View on Top and Right View on Bottom .........499
Figure 14-1: QUERY_STREAM_ENCRYPTION _STATUS Message Transaction Execution when a Source
Device is Directly Connected to an MST Sink Device............................................................................508
Figure 14-2: QUERY_STREAM_ENCRYPTION _STATUS Message Transaction Forwarding and
Execution when a Source Device is Connected to a Sink Device via MST Branch Devices ..................508
Figure 14-3: QUERY_STREAM_ENCRYPTION _STATUS Message Transaction Forwarding and
Execution when L-to-L’ Verification Error Present ................................................................................509
标签： DP
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