实例介绍
【实例简介】PCIe标准规范6.0
【实例截图】
【核心代码】
Table of Contents
6.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
Page 3
PCIe Base 6.0 vs. 5.02.2.6.2 Transaction Descriptor - Transaction ID Field ................................................................................................153
2.2.6.3 Transaction Descriptor - Attributes Field........................................................................................................159
2.2.6.4 Relaxed Ordering and ID-Based Ordering Attributes .....................................................................................160
2.2.6.5 No Snoop Attribute..........................................................................................................................................161
2.2.6.6 Transaction Descriptor - Traffic Class Field ....................................................................................................161
2.2.7 Memory, I/O, and Configuration Request Rules .....................................................................................................162
2.2.7.1 Non-Flit Mode ..................................................................................................................................................162
2.2.7.1.1 TPH Rules.................................................................................................................................................166
2.2.7.2 Flit Mode ..........................................................................................................................................................168
2.2.8 Message Request Rules ...........................................................................................................................................170
2.2.8.1 INTx Interrupt Signaling - Rules ......................................................................................................................172
2.2.8.2 Power Management Messages........................................................................................................................176
2.2.8.3 Error Signaling Messages ................................................................................................................................177
2.2.8.4 Locked Transactions Support .........................................................................................................................178
2.2.8.5 Slot Power Limit Support ................................................................................................................................179
2.2.8.6 Vendor_Defined Messages ..............................................................................................................................180
2.2.8.6.1
⇅↓PCI-SIG-Defined↓ ⇅↕PCI-SIG Defined↕ VDMs ...................................................................................182
2.2.8.6.2 Device Readiness Status (DRS) Message.................................................................................................183
2.2.8.6.3 Function Readiness Status Message ( FRS Message ).............................................................................184
2.2.8.6.4 Hierarchy ID Message ..............................................................................................................................186
2.2.8.7 Ignored Messages ............................................................................................................................................188
2.2.8.8 Latency Tolerance Reporting (LTR) Message ..................................................................................................189
2.2.8.9 Optimized Buffer Flush/Fill (OBFF) Message ..................................................................................................190
2.2.8.10 Precision Time Measurement (PTM) Messages ..............................................................................................191
2.2.8.11 Integrity and Data Encryption (IDE) Messages ...............................................................................................194
2.2.9 Completion Rules ....................................................................................................................................................197
2.2.9.1 Completion Rules for Non-Flit Mode ..............................................................................................................198
2.2.9.2 Completion Rules for Flit Mode ......................................................................................................................200
2.2.10 TLP Prefix Rules .......................................................................................................................................................201
2.2.10.1 TLP Prefix General Rules - Non-Flit Mode.......................................................................................................201
2.2.10.2 Local TLP Prefix Processing.............................................................................................................................202
2.2.10.2.1 Vendor Defined Local TLP Prefix.............................................................................................................202
2.2.10.3 Flit Mode Local TLP Prefix ...............................................................................................................................202
2.2.10.4 End-End TLP Prefix Processing - Non-Flit Mode.............................................................................................203
2.2.10.4.1 Vendor Defined End-End TLP Prefix .......................................................................................................205
2.2.10.4.2 Root Ports with End-End TLP Prefix Supported.....................................................................................205
2.2.11 ⇅↓OHC-E↓ ⇅↕OHC-E↕ Rules - Flit Mode................................................................................................................205
2.3 Handling of Received TLPs..............................................................................................................................................207
2.3.1 Request Handling Rules ..........................................................................................................................................210
2.3.1.1 Data Return for Read Requests .......................................................................................................................216
2.3.2 Completion Handling Rules ....................................................................................................................................222
2.4 Transaction Ordering.......................................................................................................................................................225
2.4.1 Transaction Ordering Rules.....................................................................................................................................225
2.4.2 Update Ordering and Granularity Observed by a Read Transaction.....................................................................231
2.4.3 Update Ordering and Granularity Provided by a Write Transaction .....................................................................232
2.5 Virtual Channel (VC) Mechanism.....................................................................................................................................232
2.5.1 Virtual Channel Identification (VC ID) .....................................................................................................................235
2.5.2 TC to VC Mapping.....................................................................................................................................................236
2.5.3 VC and TC Rules .......................................................................................................................................................237
2.6 Ordering and Receive Buffer Flow Control .....................................................................................................................238
6.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
Page 4
PCIe Base 6.0 vs. 5.02.6.1 Flow Control (FC) Rules ...........................................................................................................................................239
2.6.1.1 FC Information Tracked by Transmitter..........................................................................................................245
2.6.1.2 FC Information Tracked by Receiver ...............................................................................................................249
2.7 End-to-End Data Integrity................................................................................................................................................255
2.7.1 ECRC Rules ...............................................................................................................................................................255
2.7.2 Error Forwarding (Data Poisoning) .........................................................................................................................260
2.7.2.1 Rules For Use of Data Poisoning .....................................................................................................................261
2.8 Completion Timeout Mechanism ...................................................................................................................................262
2.9 Link Status Dependencies ...............................................................................................................................................263
2.9.1 Transaction Layer Behavior in DL_Down Status ....................................................................................................263
2.9.2 Transaction Layer Behavior in DL_Up Status .........................................................................................................264
2.9.3 Transaction Layer Behavior During Downstream Port Containment....................................................................265
3. Data Link Layer Specification..........................................................................................................................................267
3.1 Data Link Layer Overview................................................................................................................................................267
3.2 Data Link Control and Management State Machine.......................................................................................................268
3.2.1 Data Link Control and Management State Machine Rules.....................................................................................269
3.3 Data Link Feature Exchange ............................................................................................................................................272
3.4 Flow Control Initialization Protocol................................................................................................................................274
3.4.1 Flow Control Initialization State Machine Rules.....................................................................................................274
3.4.2 Scaled Flow Control.................................................................................................................................................281
3.5 Data Link Layer Packets (DLLPs) .....................................................................................................................................282
3.5.1 Data Link Layer Packet Rules ..................................................................................................................................282
3.6 Data Integrity Mechanisms..............................................................................................................................................292
3.6.1 Introduction .............................................................................................................................................................292
3.6.2 LCRC, Sequence Number, and Retry Management (TLP Transmitter) ..................................................................293
3.6.2.1 LCRC and Sequence Number Rules (TLP Transmitter) ..................................................................................293
3.6.2.2 Handling of Received DLLPs (Non-Flit Mode).................................................................................................302
3.6.2.3 Handling of Received DLLPs (Flit Mode).........................................................................................................305
3.6.3 LCRC and Sequence Number (TLP Receiver) (Non-Flit Mode)...............................................................................306
3.6.3.1 LCRC and Sequence Number Rules (TLP Receiver)........................................................................................306
4. Physical Layer Logical Block ...........................................................................................................................................313
4.1 Introduction .....................................................................................................................................................................313
4.2 Logical Sub-block ............................................................................................................................................................313
4.2.1 8b/10b Encoding for 2.5 GT/s and 5.0 GT/s Data Rates...........................................................................................315
4.2.1.1 Symbol Encoding.............................................................................................................................................315
4.2.1.1.1 Serialization and De-serialization of Data ..............................................................................................316
4.2.1.1.2 Special Symbols for Framing and Link Management (K Codes)............................................................317
4.2.1.1.3 8b/10b Decode Rules...............................................................................................................................318
4.2.1.2 Framing and Application of Symbols to Lanes...............................................................................................319
4.2.1.2.1 Framing and Application of Symbols to Lanes for TLPs and DLLPs in Non-Flit Mode .........................319
4.2.1.3 Data Scrambling ..............................................................................................................................................323
4.2.2 128b/130b Encoding for 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s Data Rates.................................................................324
4.2.2.1 Lane Level Encoding........................................................................................................................................325
4.2.2.2 Ordered Set Blocks ..........................................................................................................................................327
4.2.2.2.1 Block Alignment ......................................................................................................................................327
4.2.2.3 Data Blocks ......................................................................................................................................................328
4.2.2.3.1 Framing Tokens in Non-Flit-Mode...........................................................................................................329
4.2.2.3.2 Transmitter Framing Requirements in Non-Flit Mode ...........................................................................334
6.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
Page 5
PCIe Base 6.0 vs. 5.04.2.2.3.3 Receiver Framing Requirements in Non-Flit Mode ................................................................................335
4.2.2.3.4 Receiver Framing Requirements in Flit Mode.........................................................................................338
4.2.2.3.5 Recovery from Framing Errors in Non-Flit Mode and Flit Mode ............................................................338
4.2.2.4 Scrambling in Non-Flit Mode and Flit Mode...................................................................................................339
4.2.2.5 Precoding .........................................................................................................................................................344
4.2.2.5.1 Precoding at 32.0 GT/s Data Rate ............................................................................................................345
4.2.2.6 Loopback with 128b/130b Code in Non-Flit Mode and Flit Mode .................................................................347
4.2.3 Flit Mode Operation.................................................................................................................................................347
4.2.3.1 1b/1b Encoding for 64.0 GT/s and higher Data Rates.....................................................................................347
4.2.3.1.1 PAM4 Signaling ........................................................................................................................................349
4.2.3.1.2 1b/1b Scrambling ....................................................................................................................................350
4.2.3.1.3 Gray Coding at 64.0 GT/s and Higher Data Rates....................................................................................351
4.2.3.1.4 Precoding at 64.0 GT/s and Higher Data Rates .......................................................................................352
4.2.3.1.5 Ordered Set Blocks at 64.0 GT/s and Higher Data Rates ........................................................................354
4.2.3.1.6 Alignment at Block/ Flit Level for 1b/1b Encoding.................................................................................355
4.2.3.2 Processing of Ordered Sets During Flit Mode Data Stream ...........................................................................356
4.2.3.3 Data Stream in Flit Mode .................................................................................................................................358
4.2.3.4 Bytes in Flit Layout ..........................................................................................................................................364
4.2.3.4.1 TLP Bytes in Flit .......................................................................................................................................364
4.2.3.4.2 DLP Bytes in Flit .......................................................................................................................................366
4.2.3.4.2.1 Flit Sequence Number and Retry Mechanism................................................................................369
4.2.3.4.2.1.1 IDLE Flit Handshake Phase .....................................................................................................375
4.2.3.4.2.1.2 Sequence Number Handshake Phase ....................................................................................376
4.2.3.4.2.1.3 Normal Flit Exchange Phase ...................................................................................................377
4.2.3.4.2.1.4 Received Ack and Nak Processing ..........................................................................................379
4.2.3.4.2.1.5 Ack, Nak, and Discard Rules....................................................................................................380
4.2.3.4.2.1.6 Flit Replay Scheduling.............................................................................................................385
4.2.3.4.2.1.7 Flit Replay Transmit Rules.......................................................................................................387
4.2.3.4.3 CRC Bytes in Flit .......................................................................................................................................391
4.2.3.4.4 ECC Bytes in Flit .......................................................................................................................................392
4.2.3.4.5 Ordered Set insertion in Data Stream in Flit Mode ................................................................................398
4.2.4 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates ..........................................................................399
4.2.4.1 Rules for Transmitter Coefficients ..................................................................................................................413
4.2.4.2 Encoding of Presets .........................................................................................................................................414
4.2.5 Link Initialization and Training ...............................................................................................................................415
4.2.5.1 Training Sequences .........................................................................................................................................416
4.2.5.2 Alternate Protocol Negotiation .......................................................................................................................435
4.2.5.3 Electrical Idle Sequences ( EIOS and EIEOS ) .................................................................................................438
4.2.5.4 Inferring Electrical Idle ....................................................................................................................................443
4.2.5.5 Lane Polarity Inversion....................................................................................................................................444
4.2.5.6 Fast Training Sequence ( FTS ) ........................................................................................................................445
4.2.5.7 Start of Data Stream Ordered Set ( SDS Ordered Set ) ...................................................................................447
4.2.5.8 Link Error Recovery .........................................................................................................................................447
4.2.5.9 Reset.................................................................................................................................................................448
4.2.5.9.1 Fundamental Reset .................................................................................................................................448
4.2.5.9.2 Hot Reset..................................................................................................................................................449
4.2.5.10 Link Data Rate Negotiation .............................................................................................................................449
4.2.5.11 Link Width and Lane Sequence Negotiation ..................................................................................................449
4.2.5.11.1 Required and Optional Port Behavior ....................................................................................................449
4.2.5.12 Lane-to-Lane De-skew.....................................................................................................................................450
6.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
Page 6
PCIe Base 6.0 vs. 5.04.2.5.13 Lane vs. Link Training ......................................................................................................................................451
4.2.6 Link Training and Status State Machine (LTSSM) Descriptions..............................................................................451
4.2.6.1 Detect Overview ..............................................................................................................................................452
4.2.6.2 Polling Overview..............................................................................................................................................452
4.2.6.3 Configuration Overview ..................................................................................................................................452
4.2.6.4 Recovery Overview ..........................................................................................................................................452
4.2.6.5 L0 Overview .....................................................................................................................................................453
4.2.6.6 L0s Overview....................................................................................................................................................453
4.2.6.7 L0p Overview ...................................................................................................................................................453
4.2.6.7.1 Link Management DLLP...........................................................................................................................455
4.2.6.8 L1 Overview .....................................................................................................................................................458
4.2.6.9 L2 Overview .....................................................................................................................................................458
4.2.6.10 Disabled Overview...........................................................................................................................................459
4.2.6.11 Loopback Overview.........................................................................................................................................459
4.2.6.12 Hot Reset Overview .........................................................................................................................................460
4.2.7 Link Training and Status State Rules ......................................................................................................................460
4.2.7.1 Detect ...............................................................................................................................................................462
4.2.7.1.1 Detect.Quiet.............................................................................................................................................462
4.2.7.1.2 Detect.Active............................................................................................................................................464
4.2.7.2 Polling ..............................................................................................................................................................464
4.2.7.2.1 Polling.Active ...........................................................................................................................................465
4.2.7.2.2 Polling.Compliance .................................................................................................................................466
4.2.7.2.3 Polling.Configuration ..............................................................................................................................471
4.2.7.2.4 Polling.Speed...........................................................................................................................................471
4.2.7.3 Configuration ...................................................................................................................................................472
4.2.7.3.1 Configuration.Linkwidth.Start ................................................................................................................472
4.2.7.3.1.1 Downstream Lanes ..........................................................................................................................472
4.2.7.3.1.2 Upstream Lanes...............................................................................................................................474
4.2.7.3.2 Configuration.Linkwidth.Accept .............................................................................................................476
4.2.7.3.2.1 Downstream Lanes ..........................................................................................................................476
4.2.7.3.2.2 Upstream Lanes...............................................................................................................................477
4.2.7.3.3 Configuration.Lanenum.Accept..............................................................................................................479
4.2.7.3.3.1 Downstream Lanes ..........................................................................................................................480
4.2.7.3.3.2 Upstream Lanes...............................................................................................................................481
4.2.7.3.4 Configuration.Lanenum.Wait..................................................................................................................482
4.2.7.3.4.1 Downstream Lanes ..........................................................................................................................482
4.2.7.3.4.2 Upstream Lanes...............................................................................................................................482
4.2.7.3.5 Configuration.Complete..........................................................................................................................483
4.2.7.3.5.1 Downstream Lanes ..........................................................................................................................483
4.2.7.3.5.2 Upstream Lanes...............................................................................................................................485
4.2.7.3.6 Configuration.Idle....................................................................................................................................487
4.2.7.4 Recovery...........................................................................................................................................................490
4.2.7.4.1 Recovery.RcvrLock ..................................................................................................................................490
4.2.7.4.2 Recovery.Equalization.............................................................................................................................497
4.2.7.4.2.1 Downstream Lanes ..........................................................................................................................498
4.2.7.4.2.1.1 Phase 1 of Transmitter Equalization.......................................................................................498
4.2.7.4.2.1.2 Phase 2 of Transmitter Equalization.......................................................................................500
4.2.7.4.2.1.3 Phase 3 of Transmitter Equalization.......................................................................................501
4.2.7.4.2.2 Upstream Lanes...............................................................................................................................504
4.2.7.4.2.2.1 Phase 0 of Transmitter Equalization.......................................................................................504
6.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
Page 7
PCIe Base 6.0 vs. 5.04.2.7.4.2.2.2 Phase 1 of Transmitter Equalization.......................................................................................506
4.2.7.4.2.2.3 Phase 2 of Transmitter Equalization.......................................................................................507
4.2.7.4.2.2.4 Phase 3 of Transmitter Equalization.......................................................................................509
4.2.7.4.3 Recovery.Speed .......................................................................................................................................510
4.2.7.4.4 Recovery.RcvrCfg.....................................................................................................................................511
4.2.7.4.5 Recovery.Idle ...........................................................................................................................................518
4.2.7.5 L0 ......................................................................................................................................................................521
4.2.7.6 L0s ....................................................................................................................................................................523
4.2.7.6.1 Receiver L0s .............................................................................................................................................523
4.2.7.6.1.1 Rx_L0s.Entry ....................................................................................................................................524
4.2.7.6.1.2 Rx_L0s.Idle.......................................................................................................................................524
4.2.7.6.1.3 Rx_L0s.FTS .......................................................................................................................................524
4.2.7.6.2 Transmitter L0s ........................................................................................................................................525
4.2.7.6.2.1 Tx_L0s.Entry ....................................................................................................................................525
4.2.7.6.2.2 Tx_L0s.Idle .......................................................................................................................................525
4.2.7.6.2.3 Tx_L0s.FTS .......................................................................................................................................525
4.2.7.7 L1 ......................................................................................................................................................................527
4.2.7.7.1 L1.Entry ....................................................................................................................................................527
4.2.7.7.2 L1.Idle.......................................................................................................................................................527
4.2.7.8 L2 ......................................................................................................................................................................528
4.2.7.8.1 L2.Idle.......................................................................................................................................................528
4.2.7.8.2 L2.TransmitWake .....................................................................................................................................529
4.2.7.9 Disabled ...........................................................................................................................................................529
4.2.7.10 Loopback .........................................................................................................................................................530
4.2.7.10.1 Loopback.Entry .......................................................................................................................................530
4.2.7.10.2 Loopback.Active ......................................................................................................................................535
4.2.7.10.3 Loopback.Exit ..........................................................................................................................................536
4.2.7.11 Hot Reset..........................................................................................................................................................537
4.2.8 Clock Tolerance Compensation ..............................................................................................................................538
4.2.8.1 SKP Ordered Set for 8b/10b Encoding............................................................................................................539
4.2.8.2 SKP Ordered Set for 128b/130b Encoding......................................................................................................539
4.2.8.3 SKP Ordered Set for 1b/1b Encoding..............................................................................................................543
4.2.8.4 Rules for Transmitters .....................................................................................................................................547
4.2.8.5 Rules for Receivers...........................................................................................................................................550
4.2.9 Compliance Pattern in 8b/10b Encoding................................................................................................................550
4.2.10 Modified Compliance Pattern in 8b/10b Encoding ................................................................................................551
4.2.11 Compliance Pattern in 128b/130b Encoding..........................................................................................................553
4.2.12 Modified Compliance Pattern in 128b/130b Encoding ..........................................................................................555
4.2.13 Jitter Measurement Pattern in 128b/130b..............................................................................................................556
4.2.14 Compliance Pattern in 1b/1b Encoding..................................................................................................................556
4.2.15 Modified Compliance Pattern in 1b/1b Encoding ..................................................................................................557
4.2.16 Jitter Measurement Pattern in 1b/1b Encoding .....................................................................................................557
4.2.17 Toggle Patterns in 1b/1b encoding .........................................................................................................................558
4.2.18 Lane Margining at Receiver .....................................................................................................................................558
4.2.18.1 Receiver Number, Margin Type, Usage Model, and Margin Payload Fields...................................................559
4.2.18.1.1 Step Margin Execution Status .................................................................................................................564
4.2.18.1.2 Margin Payload for Step Margin Commands ..........................................................................................564
4.2.18.2 Margin Command and Response Flow ...........................................................................................................565
4.2.18.3 Receiver Margin Testing Requirements ..........................................................................................................568
4.3 Retimers ...........................................................................................................................................................................572
6.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
Page 8
PCIe Base 6.0 vs. 5.04.3.1 Retimer Requirements ............................................................................................................................................573
4.3.2 Supported Retimer Topologies...............................................................................................................................574
4.3.3 Variables...................................................................................................................................................................575
4.3.4 Receiver Impedance Propagation Rules.................................................................................................................576
4.3.5 Switching Between Modes ......................................................................................................................................576
4.3.6 Forwarding Rules.....................................................................................................................................................576
4.3.6.1 Forwarding Type Rules....................................................................................................................................577
4.3.6.2 Orientation, Lane Numbers, and Data Stream Mode Rules...........................................................................577
4.3.6.3 Electrical Idle Exit Rules ..................................................................................................................................578
4.3.6.4 Data Rate Change and Determination Rules ..................................................................................................581
4.3.6.5 Electrical Idle Entry Rules................................................................................................................................581
4.3.6.6 Transmitter Settings Determination Rules .....................................................................................................582
4.3.6.7 Ordered Set Modification Rules ......................................................................................................................585
4.3.6.8 DLLP, TLP, Logical Idle, and Flit Modification Rules .......................................................................................587
4.3.6.9 8b/10b Encoding Rules....................................................................................................................................587
4.3.6.10 8b/10b Scrambling Rules ................................................................................................................................587
4.3.6.11 Hot Reset Rules................................................................................................................................................588
4.3.6.12 Disable Link Rules............................................................................................................................................588
4.3.6.13 Loopback .........................................................................................................................................................588
4.3.6.14 Compliance Receive Rules ..............................................................................................................................590
4.3.6.15 Enter Compliance Rules ..................................................................................................................................591
4.3.7 Execution Mode Rules .............................................................................................................................................594
4.3.7.1 CompLoadBoard Rules....................................................................................................................................594
4.3.7.1.1 CompLoadBoard.Entry ...........................................................................................................................594
4.3.7.1.2 CompLoadBoard.Pattern ........................................................................................................................594
4.3.7.1.3 CompLoadBoard.Exit ..............................................................................................................................595
4.3.7.2 Link Equalization Rules ...................................................................................................................................596
4.3.7.2.1 Downstream Lanes ..................................................................................................................................596
4.3.7.2.1.1 Phase 1 .............................................................................................................................................596
4.3.7.2.1.2 Phase 2 .............................................................................................................................................596
4.3.7.2.1.3 Phase 3 Active ..................................................................................................................................596
4.3.7.2.1.4 Phase 3 Passive................................................................................................................................597
4.3.7.2.2 Upstream Lanes.......................................................................................................................................597
4.3.7.2.2.1 Phase 0 .............................................................................................................................................597
4.3.7.2.2.2 Phase 1 Active ..................................................................................................................................597
4.3.7.2.2.3 Phase 2 Active ..................................................................................................................................597
4.3.7.2.2.4 Phase 2 Passive................................................................................................................................598
4.3.7.2.2.5 Phase 3 .............................................................................................................................................598
4.3.7.2.3 Force Timeout..........................................................................................................................................598
4.3.7.3 Follower Loopback ..........................................................................................................................................599
4.3.7.3.1 Follower Loopback.Entry ........................................................................................................................599
4.3.7.3.2 Follower Loopback.Active.......................................................................................................................599
4.3.7.3.3 Follower Loopback.Exit...........................................................................................................................599
4.3.8 Retimer Latency.......................................................................................................................................................600
4.3.8.1 Measurement ...................................................................................................................................................600
4.3.8.2 Maximum Limit on Retimer Latency...............................................................................................................600
4.3.8.3 Impacts on Upstream and Downstream Ports ...............................................................................................600
4.3.9 SRIS ..........................................................................................................................................................................600
4.3.10 L1 PM Substates Support ........................................................................................................................................602
4.3.11 Retimer Configuration Parameters .........................................................................................................................604
6.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
Page 9
PCIe Base 6.0 vs. 5.06.0-1.0-PUB — PCI Express® Base Specification Revision 6.0
4.3.11.1 Global Parameters ...........................................................................................................................................605
4.3.11.2 Per Physical Pseudo Port Parameters.............................................................................................................605
4.3.12 In Band Register Access ...........................................................................................................................................606
5. Power Management.........................................................................................................................................................609
5.1 Overview ..........................................................................................................................................................................609
5.2 Link State Power Management .......................................................................................................................................610
5.3 PCI-PM Software Compatible Mechanisms ....................................................................................................................614
5.3.1 Device Power Management States (D-States) of a Function..................................................................................614
5.3.1.1 D0 State ............................................................................................................................................................615
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