DP2.0标准

【实例截图】

【核心代码】

Contents
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Support for this Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Acknowledgments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.1 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
1.2 DisplayPort Objectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
1.2.1 Key Industry Needs for DisplayPort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
1.2.2 Technical Objectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
1.2.3 External Connection Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
1.2.4 Internal Connection Objectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
1.2.5 CE Connection Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
1.2.6 Content Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
1.2.7 DP v2.0 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
1.3 Acronyms and Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
1.4 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
1.5 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
1.5.1 Precedence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
1.5.2 Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
1.5.3 Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
1.5.4 Bit and Byte Ordering Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
1.6 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
1.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
1.7.1 Main-Link Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
1.7.2 AUX_CH Composition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
1.7.3 Link Configuration and Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
1.7.4 Layered Modular Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Section 2 Link Layer Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.1 SST Mode with 8b/10b Link Layer Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.1.1 Number of Lanes and Per-lane Data Rate in SST and MST Modes. . . . . . . . .84
2.1.2 Number of Main, Uncompressed Video Streams in SST Mode. . . . . . . . . . . .85
2.1.3 Basic Functions in SST and MST Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
2.1.4 DP Device Types and Link Topology in SST Mode . . . . . . . . . . . . . . . . . . . .86
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2.2 Isochronous Transport Services in SST Mode
with 8b/10b Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
2.2.1 Main Video Stream to Main-Link Lane Mapping in the Source Device . . . . .92
2.2.2 Stream Reconstruction in the Sink Device . . . . . . . . . . . . . . . . . . . . . . . . . . .145
2.2.3 Stream Clock Regeneration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
2.2.4 MSA Data Transport. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
2.2.5 SDP Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
2.2.6 ECC for SDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
2.3 AUX_CH States and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
2.3.1 AUX_CH States Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
2.3.2 Link Layer Arbitration Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
2.3.3 Policy Maker AUX Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
2.3.4 Detailed DPTX AUX_CH State and Event Descriptions. . . . . . . . . . . . . . . .236
2.3.5 Detailed DPRX AUX_CH State and Event Descriptions. . . . . . . . . . . . . . . .237
2.4 DP Multi-stream Isochronous Transport Service Overview . . . . . . . . . . . . . . . . . . . .238
2.4.1 Connection-oriented Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
2.4.2 DP Isochronous Transport Service Layers . . . . . . . . . . . . . . . . . . . . . . . . . . .242
2.4.3 Sideband CH Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
2.5 Topology Management Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
2.5.1 Primitives of Multi-stream DP Devices and Device Types . . . . . . . . . . . . . .248
2.5.2 Multi-stream Topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
2.5.3 Multi-Stream Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
2.5.4 Topology Manager and Topology Assistant. . . . . . . . . . . . . . . . . . . . . . . . . .254
2.5.5 Topology Discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
2.5.6 Topology Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
2.5.7 Topologies with Single-stream-only Source devices . . . . . . . . . . . . . . . . . . .256
2.5.8 Loop Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
2.6 MST Mode 8b/10b Link Layer Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
2.6.1 Path Constraint Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
2.6.2 Link Timing Generation Based on MST Packet. . . . . . . . . . . . . . . . . . . . . . .273
2.6.3 Symbol Sequence Mapping into VC Payload. . . . . . . . . . . . . . . . . . . . . . . . .274
2.6.4 Time Slot Count Allocation to VC Payload . . . . . . . . . . . . . . . . . . . . . . . . . .285
2.6.5 VC Payload Allocation Synchronization Management . . . . . . . . . . . . . . . . .294
2.6.6 ALLOCATE_PAYLOAD Timing Sequence . . . . . . . . . . . . . . . . . . . . . . . . .299
2.6.7 Impacts of Various Events on VC Payload ID Table . . . . . . . . . . . . . . . . . . .307
2.6.8 Robustness Mandate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
2.6.9 Control Functions, Control Link Symbols, and K-code Assignment. . . . . . .311
2.6.10 Conversion between MST and SST Symbol Mapping. . . . . . . . . . . . . . . . . .313
2.6.11 MTPH Usages for CP Extension in MST Mode. . . . . . . . . . . . . . . . . . . . . . .315
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2.7 Stream Data-to-Link Symbol Mapping with 128b/132b Link Layer. . . . . . . . . . . . . .317
2.7.1 32-bit Link Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
2.7.2 Mapping to MTPs and Link Layer Frames. . . . . . . . . . . . . . . . . . . . . . . . . . .324
2.7.3 Link Layer Control Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
2.7.4 MSA Packet and VB-ID Mapping to 32-bit Link Symbols . . . . . . . . . . . . . .326
2.7.5 SDP Mapping to 32-bit Link Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
2.7.6 Time Slot Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
2.7.7 32-bit Link Symbol Content Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
2.7.8 Place Holder Symbol Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
2.8 Compressed Display Stream Transport Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
2.8.1 Transport Buffer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
2.8.2 DSC Bitstream Transport over DP SST/MST Link . . . . . . . . . . . . . . . . . . . .338
2.8.3 DSC Configuration – Discovery, Enabling, and Disabling . . . . . . . . . . . . . .340
2.8.4 Minimum Slices/Display Line Mandate . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
2.8.5 CRCs for DSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
2.8.6 DSC Bitstream Transport of 3D Stereo Video . . . . . . . . . . . . . . . . . . . . . . . .358
2.8.7 DSC Bitstream Mapping to 128b/132b Link Layer Link Symbols . . . . . . . .360
2.8.8 DSC Bitstream Pass-through across a DP Branch Device . . . . . . . . . . . . . . .361
2.9 DSC Support Mandate for 128b/132b Link Layer-capable DP Devices. . . . . . . . . . .362
2.9.1 DSC Support Mandates for a DP Source Device with
a 128b/132b Link Layer-capable DFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
2.9.2 DSC Support Mandates for a DP Sink Device with
a 128b/132b Link Layer-capable UFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
2.9.3 DSC Support Mandates for a DP Branch Device with
a 128b/132b Link Layer-capable UFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
2.10 DSC Capability, DSC Extended Capability, DSC Configuration,
and DFP Capability Extension DPCD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
2.10.1 DSC Capability and DSC Extended Capability DPCD Registers . . . . . . . . .370
2.10.2 DSC CONFIGURATION DPCD Register. . . . . . . . . . . . . . . . . . . . . . . . . . .371
2.10.3 DFP Capability Extension DPCD Registers. . . . . . . . . . . . . . . . . . . . . . . . . .371
2.10.4 DP Branch Device DSC Decoder Configuration Examples. . . . . . . . . . . . . .372
2.11 AUX Transaction Syntax in Manchester Transaction Format. . . . . . . . . . . . . . . . . . .377
2.11.1 Command Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
2.11.2 AUX Transaction Response/Reply Timeouts. . . . . . . . . . . . . . . . . . . . . . . . .382
2.11.3 Native AUX Request Transaction Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . .382
2.11.4 Native AUX Reply Transaction Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
2.11.5 I 2 C Bus Transaction Mapping onto AUX Syntax. . . . . . . . . . . . . . . . . . . . . .384
2.11.6 Conversion of I 2 C Transaction to Native AUX Transaction (Informative) . .405
2.11.7 I 2 C-over-AUX Transaction Clarifications and Implementation Rules. . . . . .406
2.12 AUX Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
2.12.1 Stream Transport Initiation Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
2.12.2 Stream Transport Termination Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
2.12.3 DPCD Field Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
2.12.4 AUX Link Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .594
2.12.5 AUX Device Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605
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2.13 Alternate Scrambler Reset for eDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606
2.13.1 Protocol Differentiation Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606
2.13.2 Symbol Error Rate Measurement Pattern Output (Informative). . . . . . . . . . .606
2.14 Messaging AUX Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608
2.14.1 Messaging AUX Client Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610
2.14.2 Message Transaction Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612
2.14.3 Sideband MSG Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .622
2.14.4 AUX Support for Messaging AUX Client . . . . . . . . . . . . . . . . . . . . . . . . . . .628
2.14.5 RAD Updated by MST Devices in the Path . . . . . . . . . . . . . . . . . . . . . . . . . .631
2.14.6 Broadcast Message Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .632
2.14.7 Message Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633
2.14.8 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .638
2.14.9 Descriptions of Available Message Transaction Requests . . . . . . . . . . . . . . .641
2.15 Audio-to-video and Audio-to-audio Synchronization . . . . . . . . . . . . . . . . . . . . . . . . .662
2.15.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662
2.15.2 DP AV Sync Data Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663
2.15.3 Delay Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .664
2.16 GTC and Audio Inter-channel Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .671
2.16.1 GTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .671
2.16.2 Application of GTC for Audio Inter-channel Synchronization . . . . . . . . . . .685
2.17 Panel Replay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .687
2.17.1 Comparison to Panel Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .687
2.17.2 Applicability of Panel Replay Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688
2.17.3 Video Timing, HDCP, and Audio Streaming in Panel Replay Mode. . . . . . .689
2.17.4 Panel Replay Mode Enumeration and Configuration. . . . . . . . . . . . . . . . . . .690
2.17.5 VSC SDP Use for Panel Replay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .691
2.17.6 Transition between Live Active Frame and Panel Replay Modes . . . . . . . . .694
2.17.7 Panel Replay with no Live Active Frame Update. . . . . . . . . . . . . . . . . . . . . .697
2.17.8 Full-screen Live Active Frame Update in Panel Replay Mode . . . . . . . . . . .698
2.17.9 Selective Update in Panel Replay Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .699
2.17.10 Data Integrity and RFB Storage Error Check and Corrective Action. . . . . . .700
2.17.11 DPCD Registers Used for Panel Replay. . . . . . . . . . . . . . . . . . . . . . . . . . . . .701
Section 3 PHY Layer Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .702
3.1.1 PHY Layer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .702
3.1.2 Link-PHY Layer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .704
3.1.3 PHY Layer and Link Media Interface Signals . . . . . . . . . . . . . . . . . . . . . . . .704
3.1.4 Main-Link Compliance Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .706
3.1.5 Electrical Signal Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .707
3.1.6 8b/10b Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .710
3.1.7 8b/10b Symbol Coding and Serialization/De-serialization. . . . . . . . . . . . . . .711
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3.2 DP_PWR for Box-to-Box DP Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713
3.2.1 DP_PWR User Detection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715
3.2.2 DP_PWR Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715
3.2.3 Inrush Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715
3.2.4 Voltage Droop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716
3.2.5 Over-current Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716
3.3 Hot Plug/Unplug Detect Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .717
3.4 AUX_CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .720
3.4.1 AUX_CH Logical Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .721
3.4.2 AUX_CH Electrical Sub-block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723
3.5 Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .731
3.5.1 Main-Link 8b/10b PHY Logical Sub-layer. . . . . . . . . . . . . . . . . . . . . . . . . . .731
3.5.2 Main-Link 128b/132b PHY Logical Sub-layer. . . . . . . . . . . . . . . . . . . . . . . .772
3.5.3 Main-Link PHY Logical Sublayer FEC- and PHY Test-related Registers. . .812
3.5.4 8b/10b Main-Link Electrical Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . .822
3.5.5 128b/132b Main-Link PHY Electrical Sub-block. . . . . . . . . . . . . . . . . . . . . .852
3.5.6 ESD and EOS Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .874
3.6 LTTPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .875
3.6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .875
3.6.2 Signal Routing Mandates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .878
3.6.3 LTTPR DPCD Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .879
3.6.4 LTTPR DPCD Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .881
3.6.5 AUX Transaction Handling Mandates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .883
3.6.6 Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .889
3.6.7 Transition to Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .907
3.6.8 Dual Mode Mandates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .908
3.6.9 LTTPR Electrical Specification Mandates . . . . . . . . . . . . . . . . . . . . . . . . . . .908
3.6.10 LTTPR Power-saving State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .909
Section 4 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
4.1 Cable-Connector Assembly Specifications (for Box-to-box) . . . . . . . . . . . . . . . . . . .911
4.1.1 Cable-Connector Assembly Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .912
4.1.2 Bulk Cable Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .916
4.1.3 Impedance Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .917
4.1.4 Insertion Loss and Return Loss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .920
4.1.5 High Bit Rate Cable-Connector Assembly Specification. . . . . . . . . . . . . . . .921
4.1.6 Reduced Bit Rate Cable-Connector Assembly Specification. . . . . . . . . . . . .931
4.1.7 DP8K Cable Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .935
4.1.8 Bulk Cable and Connector Impedance (Normative). . . . . . . . . . . . . . . . . . . .939
4.2 Connector Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .940
4.2.1 External Full-size Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .940
4.2.2 mDP External Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .953
4.2.3 Panel-side Internal Connector (Informative) . . . . . . . . . . . . . . . . . . . . . . . . .974
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Section 5 Source/Sink/Branch Device Policy Requirements for Interoperability . . . . . . . 983
5.1 DP SST Source Device with 8b/10b Channel Coding. . . . . . . . . . . . . . . . . . . . . . . . .983
5.1.1 Stream Source Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .983
5.1.2 Source Device Link Configuration Requirement . . . . . . . . . . . . . . . . . . . . . .988
5.1.3 Source Device Behavior on Stream Timing Change . . . . . . . . . . . . . . . . . . .990
5.1.4 Source Device Behavior upon HPD Pulse Detection . . . . . . . . . . . . . . . . . . .991
5.1.5 Downstream Device DPRX Power Management by a Source Device. . . . . .992
5.1.6 Source Device Connected to a Branch Device . . . . . . . . . . . . . . . . . . . . . . . .993
5.1.7 Source Device DSC Bitstream Transport and FEC Policy. . . . . . . . . . . . . . .995
5.1.8 Horizontal Blanking Expansion Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .995
5.2 DP SST Sink Device with 8b/10b Channel Coding. . . . . . . . . . . . . . . . . . . . . . . . . . .996
5.2.1 Stream Sink Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .996
5.2.2 Sink Device Link Configuration Requirement . . . . . . . . . . . . . . . . . . . . . . . .997
5.2.3 Sink Device Behavior on Stream Timing Change . . . . . . . . . . . . . . . . . . . . .999
5.2.4 Toggling of HPD Signal for Status Change Notification . . . . . . . . . . . . . . . .999
5.2.5 Sink Device DPRX Power State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000
5.2.6 Sink Device DSC Bitstream Handling and FEC Policy . . . . . . . . . . . . . . . .1005
5.3 DP SST-only Branch Device with 8b/10b Channel Coding . . . . . . . . . . . . . . . . . . .1006
5.3.1 DisplayID or Legacy EDID Access Handling Requirement. . . . . . . . . . . . .1006
5.3.2 Branch Device Link Configuration Requirements . . . . . . . . . . . . . . . . . . . .1006
5.3.3 Active Protocol Converter Adapters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1008
5.3.4 Link Rate and Lane Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1018
5.3.5 Forward Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1018
5.4 DP MST Source Device with 8b/10b Channel Coding . . . . . . . . . . . . . . . . . . . . . . .1019
5.4.1 Prompting the Downstream Device MST/SST Capabilities Transition . . . .1019
5.4.2 Atomic Message Transaction Generation. . . . . . . . . . . . . . . . . . . . . . . . . . .1019
5.4.3 Connection Status Notify Message Transaction Handling . . . . . . . . . . . . . .1019
5.4.4 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1019
5.4.5 DSC Bitstream Transport and FEC Policy . . . . . . . . . . . . . . . . . . . . . . . . . .1020
5.5 DP MST Sink Device with 8b/10b Channel Coding . . . . . . . . . . . . . . . . . . . . . . . . .1021
5.5.1 MST Sink Device with a DPRX in a Single UFP. . . . . . . . . . . . . . . . . . . . .1021
5.5.2 MST Sink Device with a DPRX in Multiple UFPs. . . . . . . . . . . . . . . . . . . .1023
5.6 DP MST Branch Device with 8b/10b Channel Coding. . . . . . . . . . . . . . . . . . . . . . .1024
5.6.1 MST Branch Device with a DPRX in a Single UFP. . . . . . . . . . . . . . . . . . .1024
5.6.2 MST Branch Device with a DPRX in Multiple UFPs . . . . . . . . . . . . . . . . .1028
5.7 DP Source Device with 128b/132b Channel Coding Enabled. . . . . . . . . . . . . . . . . .1029
5.7.1 Video Fallback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1029
5.7.2 Configuring LTTPR-capable PHY Repeaters. . . . . . . . . . . . . . . . . . . . . . . .1029
5.7.3 DSC Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1029
5.7.4 HDCP Encryption Status Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1029
5.7.5 Allocation Change Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1029
5.7.6 AUX Message Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1029
5.7.7 Panel Replay Optimization for DP Tunneling . . . . . . . . . . . . . . . . . . . . . . .1030
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5.8 DP Sink Device with 128b/132b Channel Coding Enabled. . . . . . . . . . . . . . . . . . . .1030
5.8.1 Video Fallback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1030
5.8.2 DSC Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1030
5.8.3 HDCP Encryption Status Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1030
5.8.4 Allocation Change Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1030
5.9 DP Branch Device with 128b/132b Channel Coding Enabled . . . . . . . . . . . . . . . . .1031
5.9.1 DFP Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1031
5.9.2 Virtual DP Peer Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1031
5.9.3 DSC Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1031
5.9.4 Encryption Status Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1031
5.9.5 Allocation Change Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1031
5.10 Branch-Sink Device in 8b/10b MST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1032
5.11 DP Source or Branch Device with an Embedded PHY Repeater on the DFP. . . . . .1032
5.12 DP Sink or Branch Device with an Embedded PHY Repeater on the UFP. . . . . . . .1033
5.13 Cable-Connector Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1034
5.13.1 Box-to-Box, User-Detachable Cable Assembly . . . . . . . . . . . . . . . . . . . . . .1034
5.13.2 Embedded and Captive Cable Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . .1034
5.13.3 Active Cable Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1034
5.14 DP Tunneling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1045
5.14.1 Panel Replay Optimization with DP Tunneling . . . . . . . . . . . . . . . . . . . . . .1046
Appendix A Audio Transport (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
A.1 Audio Stream Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1049
A.2 Association of Three SDP Types by way of Packet ID . . . . . . . . . . . . . . . . . . . . . . .1050
A.3 Scheduling of Audio_Stream SDP Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . .1050
A.3.1 Audio Format Change Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1052
A.4 Audio_Stream SDP Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1052
A.4.1 1- or 2-channel L-PCM Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1053
A.4.2 3- to 8-channel Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1053
A.4.3 1- to 2-channel One Bit Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1054
A.4.4 3- to 8-channel One Bit Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1054
A.4.5 1- to 16-Channel L-PCM 3D Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1055
A.4.6 17- to 32-Channel L-PCM 3D Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1055
A.4.7 DST Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1056
A.5 Channel-to-Speaker Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1057
A.6 Transfer of Sample Frequency Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1058
Appendix B Sink Event Notification Example (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . 1059
B.1 Mutual Identification by Source and Sink Devices . . . . . . . . . . . . . . . . . . . . . . . . . .1059
B.2 IRQ_HPD Pulse and Sink Device-specific IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . .1059
Appendix C Link Quality Management (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
C.1 Marginal Link Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1060
C.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1060
C.3 Tolerance to Bit Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1061
C.4 Link Retraining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1061
C.5 Long-term Link Quality Monitoring (Guidelines). . . . . . . . . . . . . . . . . . . . . . . . . . .1062
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Appendix D HBR2 Electrical Specifications (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
D.1 AUX Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1063
D.2 Main-Link Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1064
D.3 Dual-Dirac Jitter Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1069
Appendix E HBRx/RBR Scrambler C Code Reference (Informative) . . . . . . . . . . . . . . . . . . 1072
Appendix F Topology Management/Payload Bandwidth Management Usage
Examples (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
Appendix G Link Management during System Initialization (Informative). . . . . . . . . . . . . . 1079
G.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1079
G.2 Problem Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1079
G.2.1 Problem #1 – Sink Device Connected and Powered, but HPD Low . . . . . .1079
G.2.2 Problem #2 – Sink Device HPD Unplug Event Followed by Plug Event . .1080
Appendix H 3D Stereo Display Protocol Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
H.1 In-band 3D Stereo Signaling Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1085
H.1.1 MSA MISC1 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1085
H.1.2 VSC SDP Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1086
H.2 3D Stereo Display Capability Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1096
H.2.1 Legacy EDID 3D Stereo Display Capability Declaration. . . . . . . . . . . . . . .1097
H.2.2 DisplayID 3D Stereo Display Capability Declaration . . . . . . . . . . . . . . . . .1099
H.2.3 Pixel Sub-sampling/Non-Sub-sampling Capabilities Declaration . . . . . . . .1100
H.3 DP 3D Stereo Interoperability Policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1101
H.3.1 DP 3D Stereo Sink Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1101
H.3.2 DP 3D Stereo Video Source Device Support . . . . . . . . . . . . . . . . . . . . . . . .1104
Appendix I QUERY_STREAM_ENCRYPTION_STATUS Message Transaction
Handling in a CP Tree Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
I.1 Self-checking by MST Branch Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1105
I.2 Merit of QUERY_STREAM_ENCRYPTION_STATUS Message Transaction . . .1105
I.3 QUERY_STREAM_ENCRYPTION_STATUS Message
Transaction Handling in a CP Tree Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1106
I.3.1 IDs Provided by MST Source Device for
QUERY_STREAM_ENCRYPTION_STATUS Request
Message Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1106
I.3.2 Stream Status in QUERY_STREAM_ENCRYPTION_STATUS
Reply Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1108
I.3.3 Stream Status Signature in
QUERY_STREAM_ENCRYPTION_STATUS
Reply Message Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1110
I.3.4 Usage of Sink Type in Stream Status by an MST Source Device . . . . . . . .1110
I.3.5 Status Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1110
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Appendix J 16-Bit Frame CRC Example (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
Appendix K Adaptive-Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Appendix L Information and Examples for DSC Slice/Display Line
Calculations (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
L.1 Derivation of Slice Count Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1117
L.2 Usage Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1118
Appendix M 128b/132b Channel Coding without Using Place Holders . . . . . . . . . . . . . . . . 1122
M.1 Stream Data-to-Link Symbol Mapping with
128b/132b Link Layer without Place Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1123
M.2 Main-Link 128b/132b PHY Logical Sub-layer without Place Holders. . . . . . . . . . .1125
M.2.1 Conversion to PHY Logical Main-Link Lane Count . . . . . . . . . . . . . . . . . .1125
M.2.2 128b/132b PHY Logical Sub-layer Operating Sequence
without Place Holders (Alternative to Section 3.5.2.2) . . . . . . . . . . . . . . . .1125
M.2.3 Insertion of PHY Sync Symbols, CDI Bits, RS Padding Bits,
and RS Parity Symbols at PHY Logical Sub-layer. . . . . . . . . . . . . . . . . . . .1128
Appendix N UHBRx PRBS Initial Bit Sequences and Polynomials. . . . . . . . . . . . . . . . . . . . 1131
N.1 UHBRx PRBS7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1131
N.2 UHBRx PRBS9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1132
N.3 UHBRx PRBS11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1132
N.4 UHBRx PRBS15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1133
N.5 UHBRx PRBS23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1133
N.6 UHBRx PRBS31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1134
Appendix O Data EYE Mask Differences between HBR3/HBR2 and UHBRx Bit Rates. . . . 1135
O.1 HBR3/HBR2 EYE Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1135
O.2 UHBRx EYE Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1136
Appendix P Main Contributor History (Previous Versions). . . . . . . . . . . . . . . . . . . . . . . . . . 1137
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Tables
Table 1: Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 2: Main Contributors to DP v2.0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 3: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 1-1: Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 1-2: Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 1-3: Keywords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 1-4: Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 1-5: Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 1-6: DP Main-Link Application Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 1-7: Pixel Data Mapping over 4-lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 2-1: Device Types Covered by this Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 2-2: Topological Device Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 2-3: Default Framing Mode Control Link Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 2-4: Default Framing Mode (Deprecated) to
Enhanced Framing Mode Control Link Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . .97
Table 2-5: Pixel Steering into Main-Link Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 2-6: VB-ID Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 2-7: 10bpc RGB (30bpp) 1366x768 Packing to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . .104
Table 2-8: 6bpc RGB Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 2-9: 6bpc RGB Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 2-10: 6bpc RGB Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 2-11: 8bpc RGB to a 4-Lane Main-Link Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 2-12: 8bpc RGB Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 2-13: 8bpc RGB Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 2-14: 10bpc RGB Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Table 2-15: 10bpc RGB Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 2-16: 10bpc RGB Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 2-17: 12bpc RGB Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 2-18: 12bpc RGB Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 2-19: 12bpc RGB Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 2-20: 16bpc RGB Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 2-21: 16bpc RGB Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 2-22: 16bpc RGB Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 2-23: 8bpc YCbCr 4:2:2 Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 2-24: 8bpc YCbCr 4:2:2 Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 2-25: 8bpc YCbCr 4:2:2 Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 2-26: 10bpc YCbCr 4:2:2 Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 2-27: 10bpc YCbCr 4:2:2 Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 2-28: 10bpc YCbCr 4:2:2 Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 2-29: 12bpc YCbCr 4:2:2 Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
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Table 2-30: 12bpc YCbCr 4:2:2 Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 2-31: 12bpc YCbCr 4:2:2 Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 2-32: 16bpc YCbCr 4:2:2 Mapping to a 4-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 2-33: 16bpc YCbCr 4:2:2 Mapping to a 2-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 2-34: 16bpc YCbCr 4:2:2 Mapping to a 1-Lane Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 2-35: 8bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Four Main-Link Lanes. . . . .117
Table 2-36: 8bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Four Main-Link Lanes . . . . .117
Table 2-37: 8bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Two Main-Link Lanes . . . . .118
Table 2-38: 8bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Two Main-Link Lanes. . . . . .118
Table 2-39: 8bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over One Main-Link Lane . . . . . .118
Table 2-40: 8bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over One Main-Link Lane. . . . . . .118
Table 2-41: 10bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Four Main-Link Lanes. . . .119
Table 2-42: 10bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Four Main-Link Lanes . . . .119
Table 2-43: 10bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Two Main-Link Lanes . . . .120
Table 2-44: 10bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Two Main-Link Lanes. . . . .120
Table 2-45: 10bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over One Main-Link Lane . . . . .121
Table 2-46: 10bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over One Main-Link Lane. . . . . .121
Table 2-47: 12bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Four Main-Link Lanes. . . .122
Table 2-48: 12bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Four Main-Link Lanes . . . .122
Table 2-49: 12bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Two Main-Link Lanes . . . .123
Table 2-50: 12bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Two Main-Link Lanes. . . . .123
Table 2-51: 12bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over One Main-Link Lane . . . . .124
Table 2-52: 12bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over One Main-Link Lane. . . . . .124
Table 2-53: 16bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Four Main-Link Lanes. . . .125
Table 2-54: 16bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Four Main-Link Lanes . . . .125
Table 2-55: 16bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over Two Main-Link Lanes . . . .126
Table 2-56: 16bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over Two Main-Link Lanes. . . . .126
Table 2-57: 16bpc YCbCr 4:2:0 Even Lines (Starting with Line 0) over One Main-Link Lane . . . . .127
Table 2-58: 16bpc YCbCr 4:2:0 Odd Lines (Starting with Line 0) over One Main-Link Lane. . . . . .127
Table 2-59: 8bpp Y-only to a 4-Lane Main-Link Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 2-60: 8bpp Y-only Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 2-61: 8bpp Y-only Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 2-62: 10bpp Y-only Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 2-63: 10bpp Y-only Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 2-64: 10bpp Y-only Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 2-65: 12bpp Y-only Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Table 2-66: 12bpp Y-only Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Table 2-67: 12bpp Y-only Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Table 2-68: 16bpp Y-only Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 2-69: 16bpp Y-only Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 2-70: 16bpp Y-only Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 2-71: 6bpp RAW Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Table 2-72: 6bpp RAW Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Table 2-73: 6bpp RAW Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
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Table 2-74: 7bpp RAW Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 2-75: 7bpp RAW Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 2-76: 7bpp RAW Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 2-77: 8bpp RAW Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 2-78: 8bpp RAW Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 2-79: 8bpp RAW Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 2-80: 10bpp RAW Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Table 2-81: 10bpp RAW Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Table 2-82: 10bpp RAW Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Table 2-83: 12bpp RAW Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Table 2-84: 12bpp RAW Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Table 2-85: 12bpp RAW Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Table 2-86: 14bpp RAW Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Table 2-87: 14bpp RAW Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Table 2-88: 14bpp RAW Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Table 2-89: 16bpp RAW Mapping to a 4-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Table 2-90: 16bpp RAW Mapping to a 2-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Table 2-91: 16bpp RAW Mapping to a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Table 2-92: TU of 30bpp RGB Video over 2.7Gbps/lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . .141
Table 2-93: DPRX Stream Reconstruction Actions within the Sink Device . . . . . . . . . . . . . . . . . . . .145
Table 2-94: MSA Data Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Table 2-95: MSA Packet Timing Parameters that Can Be Ignored . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Table 2-96: MSA MISC1 and MISC0 Fields for Pixel Encoding/Colorimetry Format Indication . . .158
Table 2-97: SDP Header Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Table 2-98: SDP Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Table 2-99: Audio_TimeStamp SDP Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Table 2-100: Audio_TimeStamp SDP Maud and Naud Value Examples (Informative) . . . . . . . . . . . .163
Table 2-101: Audio High Bit Rate Mode (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Table 2-102: Non-HBR-encoded Audio 2-channel Layout (Informative). . . . . . . . . . . . . . . . . . . . . . .166
Table 2-103: Non-HBR-encoded Audio 8-channel Layout (Informative) . . . . . . . . . . . . . . . . . . . . . . .167
Table 2-104: L-PCM Audio and L-PCM 3D Audio Modes (Informative). . . . . . . . . . . . . . . . . . . . . . .168
Table 2-105: One Bit and DST Audio Modes (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Table 2-106: Audio_Stream SDP Header Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Table 2-107: Audio Samples Carried By Each L-PCM 3D Audio Audio_Stream SDP . . . . . . . . . . . .175
Table 2-108: Audio_Stream SDP Payload with IEC 60958-like Coding Bit Definitions . . . . . . . . . . .185
Table 2-109: Audio_Stream SDP Payload with One Bit Audio Coding Bit Definitions. . . . . . . . . . . .186
Table 2-110: Audio_Stream SDP Payload with DST Audio Coding Bit Definitions . . . . . . . . . . . . . .187
Table 2-111: Audio_Stream SDP Coding Type Payload Capacity Summary (Informative). . . . . . . . .190
Table 2-112: 32-channel L-PCM 3D Audio Mandates on DMT ID = 57h Mode (Informative) . . . . . .191
Table 2-113: Extension SDP Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Table 2-114: Audio_CopyManagement SDP Header Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
Table 2-115: ISRC SDP Header Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Table 2-116: VSC SDP Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Table 2-117: VSC SDP Payload for DB16 through DB18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Table 2-118: Camera SDP Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
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Table 2-119: PPS SDP Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Table 2-120: VSC_EXT_VESA and VSC_EXT_CTA SDP Header Bytes. . . . . . . . . . . . . . . . . . . . . .213
Table 2-121: VSC_EXT_VESA and VSC_EXT_CTA SDP Payload Bytes – DB0 through DB31 . . .213
Table 2-122: Extended INFOFRAME Payload Mapping of the
First VSC_EXT_CTA SDP Payload Bytes – DB0 through DB31. . . . . . . . . . . . . . . . . .215
Table 2-123: Extended INFOFRAME Payload Mapping of the
Second VSC_EXT_CTA SDP Payload Bytes – DB0 through DB31. . . . . . . . . . . . . . . .215
Table 2-124: Adaptive-Sync SDP Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Table 2-125: INFOFRAME SDP v1.2 Header Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes – DB0 through DB31 . . . . . . . . . . . . . . . .221
Table 2-127: INFOFRAME SDP v1.3 Header Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Table 2-128: INFOFRAME SDP v1.3 Payload Data Bytes – DB0 through DB31 . . . . . . . . . . . . . . . .222
Table 2-129: DP Source Device DP_PWR State Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
Table 2-130: DP Sink Device DP_PWR State Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Table 2-131: DPTX AUX_CH State and Event Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Table 2-132: DPRX AUX_CH State and Event Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
Table 2-133: Current_Capabilities_Structure Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
Table 2-134: Current_Capabilities_Structure Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
Table 2-135: Bit Field Definition for S3D Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
Table 2-136: Bit Field Definition for Color Depth Indication for RGB, Luma, and Chroma . . . . . . . .264
Table 2-137: DPCD Registers Used with Virtual DP Peer Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Table 2-138: Summary of VC Payload Control Link Symbol Sequence. . . . . . . . . . . . . . . . . . . . . . . .277
Table 2-139: VC Payload Bandwidth for One Time Slot per MTP Allocation
for Various Link Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
Table 2-140: 8b/10b Channel Coding VC Payload ID Table
of DPRX Mapped to DPCD Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
Table 2-141: 8b/10b Channel Coding DPCD Address Map for
VC Payload Table Update and ACT Status Verification . . . . . . . . . . . . . . . . . . . . . . . . .296
Table 2-142: Various Events and Impacts on VC Payload ID Table . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Table 2-143: MTPH Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
Table 2-144: MTP Payload Control Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
Table 2-145: Scrambled Index to K-Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
Table 2-146: 128b/132b vs. 8b/10b Channel Coding Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
Table 2-147: 8b/10b Link Layer-to-128b/132b Link Layer Control Link Symbol Mapping. . . . . . . . .323
Table 2-148: LLCP Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
Table 2-149: 128b/132b Channel Coding VC Payload ID Table of DPRX Mapped
to DPCD Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
Table 2-150: 128b/132b Link Layer Per-time-slot PBN Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
Table 2-151: Mapping of 128-bit Cipher Key Stream to 128b/132b Link Layer Lanes . . . . . . . . . . . .334
Table 2-152: XOR’ing/Non-XOR’ing of LLCP with Key Stream. . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
Table 2-153: DP DSC Sink Device Compressed Transport Bit Rate Range . . . . . . . . . . . . . . . . . . . . .341
Table 2-154: DP DSC Source Device Compressed Transport Bit Rate Range . . . . . . . . . . . . . . . . . . .342
Table 2-155: Number of Slices Needed per Display Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
Table 2-156: Color Channel Mapping for RGB Color Conversion Bypass Mode. . . . . . . . . . . . . . . . .351
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Table 2-157: DSC PPS Syntax Element Flags and Settings
Needed for Enabling RGB Color Conversion Bypass Mode . . . . . . . . . . . . . . . . . . . . . .351
Table 2-158: DSC .cfg File Settings for RGB Color Conversion Bypass Mode . . . . . . . . . . . . . . . . . .352
Table 2-159: 3D Stereo Video DP DSC Transport. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
Table 2-160: DSC Support Mandate for 128b/132b Link Layer-capable DP Device Exemptions . . . .362
Table 2-161: DSC Support Mandates for a DP Source Device with
a 128b/132b Link Layer-capable DFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
Table 2-162: DSC Support Mandates for a DP Sink Device with
a 128b/132b Link Layer-capable UFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
Table 2-163: DSC Support Mandates for a DP Branch Device with
a 128b/132b Link Layer-capable UFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
Table 2-164: DP Branch Device DFP Minimum
Uncompressed Display Stream Output Mandate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
Table 2-165: DP Branch Device DSC Decoding Resources Needed to Meet DFP Minimum
Uncompressed Display Stream Output Mandate with 2-lane UHBR10 UFP. . . . . . . . . .366
Table 2-166: Sequence of DSC Bitstream Bit Depth Change that Involves
a Time Slot Allocation Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
Table 2-167: DSC Extended Capability Branch Total DSC Resources
DPCD Registers for Figure 2-129 Configuration Example . . . . . . . . . . . . . . . . . . . . . . .373
Table 2-168: Virtual DSC Extended Capability DPCD Register Settings
for Figure 2-131 Configuration Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
Table 2-169: Virtual DSC Extended Capability DPCD Register Settings
for Figure 2-132 Configuration Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
Table 2-170: Bit/Byte Size of Various Data Types of AUX Transaction Syntax . . . . . . . . . . . . . . . . .378
Table 2-171: Request Command Definition, Bit 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
Table 2-172: Reply Command Definition, Bits 3:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
Table 2-173: Request Command Definition, Bits 2:0, When Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . .385
Table 2-174: I 2 C Write Transaction Method 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
Table 2-175: I 2 C Write Transaction Method 1 with a Slow I 2 C Bus in the Sink Device . . . . . . . . . . .390
Table 2-176: I 2 C Write Transaction Method 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
Table 2-177: I 2 C Read Transaction Method 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
Table 2-178: I 2 C Read Transaction Method 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
Table 2-179: I 2 C Write followed by an I 2 C Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
Table 2-180: Burst Write Sizes/Bus Speed Retry Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
Table 2-181: Burst Read Sizes/Bus Speed Retry Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
Table 2-182: DPCD Field Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
Table 2-183: Address Mapping within DPCD Receiver Capability Field
(DPCD Addresses 00000h through 000FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
Table 2-184: Address Mapping within DPCD Link Configuration Field
(DPCD Addresses 00100h through 001FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
Table 2-185: Address Mapping within DPCD Link/Sink Device Status Field
(DPCD Addresses 00200h through 002FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .488
Table 2-186: Address Mapping within DPCD Source Device-specific Field
(DPCD Addresses 00200h through 003FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513
Table 2-187: Address Mapping within DPCD Sink Device-specific Field
(DPCD Addresses 00400h through 004FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515
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Table 2-188: Address Mapping within DPCD Branch Device-specific Field
(DPCD Addresses 00500h through 005FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .516
Table 2-189: Address Mapping within DPCD Link/Sink Device Power Control Field
(DPCD Addresses 00600h through 006FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .517
Table 2-190: Address Mapping within DPCD eDP-specific Field
(DPCD Addresses 00700h through 007FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518
Table 2-191: Address Mapping within DPCD Sideband MSG Buffers Field
(DPCD Addresses 01000h through 017FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518
Table 2-192: Address Mapping within DPCD DPRX Event Status Indicator Field
(DPCD Addresses 02000h through 021FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519
Table 2-193: Address Mapping within DPCD Extended Receiver Capability Field
(DPCD Addresses 02000h through 022FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529
Table 2-194: Address Mapping within DPCD Protocol Converter Extension Field
(DPCD Addresses 03000h through 030FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .559
Table 2-195: Address Mapping within DPCD Multi-touch (for eDP) Field
(DPCD Addresses 60000h through 61CFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
Table 2-196: Address Mapping within DPCD HDCP 1.3 and HDCP 2.2 Field
(DPCD Addresses 68000h through 69FFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
Table 2-197: Address Mapping within DPCD Tunneling Device-specific Field
(DPCD Addresses E0000h through E00FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573
Table 2-198: Address Mapping within DPCD LTTPR Field
(DPCD Addresses F0000h through F02FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
Table 2-199: Address Mapping within DPCD MyDP Standard-specific Field
(DPCD Addresses FFF00h through FFFFFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593
Table 2-200: 8b/10b Encoding and Scrambling Rules for Link Management. . . . . . . . . . . . . . . . . . . .599
Table 2-201: 128b/132b Encoding and Scrambling Rules for Link Management. . . . . . . . . . . . . . . . .602
Table 2-202: Symbol Error Rate Measurement Pattern following Scrambler Reset . . . . . . . . . . . . . . .607
Table 2-203: Transaction Message Version Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
Table 2-204: Message_Transaction_Sequence Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612
Table 2-205: Message_Transaction_Request Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612
Table 2-206: Request Names and their Corresponding Request_Identifier . . . . . . . . . . . . . . . . . . . . . .613
Table 2-207: Request_Data Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614
Table 2-208: Message_Transaction_Reply Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617
Table 2-209: Reply_Data Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617
Table 2-210: Reasons for NAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .618
Table 2-211: ACK_Data Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .620
Table 2-212: Sideband_MSG Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .622
Table 2-213: Sideband_MSG_Header Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623
Table 2-214: Sideband_MSG_Body Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626
Table 2-215: ALLOCATE_PAYLOAD Message Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .641
Table 2-216: CLEAR_PAYLOAD_ID_TABLE Message Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . .643
Table 2-217: CONNECTION_STATUS_NOTIFY Message Syntax . . . . . . . . . . . . . . . . . . . . . . . . . .644
Table 2-218: Peer_Device_Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .645
Table 2-219: Peer_Device_Type Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .646
Table 2-220: ENUM_PATH_RESOURCES Message Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647
Table 2-221: LINK_ADDRESS Message Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .649
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Table 2-222: POWER_DOWN_PHY Message Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .651
Table 2-223: POWER_UP_PHY Message Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .652
Table 2-224: QUERY_PAYLOAD Message Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .653
Table 2-225: REMOTE_DPCD_READ Message Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .654
Table 2-226: REMOTE_DPCD_WRITE Message Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .655
Table 2-227: REMOTE_I2C_READ Message Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .657
Table 2-228: REMOTE_I2C_WRITE Message Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .659
Table 2-229: RESOURCE_STATUS_NOTIFY Message Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . .660
Table 2-230: SINK_EVENT_NOTIFY Message Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .661
Table 2-231: DPCD Registers Used for GTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673
Table 2-232: Panel Self Refresh 2 Mode Main-Link Activity Options . . . . . . . . . . . . . . . . . . . . . . . . .687
Table 2-233: VSC SDP Header Extension Bytes for Panel Replay Mode. . . . . . . . . . . . . . . . . . . . . . .691
Table 2-234: VSC SDP Payload Extension Bytes for Panel Replay Mode . . . . . . . . . . . . . . . . . . . . . .692
Table 2-235: DPCD Registers Used for Panel Replay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .701
Table 3-1: Main-Link PHY Layer Compliance Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .706
Table 3-2: Allowed Voltage Swing and TX Emphasis Level Combinations. . . . . . . . . . . . . . . . . . .708
Table 3-3: DP_PWR Specification for Box-to-Box DisplayPort Connection . . . . . . . . . . . . . . . . . .714
Table 3-4: Hot Plug Detect Signal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .717
Table 3-5: AUX_CH Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723
Table 3-6: DP AUX IC Design Guidance (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .727
Table 3-7: AUX_CH EYE Mask Minimum Voltage Values at TX Device Connector Pins . . . . . . .729
Table 3-8: AUX_CH EYE Mask Minimum Voltage Values at RX Device Connector Pins. . . . . . .730
Table 3-9: 8b/10b Special Character-to-Control Link Symbol Mapping. . . . . . . . . . . . . . . . . . . . . .731
Table 3-10: DPCD Registers Used for 8b/10b Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .732
Table 3-11: Link Training Symbol Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .734
Table 3-12: RS(254, 250) FEC Test Vectors (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .761
Table 3-13: Interleaved FEC Block for 4-, 2-, and 1-lane Configurations. . . . . . . . . . . . . . . . . . . . . .762
Table 3-14: Parity Symbols Interleaving and Splitting in 2- and 4-lane Configurations . . . . . . . . . . .766
Table 3-15: Parity Symbols Interleaving and Splitting in 1-lane Configuration . . . . . . . . . . . . . . . . .766
Table 3-16: CD_ADJ Code Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .767
Table 3-17: CD_ADJ Selection Case Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .767
Table 3-18: FEC_DECODE_EN and FEC_DECODE_DIS Control Link Symbol Sequences . . . . . .771
Table 3-19: DPCD Registers Used for 128b/132b PHY Logical Sub-layer
Capability Discovery and Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .773
Table 3-20: 128b/132b PHY Logical Sub-layer 32-bit Symbol Types . . . . . . . . . . . . . . . . . . . . . . . .777
Table 3-21: Control Link Symbol Bit Mapping – 128b/132b PHY Logical Sub-layer . . . . . . . . . . . .778
Table 3-22: PHY Sync Symbol Bit [31:24] XYh Value
to 2 nd , 3 rd , and 4 th Symbol Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .779
Table 3-23: CDI Field Intra-super-symbol Shifting When CDI Field Value is 1 or 1100b. . . . . . . . .783
Table 3-24: RS(198, 194) FEC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .786
Table 3-25: 12-bit CDI Group Field lsb and msb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .787
Table 3-26: 128b/132b PHY Logical Sub-layer Link TPSs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .791
Table 3-27: PHY Logical Frame Composition when RS FEC Is Enabled after LT Completion. . . . .793
Table 3-28: 128b/132b PHY Logical Sub-layer Inter-lane Skew Specification. . . . . . . . . . . . . . . . . .796
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Table 3-29: 128b/132b PHY Logical Sub-layer Inter-lane Skew Sources. . . . . . . . . . . . . . . . . . . . . .796
Table 3-30: DPCD Registers Used for 128b/132b Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . .797
Table 3-31: Bit Sequence for 4-/2-lane Configurations that Includes RS(198, 194)
FEC Parity Bytes before Pre-coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800
Table 3-32: Bit Sequence for 1-lane Configurations that Includes RS(198, 194)
FEC Parity Bytes before Pre-coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .806
Table 3-33: Total Data Bandwidth Efficiency (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .811
Table 3-34: DPCD Registers Used for FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .812
Table 3-35: DPCD Registers Used for FEC for LT-tunable Bit-level PHY Repeaters . . . . . . . . . . . .813
Table 3-36: FEC Error Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .815
Table 3-37: DPCD Registers Used for PHY Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .821
Table 3-38: DP Main-Link Transmitter System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .823
Table 3-39: HBR3/HBR2 DP Main-Link Transmitter TP2 Parameters. . . . . . . . . . . . . . . . . . . . . . . .824
Table 3-40: HBR/RBR DP Main-Link Transmitter TP2 Parameters. . . . . . . . . . . . . . . . . . . . . . . . . .826
Table 3-41: HBR3 DP Main-Link Transmitter TP2_CTLE and TP3_CTLE Parameters . . . . . . . . . .827
Table 3-42: HBR2 DP Main-Link Transmitter TP2 and TP3_EQ Parameters. . . . . . . . . . . . . . . . . . .828
Table 3-43: DP Main-Link Receiver System Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .829
Table 3-44: DP Main-Link Receiver TP3 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .830
Table 3-45: HBR3 DP Main-Link Receiver TP3_CTLE Parameters. . . . . . . . . . . . . . . . . . . . . . . . . .831
Table 3-46: HBR2 DP Main-Link Receiver TP3_EQ Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .832
Table 3-47: Receiver PLL Clock Recovery Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .833
Table 3-48: HBR Upstream Device DFP Time and Voltage Values at TP2 EYE Mask Vertices. . . .843
Table 3-49: RBR Upstream Device DFP Time and Voltage Values at TP2 EYE Mask Vertices . . . .843
Table 3-50: HBR Downstream Device UFP Time and Voltage Values
at TP3_EQ EYE Mask Vertices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .844
Table 3-51: RBR Downstream Device UFP Time and Voltage Values
at TP3 EYE Mask Vertices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .844
Table 3-52: Common DP Main-Link UHBR Electrical System Parameters . . . . . . . . . . . . . . . . . . . .853
Table 3-53: Preset FFE Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .855
Table 3-54: UHBR10 Cable Interoperability Matrix (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . .859
Table 3-55: UHBR10 DPTX TP3_EQ Metrics System Parameters (Normative) . . . . . . . . . . . . . . . .862
Table 3-56: UHBR10 DPTX TP2 Metrics System Parameters (Normative) . . . . . . . . . . . . . . . . . . . .863
Table 3-57: UHBR10 DPTX TPRX_EQ Metrics System Parameters (Informative). . . . . . . . . . . . . .864
Table 3-58: UHBR10 DPRX TP3_EQ Metrics System Parameters at 1E -6 BER (Informative). . . . .865
Table 3-59: UHBR13.5 DPTX TP2' Metrics System Parameters (Normative) . . . . . . . . . . . . . . . . . .866
Table 3-60: UHBR13.5 Cable Interoperability Matrix (Informative) . . . . . . . . . . . . . . . . . . . . . . . . .866
Table 3-61: UHBR13.5 TP3_EQ Metrics System Parameters (Informative). . . . . . . . . . . . . . . . . . . .869
Table 3-62: UHBR20 DPTX TP2' Metrics System Parameters (Normative) . . . . . . . . . . . . . . . . . . .870
Table 3-63: UHBR20 Cable Interoperability Matrix (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . .870
Table 3-64: UHB20 TP3_EQ Metrics System Parameters (Informative) . . . . . . . . . . . . . . . . . . . . . .873
Table 3-65: DPCD Addresses Snooped by LTTPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .880
Table 3-66: LTTPR DPCD Capability and ID Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .881
Table 3-67: LTTPR DPCD Link Configuration and Status Field(s) . . . . . . . . . . . . . . . . . . . . . . . . . .882
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Table 4-1: Supported Cable Assembly Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .912
Table 4-2: Supported Resizing Adapter Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913
Table 4-3: Supported Extension Cable Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .914
Table 4-4: Impedance Profile Values for Cable Assembly with DP Connector. . . . . . . . . . . . . . . . .918
Table 4-5: Impedance Profile Values for Cable Assembly with mDP Connector . . . . . . . . . . . . . . .919
Table 4-6: Mixed Mode Differential/Common Relations of S-parameters . . . . . . . . . . . . . . . . . . . .920
Table 4-7: Intra-pair Skew Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .929
Table 4-8: Inter-pair Skew Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .930
Table 4-9: Nyquist Frequencies and their ILFitAtNq Requirements . . . . . . . . . . . . . . . . . . . . . . . . .935
Table 4-10: DFP Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .940
Table 4-11: UFP Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .941
Table 4-12: Mating Sequence Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .943
Table 4-13: DP External Connector Mechanical Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .944
Table 4-14: DP External Connector Electrical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .945
Table 4-15: DP External Connector Environment Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .946
Table 4-16: DFP mDP Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .953
Table 4-17: UFP mDP Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .954
Table 4-18: mDP Connector Mechanical Performance Requirements. . . . . . . . . . . . . . . . . . . . . . . . .961
Table 4-19: mDP Connector Electrical Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .962
Table 4-20: mDP Connector Environment Performance Requirements. . . . . . . . . . . . . . . . . . . . . . . .963
Table 4-21: mDP Mating Sequence Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .969
Table 4-22: DP Panel-side Internal Connector Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .975
Table 4-23: Panel-side Connector Mechanical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .980
Table 4-24: Panel-side Connector Electrical Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .981
Table 4-25: Panel-side Connector Environmental Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . .982
Table 5-1: Pixel Encoding/Colorimetry Format Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .984
Table 5-2: Recommended DP Source Device Behavior when Connected to a Branch Device . . . . .994
Table 5-3: Lane Counts Needed for Typical TV Display Timings at RBR . . . . . . . . . . . . . . . . . . . .997
Table 5-4: Lane Counts Needed for Typical Data Projector Timings at RBR. . . . . . . . . . . . . . . . . .997
Table 5-5: Sink Device Power State Machine Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1002
Table 5-6: Extended Wake Timeout from SLEEP Power State Request/Grant Registers . . . . . . . .1004
Table 5-7: DVI, HDMI, and DP Protocol Converter Adapter Requirements . . . . . . . . . . . . . . .1010
Table 5-8: HDMI Protocol Converter EDID Processing and Scrambling Control. . . . . . . . . . . . . .1013
Table 5-9: CEC-Tunneling-over-AUX Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1014
Table 5-10: DPCD Registers Used for CEC-Tunneling-over-AUX. . . . . . . . . . . . . . . . . . . . . . . . . .1016
Table 5-11: DP Active Cable Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1035
Table 5-12: DFP TX of an Active Cable TX EYE Opening and
TX Drive Setting Monotonicity Test Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . .1036
Table 5-13: Active Cable Unidirectional AUX Latency Requirements. . . . . . . . . . . . . . . . . . . . . . .1038
Table 5-14: DPCD Register Used with Panel Replay Optimization with DP Tunneling. . . . . . . . . .1048
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Table A-1: Channel-to-Speaker Mapping of 3-channel L-PCM Audio
with Audio INFOFRAME SDP CA = 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1057
Table D-1: AUX_CH EYE Mask Minimum Voltage
at Transmitting IC Package Pins (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1063
Table D-2: AUX_CH EYE Mask Minimum Voltage
at Receiving IC Package Pins (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1064
Table D-3: DP Main-Link TX Silicon Parameters (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . .1065
Table D-4: DP Main-Link TX TP1 Package Pin Parameters (Informative) . . . . . . . . . . . . . . . . . . .1066
Table D-5: DP Main-Link RX TP4 Package Pin Parameters (Informative) . . . . . . . . . . . . . . . . . . .1067
Table D-6: DP Main-Link RX Silicon Pads with HBR2 (Informative) . . . . . . . . . . . . . . . . . . . . . .1068
Table D-7: DP Main-Link RX Silicon Pads with HBR/RBR (Informative). . . . . . . . . . . . . . . . . . .1068
Table H-1: MSA MISC1 Field, bits 2:1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1085
Table H-2: VSC SDP Header Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1086
Table H-3: VSC SDP DB0 Payload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1087
Table H-4: CRC Calculation Method for 3D Stereo Video Summary . . . . . . . . . . . . . . . . . . . . . . .1095
Table H-5: Legacy EDID r1.4 3D Stereo Display Capability Declaration . . . . . . . . . . . . . . . . . . . .1097
Table H-6: DisplayID Standard, 3D Stereo Display Capability Declaration . . . . . . . . . . . . . . . . . .1099
Table H-7: 3D Stereo Display Format Method Codes Supported in DisplayID Standard . . . . . . . .1100
Table H-8: Allowed Timing Range for 3D Stereo Sink,
for Frame/Field Sequential Stereo Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1102
Table H-9: Allowed Timing Range for 3D Stereo Sink, for Stacked Frame
3D Stereo Video Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1103
Table I-1: IDs Provided by MST Source Device for
QUERY_STREAM_ENCRYPTION_STATUS Request Message Transaction . . . . . .1107
Table I-2: Stream Status Information Replied by the MST Branch Device . . . . . . . . . . . . . . . . . .1108
Table I-3: MST Branch Device Status Query Calculated Values . . . . . . . . . . . . . . . . . . . . . . . . . .1110
Table L-1: Sample Display Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1118
Table L-2: Determining Number of Slices/Display Line
that Are Supported by Table L-1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1119
Table P-1: Main Contributor History (Previous Versions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1137
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Figures
Figure 1-1: DP Data Transport Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 1-2: Layered DP Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 2-1: Link Layer Services Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 2-2: Single DP Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 2-3: DP Source-to-Sink Device by way of a DP Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 2-4: DP Source-to-Legacy Sink Device by way of a DP-to-Legacy Protocol Converter. . . . . .88
Figure 2-5: Legacy Source-to-DP Sink Device by way of a Legacy-to-DP Protocol Converter. . . . . .88
Figure 2-6: Multiple DP Source Devices to DP Sink Device by way of an Input Switch. . . . . . . . . . .89
Figure 2-7: DP Source Device to Multiple DP Sink Devices
by way of a DP Replicator/Output Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 2-8: DPTX Main-Link Data Path High-Level Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 2-9: DPRX Main-Link Data Path High-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .94
Figure 2-10: Main Video Stream Data Packing Example for a 4-Lane Main-Link. . . . . . . . . . . . . . . . .99
Figure 2-11: Link Symbols over the Main-Link without Main Video Stream . . . . . . . . . . . . . . . . . . .102
Figure 2-12: VB-ID, Mvid[7:0], and Maud[7:0] Packing over the Main-Link . . . . . . . . . . . . . . . . . . .103
Figure 2-13: TU during Active Video Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Figure 2-14: Secondary-data Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Figure 2-15: Inter-lane Skewing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Figure 2-16: Reference Pulse and Feedback Pulse of Stream Clock Regeneration Circuit. . . . . . . . . .146
Figure 2-17: Mvid and Nvid Value Determination Example in
Asynchronous Clock Mode in a Source Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Figure 2-18: DP MSA Packet Transport Mapping over Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Figure 2-19: Horizontal Blanking Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Figure 2-20: Interlaced Video Format/Timing for Odd Number of Lines/frame. . . . . . . . . . . . . . . . . .156
Figure 2-21: Interlaced Video Format/Timing for Even Number of Lines/frame. . . . . . . . . . . . . . . . .156
Figure 2-22: Audio_TimeStamp SDP Mapping over Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Figure 2-23: Audio_Stream SDP over Main-Link for 2-Channel Layout Audio . . . . . . . . . . . . . . . . .173
Figure 2-24: Audio_Stream SDP over Main-Link for 8-Channel Layout Audio . . . . . . . . . . . . . . . . .174
Figure 2-25: Audio_Stream SDP over Main-Link for 16-Channel Layout Audio
(L-PCM 3D Audio Extension Type Code 13). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Figure 2-26: Audio_Stream SDP over Main-Link for 32-Channel Layout Audio
(L-PCM 3D Audio Extension Type Code 13). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Figure 2-27: Audio_Stream SDP over Main-Link for DST Audio Layout . . . . . . . . . . . . . . . . . . . . . .180
Figure 2-28: L-PCM 3D Audio Data Allocation with Audio INFOFRAME Byte 4 = FEh,
8.1 SPM Asserted (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Figure 2-29: L-PCM 3D Audio Data Allocation with Audio INFOFRAME Byte 4 = FFh,
8.1 SPM Asserted, RCD Order Used (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Figure 2-30: L-PCM 3D Audio Data Allocation with Audio INFOFRAME Byte 4 = FEh,
All SPM Asserted (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Figure 2-31: L-PCM 3D Audio Data Allocation with Audio INFOFRAME Byte 4 = FFh,
All SPM Asserted, RCD Order Used (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Figure 2-32: Data Mapping within the 4-byte Payload of an
Audio_Stream SDP with IEC 60958-like Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
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Figure 2-33: Data Mapping within the 4-byte Payload of an
Audio_Stream SDP with One Bit Audio Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
Figure 2-34: Data Mapping within the 4-Byte Payload Sub-layout of a DST Audio_Stream SDP
with DST Audio Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
Figure 2-35: Extension SDP Mapping over Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Figure 2-36: Audio_CopyManagement SDP Mapping over Main-Link . . . . . . . . . . . . . . . . . . . . . . . .196
Figure 2-37: ISRC SDP Mapping over the Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Figure 2-38: VSC SDP Mapping over the Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Figure 2-39: Camera SDP Mapping over Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Figure 2-40: Camera RAW Active Pixels (Main Video Stream) and Camera SDP Transport . . . . . . .207
Figure 2-41: PPS Timing – No Change from Prior PPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Figure 2-42: PPS SDP Payload Mapping over Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Figure 2-43: VSC_EXT_VESA SDP Framework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Figure 2-44: Adaptive-Sync SDP Transmission Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
Figure 2-45: INFOFRAME SDP v1.2 and v1.3 Mapping over Main-Link. . . . . . . . . . . . . . . . . . . . . .219
Figure 2-46: SDP Splitting in SST Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Figure 2-47: RS(15, 13) Encoder Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Figure 2-48: ECC Block Nibble-Interleaving for 4- and 2-Lane Main-Links (Payload). . . . . . . . . . . .227
Figure 2-49: ECC Block Nibble-Interleaving for 1-Lane Main-Link (Payload) . . . . . . . . . . . . . . . . . .227
Figure 2-50: ECC Block Nibble-Interleaving for 4- and 2-Lane Main-Links (Header) . . . . . . . . . . . .228
Figure 2-51: ECC Block Nibble-Interleaving for 1-Lane Main-Link (Header). . . . . . . . . . . . . . . . . . .228
Figure 2-52: 15-nibble Code-word for Packet Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Figure 2-53: 15-nibble Code-word for Packet Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Figure 2-54: DPTX AUX_CH State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
Figure 2-55: DPRX AUX_CH State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
Figure 2-56: DP Data Transport Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Figure 2-57: DP MST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
Figure 2-58: Illustration of Virtual Channel, Link, and Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Figure 2-59: Single-Stream Source Device to Dual-Stream Sink Devices (Dual-Display Clone) . . . .241
Figure 2-60: Dual-Stream Source Devices to Dual-Stream Sink Devices (Extended Desktop) . . . . . .241
Figure 2-61: Single-stream-only Isochronous Transport Service Layers . . . . . . . . . . . . . . . . . . . . . . .242
Figure 2-62: Multi-stream Isochronous Transport Service Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Figure 2-63: Sideband CH Communication Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
Figure 2-64: Branching Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Figure 2-65: Multi-stream Multi-sink Device with Multiple Main Stream Sinks and SDP Sinks . . . .249
Figure 2-66: Multi-stream Sink Device with Single Main Stream Sink and Multiple SDP Sinks . . . .250
Figure 2-67: Multi-stream Audio-only Sink Device with SDP Sinks . . . . . . . . . . . . . . . . . . . . . . . . . .250
Figure 2-68: Multi-stream Topology Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Figure 2-69: Example Topology with RAD of Devices Relative to Source Devices . . . . . . . . . . . . . .253
Figure 2-70: Multi-stream Topology with a Loop and a Parallel Path . . . . . . . . . . . . . . . . . . . . . . . . .257
Figure 2-71: Layers Discussed in this Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Figure 2-72: DP MST Source Device Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
Figure 2-73: DP MST Sink Device Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Figure 2-74: DP MST Branch Device Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Figure 2-75: DP SST Source Device Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
Figure 2-76: DP SST Sink Device Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
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Figure 2-77: Multi-function Branch-Sink Device Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
Figure 2-78: Multi-function MST Branch-Sink Device Enumeration Example . . . . . . . . . . . . . . . . . .267
Figure 2-79: Enumeration after DP SST Monitor 1 Is Plugged. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
Figure 2-80: DSC Decompression Operation Control
by way of Virtual/Physical DPCD Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Figure 2-81: Link Timing Generation in MST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
Figure 2-82: Time Slot Allocation to VC Payload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
Figure 2-83: VC Payload Symbol Generator of a DP Source Device . . . . . . . . . . . . . . . . . . . . . . . . . .275
Figure 2-84: 4-Symbol Sequence Unit Mapping to Main-Link Lanes . . . . . . . . . . . . . . . . . . . . . . . . .276
Figure 2-85: Repetition of 4-Symbol Sequence Unit Example for 1-Lane Main-Link . . . . . . . . . . . . .276
Figure 2-86: AV Stream Mapping in MST Mode After VC Payloads for a Given Main Video
Stream are Concatenated and VC Payload Fill Symbol Sequences Removed . . . . . . . . .280
Figure 2-87: DP Source Device VC Payload Mapping Logic Block Diagram . . . . . . . . . . . . . . . . . . .281
Figure 2-88: DP Sink Device VC Payload Mapping Logic Block Diagram . . . . . . . . . . . . . . . . . . . . .281
Figure 2-89: Pass-through DP Branch Device VC Payload Mapping Logic Block Diagram . . . . . . . .281
Figure 2-90: SDP Splitting in MST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Figure 2-91: Bandwidth Management by Payload Bandwidth Manager. . . . . . . . . . . . . . . . . . . . . . . .286
Figure 2-92: ACT Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Figure 2-93: VC Payload Allocation Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
Figure 2-94: Time Sequence for Adding a New Payload Example. . . . . . . . . . . . . . . . . . . . . . . . . . . .300
Figure 2-95: Timing Sequence for Adding a New Payload with Error . . . . . . . . . . . . . . . . . . . . . . . . .301
Figure 2-96: Timing Sequence for Deleting a Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
Figure 2-97: Timing Sequence for Deleting a Payload with an Error . . . . . . . . . . . . . . . . . . . . . . . . . .303
Figure 2-98: Timing Sequence for Deleting a Payload with Locally Unrecoverable Error. . . . . . . . . .304
Figure 2-99: Timing Sequence for Reducing the VC Payload Allocation. . . . . . . . . . . . . . . . . . . . . . .305
Figure 2-100: Timing Sequence for Increasing the VC Payload Allocation . . . . . . . . . . . . . . . . . . . . . .306
Figure 2-101: MSTM ECF and LVP Signaling at Link Frame Boundary. . . . . . . . . . . . . . . . . . . . . . . .316
Figure 2-102: ECF Immediately prior to ACT Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
Figure 2-103: 128b/132b Link Layer-capable
DP Source and Sink Device Connection, Highlighting Link Layer Blocks . . . . . . . . . . .317
Figure 2-104: DP Source Device 128b/132b Link Layer Logical View (Informative). . . . . . . . . . . . . .320
Figure 2-105: DP Sink Device Logical View for 128b/132b Link Layer (Informative). . . . . . . . . . . . .321
Figure 2-106: DP Branch Device Logical View for 128b/132b Link Layer (Informative). . . . . . . . . . .321
Figure 2-107: Pixel Data to 32-bit Link Symbol Mapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . .322
Figure 2-108: 128b/132b Link Layer MTPs and Link Layer Frames . . . . . . . . . . . . . . . . . . . . . . . . . . .324
Figure 2-109: MSA Packet Mapping to 32-bit Link Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
Figure 2-110: VB-ID Mapping to 32-bit Link Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
Figure 2-111: SDP Mapping to 32-bit Link Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
Figure 2-112: Audio_TimeStamp SDP Mapping to 32-bit Link Symbols . . . . . . . . . . . . . . . . . . . . . . .329
Figure 2-113: 128b/132b DP Link HDCP Encryption Status Signaling . . . . . . . . . . . . . . . . . . . . . . . . .335
Figure 2-114: DPTX 128b/132b Link Layer Place Holder Symbol Insertion (Informative). . . . . . . . . .336
Figure 2-115: DP Layer Architecture Model with Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
Figure 2-116: High-Level Compression Architectural Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
Figure 2-117: Single DSC Bitstream DP SST Display Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
Figure 2-118: Multiple DSC Bitstream DP MST Display Example . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
Figure 2-119: Initial DSC Discovery, Setup, and Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
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Figure 2-120: Compressed/Uncompressed Stream Indication in VB-ID. . . . . . . . . . . . . . . . . . . . . . . . .346
Figure 2-121: Packing DSC Data Bytes within a Video Frame Example . . . . . . . . . . . . . . . . . . . . . . . .353
Figure 2-122: Source-side CRC Component Locations for the Compressed Data Stream . . . . . . . . . . .355
Figure 2-123: Mapping of Compressed Data Bytes to CRC Engines . . . . . . . . . . . . . . . . . . . . . . . . . . .356
Figure 2-124: CRC Calculation Locations for the Reconstructed Image . . . . . . . . . . . . . . . . . . . . . . . .357
Figure 2-125: EOC Symbols on VSR Lines for 4-slice DSC Example
Stacked Frame 3D Stereo Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
Figure 2-126: DSC Bitstream Mapping to 128b/132b Link Layer Link Symbols. . . . . . . . . . . . . . . . . .360
Figure 2-127: DSC Bitstream Pass-through Enable Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
Figure 2-128: Logical Views of a DP Multi-stream Branch Device with (top)
and without (bottom) a Single-stream DPRX Plugged to DFP. . . . . . . . . . . . . . . . . . . . .368
Figure 2-129: DP Multi-stream Branch Device with Three DSC Decoders Configuration Example. . .372
Figure 2-130: DP Multi-stream Branch Device Enumeration
with Virtual DP Peer Devices Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . .373
Figure 2-131: DP Multi-stream Branch Device Configuration Example #1 . . . . . . . . . . . . . . . . . . . . . .374
Figure 2-132: DP Multi-stream Branch Device Configuration Example #2 . . . . . . . . . . . . . . . . . . . . . .375
Figure 2-133: Examples of AUX_CH Bridging Two I 2 C Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
Figure 2-134: DP Source and Sink Device Action Flow Sequences
when a Hot Plug Detect Event Occurs (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
Figure 2-135: Messaging AUX Client in DP Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608
Figure 2-136: Messaging AUX Client Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610
Figure 2-137: DOWN_REQ_MSG and DOWN_REP_MSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
Figure 2-138: UP_REQ_MSG and UP_REP_MSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
Figure 2-139: Mapping Message Transaction to Multiple Sideband MSGs
(SB MSG CRC Is the Sideband_MSG_Data_CRC Field) . . . . . . . . . . . . . . . . . . . . . . . .622
Figure 2-140: Relative Address Update along the Path Using Example Topology. . . . . . . . . . . . . . . . .631
Figure 2-141: AUX Error while Delivering a DOWN_REQ_MSG . . . . . . . . . . . . . . . . . . . . . . . . . . . .639
Figure 2-142: AUX Error while Delivering an UP_REQ_MSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .640
Figure 2-143: Source Device Delay Aggregation and Introduction of Delay Stamps. . . . . . . . . . . . . . .663
Figure 2-144: DisplayPort Monitor Connected through a Repeater Device . . . . . . . . . . . . . . . . . . . . . .665
Figure 2-145: Delay Compensation for Audio-to-video Synchronization. . . . . . . . . . . . . . . . . . . . . . . .666
Figure 2-146: DisplayPort Source Device Streaming Audio-to-video Streams to Multiple Monitors . .667
Figure 2-147: Delay Compensation for Audio-to-video Sync in a Multi-monitor Configuration. . . . . .668
Figure 2-148: Delay Compensation for Audio-to-audio Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .669
Figure 2-149: GTC Value Measurement Point by GTC Primary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .675
Figure 2-150: Lock Acquisition and Maintenance Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .676
Figure 2-151: AUX Transactions for GTC Synchronization (Informative). . . . . . . . . . . . . . . . . . . . . . .682
Figure 2-152: Pictorial Representation of Video Frame and Active Frame. . . . . . . . . . . . . . . . . . . . . . .688
Figure 2-153: Panel Replay Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .690
Figure 2-154: DP Source Device Panel Replay States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .695
Figure 2-155: DP Sink Device Panel Replay Mode States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .696
Figure 2-156: Panel Replay with no Live Active Frame Update. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .697
Figure 2-157: Full-screen Live Active Frame Update in Panel Replay Mode. . . . . . . . . . . . . . . . . . . . .698
Figure 2-158: Panel Replay with Selective Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .700
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Figure 3-1: DP PHY Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .702
Figure 3-2: Differential Voltage and Differential Voltage Peak-to-peak Definition. . . . . . . . . . . . . .707
Figure 3-3: Pre-emphasis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .709
Figure 3-4: Character-to-Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .712
Figure 3-5: AUX_CH Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .720
Figure 3-6: AUX_CH Self-clocking with Manchester-II Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . .721
Figure 3-7: AUX_SYNC Pattern and AUX STOP Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .722
Figure 3-8: V AUX_PP_MEAN Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .725
Figure 3-9: DP AUX IC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .726
Figure 3-10: AUX_CH EYE Mask at TX Device Connector Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .729
Figure 3-11: AUX_CH EYE Mask at RX Device Connector Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .730
Figure 3-12: Link Training LANEx_CR_DONE Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .745
Figure 3-13: Link Training LANEx_CHANNEL_EQ_DONE Sequence . . . . . . . . . . . . . . . . . . . . . . .750
Figure 3-14: Link Training LANEx_CR_DONE Sequence
for Maximum Link Data Bandwidth Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .752
Figure 3-15: Link Training LANEx_CHANNEL_EQ_DONE Sequence
for Maximum Link Data Bandwidth Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .753
Figure 3-16: POST_LT_ADJ_REQ Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .755
Figure 3-17: DPTX FEC Encoding (Logical View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .759
Figure 3-18: DPRX FEC Decoding (Logical View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .760
Figure 3-19: Schematic RS Encoder Representation for 8b/10b (Informative). . . . . . . . . . . . . . . . . . .761
Figure 3-20: Interleaved FEC Block Transport for 2- and 4-lane Configurations. . . . . . . . . . . . . . . . .762
Figure 3-21: Interleaved FEC Block Transport for 1-lane Configuration . . . . . . . . . . . . . . . . . . . . . . .762
Figure 3-22: Two-way FEC Interleaving for 2- and 4-lane Configurations in DPTX. . . . . . . . . . . . . .763
Figure 3-23: Two-way FEC Interleaving for 2- and 4-lane Configurations in DPRX. . . . . . . . . . . . . .763
Figure 3-24: Two-way FEC Interleaving for 1-lane Configuration in DPTX . . . . . . . . . . . . . . . . . . . .764
Figure 3-25: Two-way FEC Interleaving for 1-lane Configuration in DPRX. . . . . . . . . . . . . . . . . . . .764
Figure 3-26: FEC_DECODE_EN Control Link Symbol Sequence Transmission
(4- and 2-lane Configuration Example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .771
Figure 3-27: FEC_DECODE_DIS Control Link Symbol Sequence Transmission
(4- and 2-lane Configuration Example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .771
Figure 3-28: 128b/132b Link Layer-capable DP Source and Sink Device Connection,
Highlighting PHY Logical Sub-layer Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .772
Figure 3-29: DPTX 128b/132b PHY Logical Sub-layer Diagram (Informative) . . . . . . . . . . . . . . . . .774
Figure 3-30: DPRX 128b/132b PHY Logical Sub-layer Diagram (Informative) . . . . . . . . . . . . . . . . .775
Figure 3-31: Super Symbols – 128b/132b PHY Logical Sub-layer. . . . . . . . . . . . . . . . . . . . . . . . . . . .776
Figure 3-32: Control Link Symbol Bit Mapping – 128b/132b PHY Logical Sub-layer . . . . . . . . . . . .778
Figure 3-33: Four Physical Lanes (Link Symbols Shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .780
Figure 3-34: Conversion to Two Physical Lanes (Link Symbols Shown). . . . . . . . . . . . . . . . . . . . . . .780
Figure 3-35: Conversion to One Physical Lane (Link Symbols Shown). . . . . . . . . . . . . . . . . . . . . . . .780
Figure 3-36: Place Holder Symbol Mapping to 4-lane PHY Logical Main-Link (Informative). . . . . .781
Figure 3-37: Place Holder Symbol Mapping to 2-lane PHY Logical Main-Link (Informative). . . . . .782
Figure 3-38: Place Holder Symbol Mapping to 1-lane PHY Logical Main-Link (Informative). . . . . .782
Figure 3-39: Intra-super-symbol Shifting and Reverse Shifting
with Symbol Type Vector Field Value = 1000b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .783
Figure 3-40: Intra-super-symbol Shifting and Reverse Shifting
with Symbol Type Vector Field Value = X100b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784
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Figure 3-41: Intra-super-symbol Shifting and Reverse Shifting
with Symbol Type Vector Field Value = XX10b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784
Figure 3-42: Schematic RS Encoder Representation for 128b/132b (Informative). . . . . . . . . . . . . . . .786
Figure 3-43: 32-bit RS Parity Symbol Insertion (for 4-lane PHY Logical Main-Link) Example . . . . .787
Figure 3-44: RS FEC Parity Bytes Mapping for 4-/2-lane PHY Logical Main-Link . . . . . . . . . . . . . .788
Figure 3-45: RS FEC Parity Bytes Mapping for 1-lane PHY Logical Main-Link. . . . . . . . . . . . . . . . .789
Figure 3-46: Logical Diagrams of Pre-coding/Pre-coding Removal and Bit Pattern Example. . . . . . .790
Figure 3-47: 128b/132b PHY Logical Sub-layer Link TPSs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .791
Figure 3-48: Link Training Completion and RS FEC/Pre-coding Enablement. . . . . . . . . . . . . . . . . . .792
Figure 3-49: Serial Bit Transmission Order of CDI field and 32-bit Link Symbols . . . . . . . . . . . . . . .795
Figure 3-50: Bit Sequence Lists Illustration for 4-lane PHY Logical Main-Link. . . . . . . . . . . . . . . . .799
Figure 3-51: Bit Sequence Lists Illustration for 1-lane PHY Logical Main-Link. . . . . . . . . . . . . . . . .806
Figure 3-52: Main-Link Differential Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .822
Figure 3-53: PE vs. TX_MEQ Specification (Normative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .825
Figure 3-54: HBR3 Receiver Jitter Output/Input Tolerance Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . .835
Figure 3-55: HBR2 Receiver Jitter Output/Input Tolerance Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . .837
Figure 3-56: HBR Jitter Output/Input Tolerance Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .838
Figure 3-57: RBR Jitter Output/Input Tolerance Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .839
Figure 3-58: HBR3/HBR2 Variable EYE Height Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .841
Figure 3-59: HBR/RBR EYE Mask at Upstream Device DFP Connector Pins . . . . . . . . . . . . . . . . . .842
Figure 3-60: Downstream Device UFP EYE Mask at TP3_EQ (HBR) or TP3 (RBR). . . . . . . . . . . . .844
Figure 3-61: Reference Receiver CTLE for TP3_CTLE and
TP2_CTLE Test Point for HBR3 Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .846
Figure 3-62: Reference Receiver Equalizer for HBR3 with Reference Receiver DFE . . . . . . . . . . . . .847
Figure 3-63: Reference Receiver Equalizer for HBR2 Transfer Function. . . . . . . . . . . . . . . . . . . . . . .848
Figure 3-64: Reference Receiver Equalizer for HBR Transfer Function. . . . . . . . . . . . . . . . . . . . . . . .849
Figure 3-65: Enhanced Reference Receiver CTLE for HBR Relative to
Reference Receiver CTLE for HBR and HBR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .851
Figure 3-66: DPTX and DPRX Connected by way of a Detachable Cable. . . . . . . . . . . . . . . . . . . . . .852
Figure 3-67: DPRX with a Tethered USB Type-C Plug Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .852
Figure 3-68: UHBR SSC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .853
Figure 3-69: 3-tap FFE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .854
Figure 3-70: FFE Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .854
Figure 3-71: 3-tap FFE Example Waveform (for Preset #7 of Table 3-53). . . . . . . . . . . . . . . . . . . . . .856
Figure 3-72: UHBRx Reference Receiver CDR OJTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .857
Figure 3-73: Reference Receiver CTLE for UHBR10 Curves (Normative) . . . . . . . . . . . . . . . . . . . . .860
Figure 3-74: UHBR10 1-tap Reference Receiver DFE Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861
Figure 3-75: UHBRx EYE Opening Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .864
Figure 3-76: Reference Receiver CTLE for UHBR13.5 Curves (Informative). . . . . . . . . . . . . . . . . . .867
Figure 3-77: 3-tap Reference Receiver DFE Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .868
Figure 3-78: Reference Receiver CTLE for UHBR20 Curves (Informative) . . . . . . . . . . . . . . . . . . . .871
Figure 3-79: 3-tap Reference Receiver DFE Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .872
Figure 3-80: DP Topology Example with LTTPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .877
Figure 3-81: Signal Routing Mandates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .878
Figure 3-82: Partitioning within the DPCD LTTPR Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .879
Figure 3-83: LTTPR AUX UFP State Machine (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .885
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Figure 3-84: LTTPR AUX DFP State Machine (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .886
Figure 3-85: AUX Read that Does Not Target an LTTPR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .887
Figure 3-86: AUX Read that Targets Only an LTTPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .887
Figure 3-87: AUX Write that Does Not Target an LTTPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .888
Figure 3-88: AUX Write that Targets an LTTPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .888
Figure 3-89: Laptop and Docking Station Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .894
Figure 3-90: LTTPR Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .895
Figure 3-91: Link Training High-level Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .896
Figure 3-92: Start of LANEx_CR_DONE Sequence with LTTPR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .898
Figure 3-93: Read Status of LTTPR2 Lanes 0 and 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .899
Figure 3-94: DPTX Adjusts Output Voltage Swing and Pre-emphasis. . . . . . . . . . . . . . . . . . . . . . . . .899
Figure 3-95: LTTPR2 Achieved LANEx_CR_DONE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .899
Figure 3-96: DPTX Initiates LANEx_CHANNEL_EQ_DONE Sequence with LTTPR2 . . . . . . . . . .900
Figure 3-97: LTTPR2 Achieved LANEx_CHANNEL_EQ_DONE Sequence. . . . . . . . . . . . . . . . . . .900
Figure 3-98: DPTX Ends LTTPR2 Link Training. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .901
Figure 3-99: Start of LANEx_CR_DONE Sequence with LTTPR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .901
Figure 3-100: Determine LTTPR1’s LANEx_CR_DONE Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .902
Figure 3-101: LTTPR2 Adjusts Output Voltage Swing and Pre-emphasis . . . . . . . . . . . . . . . . . . . . . . .902
Figure 3-102: LTTPR1 Achieved LANEx_CHANNEL_EQ_DONE Sequence. . . . . . . . . . . . . . . . . . .903
Figure 3-103: End LTTPR1 Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .903
Figure 3-104: Start of LANEx_CR_DONE Sequence with DPRX. . . . . . . . . . . . . . . . . . . . . . . . . . . . .904
Figure 3-105: DPRX Achieved LANEx_CR_DONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .905
Figure 3-106: Start of LANEx_CHANNEL_EQ_DONE Sequence with DPRX . . . . . . . . . . . . . . . . . .905
Figure 3-107: Determine DPRX’s LANEx_CHANNEL_EQ_DONE Sequence Status . . . . . . . . . . . . .906
Figure 3-108: DPRX Achieved LANEx_CHANNEL_EQ_DONE Sequence. . . . . . . . . . . . . . . . . . . . .906
Figure 3-109: End Link Training. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .907
Figure 4-1: Type C1 Cable Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .912
Figure 4-2: Type C2 Cable Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .912
Figure 4-3: Type C3 Cable Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .912
Figure 4-4: Type A1 Resizing Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913
Figure 4-5: Type A2 Resizing Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913
Figure 4-6: Type E1 Extension Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .914
Figure 4-7: Bulk Cable Construction (Informative – for Reference Only) . . . . . . . . . . . . . . . . . . . . .916
Figure 4-8: DP Connector Differential Impedance Profile Measurement Data Example . . . . . . . . . .918
Figure 4-9: mDP Connector Differential Impedance Profile Measurement Data Example. . . . . . . . .919
Figure 4-10: Mixed Mode Differential Insertion Loss
for HBR Cable Assembly Types C1, C2, and C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .921
Figure 4-11: Mixed Mode Differential Insertion Loss for HBR Resizing Adapter. . . . . . . . . . . . . . . .922
Figure 4-12: Mixed Mode Differential Insertion Loss for Extension Cable . . . . . . . . . . . . . . . . . . . . .923
Figure 4-13: Mixed Mode Differential RL for HBR Cable Assembly/Adapter (DP Connector) . . . . .924
Figure 4-14: Mixed Mode Differential RL for HBR Cable Assembly/Adapter (mDP Connector). . . .925
Figure 4-15: Near-End Total Noise (peak) for HBR Cable Assembly . . . . . . . . . . . . . . . . . . . . . . . . .926
Figure 4-16: Power Sum Equal Level Far-End Total Noise (peak) for HBR Cable Assembly. . . . . . .928
Figure 4-17: Intra-pair Skew Measurement Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .929
Figure 4-18: Inter-pair Skew Measurement Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .930
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Figure 4-19: Mixed Mode Differential Insertion Loss (SDD21) Mask of RBR Cable . . . . . . . . . . . . .931
Figure 4-20: Mixed Mode Differential Return Loss (SDD11) of RBR Cable. . . . . . . . . . . . . . . . . . . .932
Figure 4-21: Near-End Total Noise (peak) for RBR Cable Assembly. . . . . . . . . . . . . . . . . . . . . . . . . .933
Figure 4-22: Far-End Total Noise (peak) for RBR Cable Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . .934
Figure 4-23: UHBR10 Insertion Loss Fit at Nyquist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .936
Figure 4-24: HBR3 Insertion Loss Fit at Nyquist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .936
Figure 4-25: HBR2 Insertion Loss Fit at Nyquist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .937
Figure 4-26: HBR Insertion Loss Fit at Nyquist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .937
Figure 4-27: HBR3 IMR as a Function of ILFitAtNq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .938
Figure 4-28: HBR3 IRL as a Function of ILFitAtNq. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .939
Figure 4-29: External Cable Connector Assembly Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .942
Figure 4-30: Connector Mating Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .943
Figure 4-31: DisplayPort External Connector Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .947
Figure 4-32: DisplayPort External Cable-Connector Assembly Drawings . . . . . . . . . . . . . . . . . . . . . .948
Figure 4-33: Recommended External Connector Orientations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .949
Figure 4-34: Plug Overmold Dimensions for Non-Latch Plug Connector . . . . . . . . . . . . . . . . . . . . . .949
Figure 4-35: Fully Mated Condition for DP External Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . .950
Figure 4-36: Recommended PCB Layout for DP External Cable-Connector Assembly. . . . . . . . . . . .951
Figure 4-37: Reference Design for Four DP External Connectors on a PCI Card. . . . . . . . . . . . . . . . .952
Figure 4-38: Panel Cut Out Reference Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .952
Figure 4-39: mDP Cable Connector Assembly Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .955
Figure 4-40: mDP-to-DP Cable Connector Assembly Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .956
Figure 4-41: DP-to-mDP Cable Connector Assembly Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .957
Figure 4-42: mDP-to-DP Adapter Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .958
Figure 4-43: DP-to-mDP Adapter Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .959
Figure 4-44: mDP Cable Extender Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .960
Figure 4-45: mDP Cable-Connector (Plug) Dimensions – 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .965
Figure 4-46: mDP Cable-Connector (Plug) Dimensions – 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .966
Figure 4-47: Mini DisplayPort Connector (Receptacle) Dimensions – 1 . . . . . . . . . . . . . . . . . . . . . . .967
Figure 4-48: Mini DisplayPort Connector (Receptacle) Dimensions – 2 . . . . . . . . . . . . . . . . . . . . . . .968
Figure 4-49: Fully Mated mDP Connector Illustrating Mating Levels . . . . . . . . . . . . . . . . . . . . . . . . .969
Figure 4-50: Recommended mDP Connector PCB Contacts and Mounting. . . . . . . . . . . . . . . . . . . . .971
Figure 4-51: Reference Design for Four mDP Connectors on a Reduced Height PCI Card – 1. . . . . .972
Figure 4-52: Reference Design for Four mDP Connectors on a Reduced Height PCI Card – 2. . . . . .973
Figure 4-53: Panel-side Internal PCB Mount Receptacle Connector with Pin 1 Shown. . . . . . . . . . . .975
Figure 4-54: Panel-side Internal PCB Mount Receptacle Connector (in mm) – 1. . . . . . . . . . . . . . . . .976
Figure 4-55: Panel-side Internal PCB Mount Receptacle Connector (in mm) – 2. . . . . . . . . . . . . . . . .977
Figure 4-56: PCB Mount Connector Recommended Footprint Layout (in mm). . . . . . . . . . . . . . . . . .978
Figure 4-57: Panel-side Internal Cable Plug Connector (in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .978
Figure 4-58: Contact and Mechanical Guide Details (in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .979
Figure 4-59: Mating Condition (Reference) of Panel Side Internal Cable Connector (in mm). . . . . . .980
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Figure 5-1: HPD Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .991
Figure 5-2: Sink Device Power State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1001
Figure 5-3: CEC Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1015
Figure 5-4: DP-to-Dual-link DVI Cable Adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1017
Figure 5-5: DPTX with an Embedded PHY Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1032
Figure 5-6: DPRX with an Embedded PHY Repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1033
Figure 5-7: PHY Layer Topologies without and with One LTTPR Function
between DFP of an Active Cable and a DPRX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1037
Figure 5-8: Active Cable Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1040
Figure 5-9: Extended Wake Request and SLEEP Power State Entry Flow
when Active Cable Requests Extended Wake. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1041
Figure 5-10: Wake from SLEEP Power State after Extended Wake Request
from Active Cable Is Granted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1042
Figure 5-11: Extended Wake Request and SLEEP Power State Entry Flow
when Active Cable and DP Sink Device Both Request Extended Wake . . . . . . . . . . . .1043
Figure 5-12: Wake from SLEEP Power State after Both Extended Wake Requests
from Active Cable and DP Sink Device Are Granted. . . . . . . . . . . . . . . . . . . . . . . . . . .1044
Figure 5-13: DP Tunneling from DP Source Device to DP Sink/Branch Device . . . . . . . . . . . . . . . .1045
Figure 5-14: DP Output from a DP Downstream-facing Tunneling Bridge Device . . . . . . . . . . . . . .1045
Figure 5-15: Dummy Symbol Signaling with SST Mapping Protocol
when Panel Replay Optimization with DP Tunneling Is Enabled . . . . . . . . . . . . . . . . .1047
Figure 5-16: Dummy Symbol Signaling with MST Mapping Protocol and
128b/132b Channel Coding when Panel Replay Optimization
with DP Tunneling Is Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1048
Figure A-1: Audio_Stream SDPs Transfer with No Video or during Video Vertical Blanking . . . .1051
Figure A-2: Audio_Stream SDPs Transfer with Video during Video Vertical Active Period. . . . . .1051
Figure D-1: AUX_CH EYE Mask at Transmitting IC Package Pins (Informative). . . . . . . . . . . . . .1063
Figure D-2: AUX_CH EYE Mask at Receiving IC Package Pins (Informative) . . . . . . . . . . . . . . . .1064
Figure G-1: Link Quality Management with Fast Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . .1081
Figure G-2: Link Quality Management Source Fail Safe Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1083
Figure G-3: DP Sink Device Power Management State Diagram
with State 2S for a DP Upstream Device Not Capable of HPD Assertion Handling . . .1084
Figure H-1: Frame/Field Sequential 3D Stereo Video Left- and Right-eye View
Frame Mapping, Transport Timing, and CRC Value Calculation . . . . . . . . . . . . . . . . .1088
Figure H-2: Stacked Frame 3D Stereo Video Left- and Right-eye View
Frame Mapping, Transport Timing, and CRC Value Calculation . . . . . . . . . . . . . . . . .1089
Figure H-3: Pixel Interleaved 3D Stereo Video Left- and Right-eye View Frame Pixel Mapping . .1090
Figure H-4: Pixel Interleaved 3D Stereo Video Left- and Right-eye View
Transport Timing and CRC Value Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1091
Figure H-5: Side-by-side 3D Stereo Video Left- and Right-eye View
Frame Mapping, Transport Timing, and CRC Value Calculation . . . . . . . . . . . . . . . . .1092
Figure H-6: Top-to-bottom 3D Stereo Video Left- and Right-eye View
Frame Mapping, Transport Timing, and CRC Value Calculation . . . . . . . . . . . . . . . . .1093
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Figures
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VESA DP Standard Version 2.0
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Figure I-1: QUERY_STREAM_ENCRYPTION_STATUS Message Transaction
Execution when MST Source Device Is Directly Connected to Sink Device. . . . . . . . .1111
Figure I-2: QUERY_STREAM_ENCRYPTION_STATUS Message Transaction
Forwarding and Execution when MST Source Device Is Connected to
Sink Device by way of MST Branch Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1111
Figure M-1: DP Source Device 128b/132b Link Layer Logical View
without Place Holders (Informative) (Alternative to Figure 2-104) . . . . . . . . . . . . . . . .1123
Figure M-2: DP Sink Device 128b/132b Link Layer Logical View
without Place Holders (Informative) (Alternative to Figure 2-105) . . . . . . . . . . . . . . . .1124
Figure M-3: DP Branch Device 128b/132b Link Layer Logical View
without Place Holders (Informative) (Alternative to Figure 2-106) . . . . . . . . . . . . . . . .1124
Figure M-4: DPTX 128b/132b PHY Logical Sub-layer Diagram (Informative)
(Alternative to Figure 3-29). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1126
Figure M-5: DPRX 128b/132b PHY Logical Sub-layer Diagram (Informative)
(Alternative to Figure 3-30). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127
Figure M-6: Insertion of PHY Sync Symbols, CDI Bits, RS Padding Bits,
and RS Parity Symbols in 4-lane PHY Logical Main-Link (Informative) . . . . . . . . . . .1128
Figure M-7: Insertion of PHY Sync Symbols, CDI Bits, RS Padding Bits,
and RS Parity Symbols in 2-lane PHY Logical Main-Link (Informative) . . . . . . . . . . .1129
Figure M-8: Insertion of PHY Sync Symbols, CDI Bits, RS Padding Bits,
and RS Parity Symbols in 1-lane PHY Logical Main-Link (Informative) . . . . . . . . . . .1130
Figure N-1: UHBRx PRBS7 Initial Bit Sequences and Polynomial. . . . . . . . . . . . . . . . . . . . . . . . . .1131
Figure N-2: UHBRx PRBS9 Initial Bit Sequences and Polynomial. . . . . . . . . . . . . . . . . . . . . . . . . .1132
Figure N-3: UHBRx PRBS11 Initial Bit Sequences and Polynomial. . . . . . . . . . . . . . . . . . . . . . . . .1132
Figure N-4: UHBRx PRBS15 Initial Bit Sequences and Polynomial. . . . . . . . . . . . . . . . . . . . . . . . .1133
Figure N-5: UHBRx PRBS23 Initial Bit Sequences and Polynomial. . . . . . . . . . . . . . . . . . . . . . . . .1133
Figure N-6: UHBRx PRBS31 Initial Bit Sequences and Polynomial. . . . . . . . . . . . . . . . . . . . . . . . .1134
Figure O-1: HBR3/HBR2 EYE Opening Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1135
Figure O-2: UHBRx EYE Opening Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1136