arm_cortexm3_processor_trm_100165_0201_00_en.pdf

【实例截图】

【核心代码】

Contents
ARM ® Cortex ® -M3 Processor Technical Reference
Manual
Preface
About this book ............................................................................................................ 7
Feedback .................................................................................................................... 10
Chapter 1 Introduction
1.1 About the processor ................................................................................................ 1-12
1.2 Processor features list .............................................. .............................................. 1-13
1.3 External interfaces .................................................................................................. 1-14
1.4 Optional implementation components .................................. .................................. 1-15
1.5 Product documentation ............................................................................................ 1-16
1.6 Product revisions .................................................................................................... 1-19
Chapter 2 Functional Description
2.1 About the functions .................................................................................................. 2-22
2.2 Processor features list .............................................. .............................................. 2-23
2.3 Interfaces ................................................................................................................ 2-25
Chapter 3 Programmers Model
3.1 About the programmers’ model ....................................... ....................................... 3-29
3.2 Modes of operation and execution .......................................................................... 3-30
3.3 Instruction set summary .......................................................................................... 3-31
3.4 Processor memory model ........................................................................................ 3-37
ARM 100165_0201_00_en Copyright © 2005-2008, 2010, 2015 ARM. All rights reserved. 4
Non-Confidential
3.5 Write buffer .............................................................................................................. 3-40
3.6 Exclusive monitor .................................................................................................... 3-41
3.7 Bit-banding .............................................................................................................. 3-42
3.8 Processor core register summary ............................................................................ 3-44
3.9 Exceptions .............................................................................................................. 3-46
Chapter 4 System Control
4.1 System control registers .......................................................................................... 4-49
4.2 Auxiliary Control Register, ACTLR .......................................................................... 4-51
4.3 CPUID Base Register, CPUID ................................................................................ 4-52
4.4 Auxiliary Fault Status Register, AFSR .................................................................... 4-53
Chapter 5 Memory Protection Unit
5.1 About the MPU ........................................................................................................ 5-55
5.2 MPU functional description ...................................................................................... 5-56
5.3 MPU programmers model table .............................................................................. 5-57
Chapter 6 Nested Vectored Interrupt Controller
6.1 NVIC functional description .......................................... .......................................... 6-59
6.2 NVIC programmers’ model ...................................................................................... 6-60
Chapter 7 Debug
7.1 Debug configuration ................................................................................................ 7-63
7.2 AHB-AP debug access port .................................................................................... 7-67
7.3 Flash Patch and Breakpoint Unit (FPB) .................................................................. 7-70
Chapter 8 Data Watchpoint and Trace Unit
8.1 DWT functional description ...................................................................................... 8-73
8.2 DWT Programmers’ model ...................................................................................... 8-74
Chapter 9 Instrumentation Trace Macrocell Unit
9.1 ITM functional description ........................................................................................ 9-77
9.2 ITM programmers’ model ........................................................................................ 9-78
9.3 ITM Trace Privilege Register, ITM_TPR .................................................................. 9-79
Chapter 10 Embedded Trace Macrocell
10.1 About the ETM ...................................................................................................... 10-81
10.2 ETM functional description .................................................................................... 10-82
10.3 ETM Programmers model .......................................... .......................................... 10-88
Chapter 11 Trace Port Interface Unit
11.1 About the TPIU .................................................................................................... 11-104
11.2 TPIU functional description .................................................................................. 11-105
11.3 TPIU programmers model ......................................... ......................................... 11-107
Appendix A Revisions
A.1 Revisions .................................................. .................................................. Appx-A-117