verilog仿真使用PLI的学习手册

【实例简介】verilog仿真使用PLI的学习手册

The Verilog PLI Handbook英文644页

【实例截图】

【核心代码】

Table of Contents
Dedication
xxi
v
Table of Contents vii
About the Author xv
List of Examples
Foreword
Acknowledgments
Introduction
Intended Audience:
The IEEE 1364 Verilog PLI standard
The history of the Verilog PLI
1985: The TF routines
1988: The ACC routines
1990: The OVI PLI 1.0 standard
1993: The OVI PLI 2.0 standard
1995: The IEEE 1364-1995 PLI standard and VPI routines
2001: The IEEE 1364-2001 PLI standard
Ambiguities in the Verilog PLI standard
Organization of this book
About the PLI examples in this book
Other sources of information
xvii
xxiii
1
1
2
2
2
3
3
3
4
4
5
5
6
7
viii Using The Verilog PLI
Part One: The VPI Portion of the Verilog PLI Standard
Creating PLI Applications Using VPI Routines
1.1
1.2
1.3
1.4
1.5
The capabilities of the Verilog PLI
General steps to create a PLI application
User-defined system tasks and system functions
The $hello PLI application example
The $show_value PLI application example
Interfacing VPI Applications to Verilog Simulators
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
General PLI terms as used in this book
System tasks and system functions
Instantiated Verilog designs
How PLI applications work
calltf routines
compiletf routines
sizetf routines
VPI Simulation callback routines
PLI routine inputs and outputs
2.10
2.11
2.12
2.13
A complete system function example — $pow
Interfacing PLI applications to Verilog simulators
Using the VPI user_data field
Compiling and linking PLI applications
How to Use the VPI Routines
3.10
3.11
3.12
3.13
3.14
3.15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Specification of $show_all_nets and $show_all_signals
The VPI routine library
Advantages of the VPI library
Verilog HDL objects
Obtaining object handles
Accessing the arguments of a system task/function
Printing messages from VPI applications
Accessing object properties
Reading the logic values of Verilog objects
Reading the current simulation time
Controlling simulation from PLI applications
A complete PLI application using VPI routines
Obtaining handles for reg and variable data types
Obtaining a handle to the current hierarchy scope
Obtaining handles to multiple task/function arguments
11
11
13
14
15
19
27
27
29
31
34
36
37
39
41
42
42
46
51
53
55
55
56
57
59
62
65
66
67
69
71
73
74
78
85
91
CHAPTER 1:
CHAPTER 2:
CHAPTER 3:
ix
CHAPTER 4: Details about the VPI Routine Library
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
PLI application performance considerations
The VPI string buffer
VPI error handling
VPI object diagrams
Obtaining handles for objects
System task and system function objects
Storing data for each instance of a system task/function
Traversing Verilog hierarchy using object relationships
Writing messages to files
Reading and using simulation times
User-defined invocation options
Controlling Simulations
CHAPTER 5: Reading and Modifying Values Using VPI Routines
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Accessing objects which have logic values
Reading object logic values
Writing values to Verilog objects
Returning logic values of system functions
Reading and writing automatic variables
Reading IEEE 1364-2001 Verilog attributes
Reading IEEE 1364-1995 specparam constant attributes
Accessing Verilog net, reg, memory and arrays
Reading and modifying delay values
CHAPTER 6: Synchronizing to Simulations Using VPI Callbacks
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
PLI application callbacks
Sharing information between callback routines
Registering simulation callback routines
Removing scheduled callbacks
Avoiding memory leaks with simulation callbacks
Simulation action-related callbacks
Simulation time-related callbacks
Simulation event-related callbacks
CHAPTER 7: Interfacing to C Models Using VPI Routines
7.1
7.2
7.3
7.4
7.5
7.6
How to interface C models with Verilog simulations
Creating the C language model
A C model example
Creating a Verilog shell module
Creating a combinational logic interface to a C model
Creating a sequential logic interface to a C model
97
98
99
100
102
106
116
122
128
137
140
144
148
151
151
152
173
177
180
182
182
185
186
197
197
198
201
204
205
206
216
235
241
242
244
245
248
249
256
4.10
4.11
4.12
Using The Verilog PLI
7.7
7.8
7.9
7.10
Synchronizing with the end of a simulation time step
Synchronizing with a future simulation time step
Allocating storage within a C model
Representing propagation delays in a C model
259
263
263
267
Part Two: The TF/ACC Portion of the Verilog PLI Standard
CHAPTER 8: Creating PLI Applications Using TF and ACC Routines 273
8.1
8.2
8.3
8.4
8.5
The capabilities of the Verilog PLI
General steps to create a PLI application
User-defined system tasks and system functions
The $hello PLI application example
The $show_value PLI application example
273
275
276
277
280
CHAPTER 9: Interfacing TF/ACC Applications to Verilog Simulators 287
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
General PLI terms as used in this book
System tasks and system functions
Instantiated Verilog designs
How PLI applications work
calltf routines
checktf routines
sizetf routines
misctf routines
PLI routine inputs and outputs
A complete system function example — $pow
Interfacing PLI applications to Verilog simulators
Using the user_data field
Compiling and linking PLI applications
287
289
291
294
296
297
299
300
302
303
305
310
311
CHAPTER 10: How to Use the TF Routines 313
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
The TF Library
System tasks and system functions
The PLI string buffer
Controlling simulation
Printing messages
Checking system task/function arguments
The TF work area
Reading and using simulation times
Reading simulation invocation options
Utility TF routines
A complete PLI application using TF Routines
313
315
318
319
319
323
325
329
334
335
337
x
xi
CHAPTER 11: Reading and Writing Values Using TF Routines 341
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Working with a 4-logic value, multiple strength level system
How the PLI writes values into Verilog
Reading and writing 2-state values
Reading and writing 4-state logic values using C strings
Reading Verilog strings
Reading and writing 4-state values using aval/bval encoding
Reading 4-state logic values with strengths
Reading from and writing into Verilog memory arrays
341
342
344
349
357
358
371
378
CHAPTER 12: Synchronizing to Simulations Using Misctf Routines 401
12.1
12.2
12.3
12.4
12.5
12.6
12.7
The purpose of the misctf routine
Automatic callbacks for simulation events
Application scheduled callbacks at the end of a time step
Application-scheduled callbacks at a future simulation time
System task/function argument value change callbacks
Simulation save and restart checkpoint files
A complete example of using misctf routine callbacks
401
405
408
414
418
422
424
CHAPTER 13: Interfacing to C Models Using TF Routines 431
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
How to interface C models with Verilog simulations
Creating the C language model
A C model example
Creating a Verilog shell module
Creating a combinational logic interface to a C model
Creating a sequential logic interface to a C model
Synchronizing with the end of a simulation time step
Synchronizing with a future simulation time step
Allocating storage within a C model
Representing propagation delays in a C model
432
434
435
437
439
445
448
451
451
455
CHAPTER 14: How to Use the ACC Routines 459
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
Specification of $show_all_nets and $show_all_signals
The ACC routine library
Advantages of the ACC library
Verilog HDL objects
ACC handle routines
ACC next routines
Accessing object types and fulltypes
Accessing the names of objects
The ACC string buffer
Reading the logic values of Verilog objects
459
460
462
463
465
466
468
470
471
472
xii Using The Verilog PLI
14.11
14.12
14.13
14.14
A complete PLI application using ACC routines
Accessing handles for reg and variable data types
Obtaining handles to the current hierarchy scope
Obtaining handles to multiple task/function arguments
473
475
479
483
CHAPTER 15: Details on the ACC Routine Library 487
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
PLI application performance considerations
Initializing and configuring ACC routines
ACC routine error handling
Using ACC object diagrams
Using ACC handle routines
Using ACC next routines
Traversing Verilog hierarchy using object relationships
Traversing hierarchy across module ports
Identifying modules and library cells
15.10
15.11
15.12
15.13
15.14
15.15
Accessing loads and drivers
Accessing model timing
Counting the number of objects
Collecting and maintaining lists of object handles
Obtaining object handles using an object’s name
Comparing ACC handles
487
489
492
494
498
499
501
506
512
514
516
523
525
528
532
CHAPTER 16: Reading and Modifying Values Using ACC Routines
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
16.11
16.12
16.13
16.14
16.15
Using ACC fetch routines
Reading object type properties
Accessing an object’s source code location
Reading the simulation invocation commands
Accessing objects in simulation which have logic values
Reading the values of system task/function arguments
Reading object logic values
Writing values into Verilog objects
Returning logic values of system functions
Reading module time scale information
Reading delay values
Writing delay values into an object
Reading parameter constant values
Using constants as model attributes
Reading and modifying path pulse controls
535
536
538
542
544
546
547
552
564
570
572
575
584
590
592
594
CHAPTER 17: Using the Value Change Link (VCL) 601
17.1
17.2
An overview of the VCL routines
Adding and removing VCL flags on Verilog objects
601
602
xiii
17.3
17.4
17.5
Using the VCL consumer routine
An example of using Value Change Link routines
Obtaining object handles from the consumer routine
605
608
609
CHAPTER 18: Interfacing to C Models Using ACC Routines 611
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10
How to interface C models with Verilog simulations
Creating the C language model
A C model example
Creating a Verilog shell module
Creating a combinational logic interface to a C model
Creating a sequential logic interface to a C model
Synchronizing with the end of a simulation time step
Synchronizing with a future simulation time step
Allocating storage within a C model
Representing propagation delays in a C model
612
614
615
618
619
624
627
631
631
637
Appendices
APPENDIX A: Linking PLI Applications to Verilog Simulators 641
A.1
A.2
A.3
A.4
The PLI interface mechanism
Linking to the Cadence Verilog-XL and NC-Verilog simulators
Linking to the Synopsys VCS simulator
Linking to the Model Technology ModelSim simulator
642
649
657
664
APPENDIX B: The IEEE 1364-2001 TF Routine Library 669
B.1 TF routine definitions 670
APPENDIX C: The IEEE 1364-2001 ACC Routine Library 685
C.1
C.2
ACC object relationships
ACC routine definitions
686
699
APPENDIX D: The IEEE 1364-2001 VPI Routine Library 719
D.1
D.2
VPI object relationships
VPI routine definitions
720
754
Index 767
About the CD 783
About the Author
M
r. Stuart Sutherland is a member of the IEEE Verilog standards committee,
where he is co-chair of the PLI standards task force and technical editor for the
PLI sections of the IEEE 1364 Verilog Language Reference Manual.
Mr. Sutherland has more than 18 years of experience in hardware design and over 14
years of experience with Verilog. He is the founder of Sutherland HDL Inc., located
in Portland Oregon. Sutherland HDL provides expert Verilog HDL and Verilog PLI
design services, including training, modeling, design verification and software tool
evaluation. Verilog PLI training is one of the specialties of Sutherland HDL. Prior to
founding Sutherland HDL in 1992, Mr. Sutherland was as an engineer at Sanders Dis-
play Products Division in New Hampshire, where he worked on high speed graphics
systems for the defense industry. In 1988, he became a senior applications engineer
for Gateway Design Automation, the founding company of Verilog. At Gateway,
which was acquired by Cadence Design Systems in 1989, Mr. Sutherland specialized
in training and support for logic simulation, timing analysis, fault simulation, and the
Verilog PLI. Mr. Sutherland has also worked closely with several EDA vendors to
specify, test and bring to market Verilog simulation products.
Mr. Sutherland holds a Bachelor of Science in Computer Science, with an emphasis in
Electronic Engineering Technology, from Weber State University (Ogden, Utah) and
Franklin Pierce College (Nashua, New Hampshire). He has taught Verilog engineer-
ing courses at the University of California, Santa Cruz (Santa Clara extension), and
has authored the “ Verilog 2001: A Guide to the New Features in Verilog”, “Verilog
HDL Quick Reference Guide” and “ Verilog PLI Quick Reference Guide”. He has pre-
sented tutorials and papers at the International Verilog Conference, EDA-Front-to-
Back Conference, DesignCon Conference, Synopsys User’s Group Conference, and
at the International Cadence User's Group Conference.
List of Examples
The source code files for the major examples used in this book are provided on a CD
located inside the back of this book. The examples can also be downloaded from the
Author’s web page. Go to http://www.sutherland-hdl.com , and navigate the links to:
“ The Verilog PLI Handbook” — “PLI Book Examples” .
CHAPTER 1: Creating PLI Applications Using VPI Routines
Example 1-1:
Example 1-2:
Example 1-3:
Example 1-4:
Example 1-5:
Example 1-6:
Example 1-7:
Example 1-8:
$hello — a VPI calltf routine for a PLI application
$hello — VPI register function for a PLI application
$hello — simulation results
$show_value — a VPI compiletf routine for a PLI application
$show_value — a VPI calltf routine for a PLI application
$show_value — a VPI register function for a PLI application
$show_value — a Verilog HDL test case using a PLI application
$show_value — sample output
16
18
19
21
23
24
24
25
CHAPTER 2: Interfacing VPI Applications to Verilog Simulators
Example 2-1:
Example 2-2:
Example 2-3:
Example 2-4:
$pow — a system function using VPI routines
$pow — sample simulation results
$pow — a VPI register function for a system function
a vlog_startup_routines array with 2 register functions
43
46
50
50
CHAPTER 3: How to Use the VPI Routines
Example 3-1:
Example 3-2:
Example 3-3:
Example 3-4:
Example 3-5:
Example 3-6:
Example 3-7:
Example 3-8:
$show_all_nets — using VPI routines to access simulation objects
$show_all_nets — a Verilog HDL test using a PLI application
$show_all_nets — simulation results using a PLI application
$show_all_signals, version 1 — printing values of all Verilog types
$show_all_signals — Verilog HDL test for the PLI application
$show_all_signals — simulation results using the PLI application
$show_all_signals, version 2 — obtaining the local scope handle
$show_all_signals, version 3 — obtaining handles for multiple tfargs
74
77
78
81
84
85
87
92
CHAPTER 4: Details about the VPI Routine Library
Example 4-1: PLIbook_count_args_vpi() — accessing system task/func. arguments 119
xviii Using The Verilog PLI
Example 4-2:
Example 4-3:
Example 4-4:
Example 4-5:
Example 4-6:
Example 4-7:
PLIbook_get_arg_handle_vpi() — accessing system task/func args
PLIbook_get_arg_handle_vpi() — efficient version
$list_pathout_ports — traversing Verilog hierarchy
$port_info — traversing hierarchy across module ports
$count_all_prims — traversing multiple levels of hierarchy
$test_invoke_options — testing for user-defined invocation options
120
125
131
134
136
146
CHAPTER 5: Reading and Modifying Values Using VPI Routines
Example 5-1:
Example 5-2:
Example 5-3:
Example 5-4:
Example 5-5:
Example 5-6:
Example 5-7:
Example 5-8:
Example 5-9:
Example 5-10:
Example 5-11:
PLIbook_get_arg_int_val_vpi() —reading values as 32-bit C integers
PLIbook_get_arg_real_val_vpi() — reading values as C doubles
PLIbook_get_arg_string_val_vpi() — reading Verilog string values
using vpi_get_value()to read 4-state values as a C string
$read_vecval — reading 4-state vector values as aval/bval pairs
$read_strengthval — reading logic and strength values
$read_timeval — reading time variable values
$realpow — returning values of system functions
using vpi_get_value() to read attribute constant values
$read_delays — reading module path delays
$mipd_delays — using vpi_put_delays()
CHAPTER 6: Synchronizing to Simulations Using VPI Callbacks
Example 6-1:
Example 6-2:
Example 6-3:
Example 6-4:
$read_test_vector — using VPI simulation action callbacks
$my_strobe — simulation callbacks at the end of the current time
$read_stimulus_ba — scheduling callbacks at a future time
$my_monitor — scheduling simulation callbacks at a future time
158
159
160
162
166
169
171
179
184
191
194
213
225
229
239
CHAPTER 7: Interfacing to C Models Using VPI Routines
Example 7-1:
Example 7-2:
Example 7-3:
Example 7-4:
Example 7-5:
Example 7-6:
Example 7-7:
Example 7-8:
scientific ALU C model — combinational logic version
Verilog shell module for the scientific ALU C model
combinational logic C model interface using VPI routines
sequential logic C model interface using VPI routines
C model interface synchronized to the end of a time step
scientific ALU C model with latched outputs
combinational logic interface to the latched scientific ALU C model
scientific ALU Verilog shell module with pin-to-pin path delays
247
248
252
257
260
264
265
268
CHAPTER 8: Creating PLI Applications Using TF and ACC Routines
Example 8-1:
Example 8-2:
Example 8-3:
Example 8-4:
$hello — a TF/ACC calltf routine for the PLI application
$show_value — a TF/ACC checktf routine for a PLI application
$show_value — a TF/ACC calltf routine for a PLI application
$show_value — a Verilog HDL test case using a PLI application
278
282
283
284
CHAPTER 9: Interfacing TF/ACC Applications to Verilog Simulators
Example 9-1:
Example 9-2:
$pow — a system function using TF/ACC routines
example veriusertfs array for registering TF/ACC PLI applications
304
309
xix
CHAPTER 10: How to Use the TF Routines
Example 10-1:
Example 10-2:
Example 10-3:
usin g the tf_setworkarea () and tf_getworkarea () routines
storing multiple values in the TF work area
$read_test_vector — using the TF routines
326
328
338
CHAPTER 11: Reading and Writing Values Using TF Routines
Example 11-1:
Example 11-2:
Example 11-3:
Example 11-4:
Example 11-5:
Example 11-6:
Example 11-7:
Example 11-8:
Example 11-9:
$realpow — using TF routines to read/write 2-state values
$exprinfo_test — using tf_exprinfo () to read 4-state values
$evaluatep_test — using tf_evaluatep ( ) to read 4-state values
$propagatep_test—using tf_propagatep () to write 4-state values
$nodeinfo_test—using the tf_nodeinfo () routine
$dump_mem_?? — using tf_nodeinfo () with Verilog memories
$fill_mem — using tf_nodeinfo () to modify Verilog memories
$dump_mem_bin — accessing a memory word bit; obvious method
$dump_mem_bin — accessing a memory word bit; efficient method
348
364
366
369
376
387
392
395
397
CHAPTER 12: Synchronizing to Simulations Using Misctf Routines
Example 12-1:
Example 12-2:
Example 12-3:
Example 12-4:
Example 12-5:
Example 12-6:
Example 12-7:
using the misctf reason input
partial-code for using automatic misctf routine callbacks
$my_strobe — using the tf_rosynchronize () routine
$read_stimulus — using the tf_setdelay () routine
$my_monitor1 — asynchronous argument value change callbacks
$my_monitor2 — synchronized analysis of argument value changes
$read_stimulus_ba — using several misctf routine callbacks
404
406
414
417
419
421
425
CHAPTER 13: Interfacing to C Models Using TF Routines
Example 13-1:
Example 13-2:
Example 13-3:
Example 13-4:
Example 13-5:
Example 13-6:
Example 13-7:
Example 13-8:
Example 13-9:
scientific ALU C model — combinational logic version
Verilog shell module for the scientific ALU C model
combinational logic C model interface using a calltf routine
combinational logic C model interface using a misctf routine
sequential logic C model interface using TF routines
C model interface synchronized to the end of a time step
scientific ALU C model with latched outputs
combinational logic interface to latched scientific ALU C model
scientific ALU Verilog shell module with pin-to-pin path delays
437
438
441
444
446
449
452
454
456
CHAPTER 14: How to Use the ACC Routines
Example 14-1:
Example 14-2:
Example 14-3:
Example 14-4:
Example 14-5:
Example 14-6:
Example 14-7:
Example 14-8:
$show_all_nets — using ACC routines in a PLI application
$show_all_nets — Verilog HDL test case for the PLI application
$show_all_nets — simulation results
$show_all_signals, version 1 — using theacc_next () routine
$show_all_signals1 — Verilog HDL test case for the PLI application
$show_all_signals1 — simulation results
$show_all_signals, version 2—obtaining a handle for the local scope
$show_all_signals, version 3—obtaining handles for multiple tfargs
473
474
475
477
478
479
482
484
xx Using The Verilog PLI
CHAPTER 15: Details on the ACC Routine Library
Example 15-1:
Example 15-2:
Example 15-3:
Example 15-4:
Example 15-5:
$list_pathout_ports — traversing Verilog hierarchy
$port_info — traversing Verilog hierarchy across module ports
$list_cells — working with module cells
$count_loads — using the acc_count () routine
$display_all_nets — using theacc_collect () routine
506
510
514
524
527
CHAPTER 16: Reading and Modifying Values Using ACC Routines
Example 16-1:
Example 16-2:
Example 16-3:
Example 16-4:
Example 16-5:
Example 16-6:
Example 16-7:
Example 16-8:
$print_invoke_commands — printing invocation commands
$list_nets — using acc_fetch_value ( ) to read values as strings
$read_vector_value — reading vector values as aval/bval pairs
$func_72bit — returning 4-state vector values with system functions
$list_prim_delays — reading typical delays
$list_path_delays — reading min:typ:max delay values
$mipd_delays — modifying min:typ:max delays
$list_params — reading parameter and specparam values
545
554
563
571
580
583
589
591
CHAPTER 17: Using the Value Change Link (VCL)
Example 17-1: $my_monitor — using the acc_vcl_add() routine 608
CHAPTER 18: Interfacing to C Models Using ACC Routines
Example 18-1:
Example 18-2:
Example 18-3:
Example 18-4:
Example 18-5:
Example 18-6:
Example 18-7:
scientific ALU C model — combinational logic version
Verilog shell module for the Scientific ALU C model
combinational logic C model interface using ACC routines
sequential logic C model interface using ACC routines
C model interface synchronized to the end of a time step
scientific ALU C model with latched outputs
combinational logic interface to latched scientific ALU C model
APPENDIX A: Linking PLI Applications to Verilog Simulators
Example A-1:
Example A-2:
Example A-3:
Example A-4:
Example A-5:
VPI register function for the $hello system function
sample vlog_startup_routines array
sample veriusertfs array, as used by many Verilog simulators
Sample Cadence TF/ACC bootstrap file
617
618
621
624
628
633
634
PLI table file to specify PLI applications for the VCS simulator
643
644
646
654
662