pcie_3.0_总线规范.pdf

【实例截图】

【核心代码】

Figures
FIGURE 1-1: PCI EXPRESS LINK.................................................................................................... 39
FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 41
FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 45
FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 47
FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 48
FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER.............................. 53
FIGURE 2-2: SERIAL VIEW OF A TLP............................................................................................. 56
FIGURE 2-3: GENERIC TLP FORMAT............................................................................................. 57
FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 58
FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 59
FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 64
FIGURE 2-7: 64-BIT ADDRESS ROUTING........................................................................................ 66
FIGURE 2-8: 32-BIT ADDRESS ROUTING........................................................................................ 66
FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 68
FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 68
FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER....................................................... 69
FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 72
FIGURE 2-13: TRANSACTION ID.................................................................................................... 72
FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 74
FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY........................ 78
FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 78
FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS.............................................. 79
FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 80
FIGURE 2-19: TPH TLP PREFIX .................................................................................................... 81
FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ............................................. 81
FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ............................................. 82
FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER......................... 83
FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ..... 83
FIGURE 2-24: MESSAGE REQUEST HEADER .................................................................................. 84
FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ........................................................... 94
FIGURE 2-26: LTR MESSAGE........................................................................................................ 96
FIGURE 2-27: OBFF MESSAGE ..................................................................................................... 97
FIGURE 2-28: COMPLETION HEADER FORMAT .............................................................................. 98
FIGURE 2-29: (NON-ARI) COMPLETER ID .................................................................................... 98
FIGURE 2-30: ARI COMPLETER ID................................................................................................ 99
FIGURE 2-31: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 105
FIGURE 2-32: FLOWCHART FOR SWITCH HANDLING OF TLPS..................................................... 107
FIGURE 2-33: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 112
FIGURE 2-34: VIRTUAL CHANNEL CONCEPT – AN ILLUSTRATION .............................................. 129
FIGURE 2-35: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM FLOW) ............. 129
FIGURE 2-36: AN EXAMPLE OF TC/VC CONFIGURATIONS.......................................................... 132
FIGURE 2-37: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER..................... 133 
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
13
FIGURE 2-38: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY
PROTECTION ........................................................................................................................ 148
FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 155
FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE.................................. 157
FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED
FRAMING ............................................................................................................................. 163
FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 164
FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK....................................... 166
FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 166
FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 166
FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC............................................ 166
FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT ............................................................... 167
FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 167
FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 168
FIGURE 3-12: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 169
FIGURE 3-13: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS
............................................................................................................................................. 171
FIGURE 3-14: CALCULATION OF LCRC ...................................................................................... 173
FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART...................................................... 180
FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART.......................................................... 181
FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 185
FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER.......................................... 191
FIGURE 4-2: CHARACTER TO SYMBOL MAPPING......................................................................... 192
FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 193
FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 193
FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 196
FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 197
FIGURE 4-7: FRAMED TLP ON A X1 LINK.................................................................................... 197
FIGURE 4-8: FRAMED TLP ON A X2 LINK.................................................................................... 198
FIGURE 4-9: FRAMED TLP ON A X4 LINK.................................................................................... 198
FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL............................................................... 200
FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A
BLOCK ................................................................................................................................. 201
FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 202
FIGURE 4-13: LAYOUT OF FRAMING TOKENS.............................................................................. 205
FIGURE 4-14: TLP AND DLLP LAYOUT...................................................................................... 207
FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 207
FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS............................. 208
FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK ............................................ 208
FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE .... 215
FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING...................... 217
FIGURE 4-20: EQUALIZATION FLOW............................................................................................ 223
FIGURE 4-21: ELECTRICAL IDLE EXIT ORDERED SET.................................................................. 234
FIGURE 4-22: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE ........ 249
FIGURE 4-23: DETECT SUBSTATE MACHINE ............................................................................... 251
FIGURE 4-24: POLLING SUBSTATE MACHINE .............................................................................. 259 
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
14
FIGURE 4-25: CONFIGURATION SUBSTATE MACHINE.................................................................. 275
FIGURE 4-26: RECOVERY SUBSTATE MACHINE........................................................................... 296
FIGURE 4-27: L0S SUBSTATE MACHINE ...................................................................................... 303
FIGURE 4-28: L1 SUBSTATE MACHINE........................................................................................ 305
FIGURE 4-29: L2 SUBSTATE MACHINE........................................................................................ 306
FIGURE 4-30: LOOPBACK SUBSTATE MACHINE........................................................................... 312
FIGURE 4-31: TRANSMITTER, CHANNEL, AND RECEIVER BOUNDARIES ...................................... 325
FIGURE 4-32: REQUIRED SETUP FOR CHARACTERIZING A 5.0 GT/S TRANSMITTER..................... 326
FIGURE 4-33: ALLOWABLE SETUP FOR CHARACTERIZING A 2.5 GT/S TRANSMITTER ................. 326
FIGURE 4-34: TX TEST BOARD EXAMPLE.................................................................................... 327
FIGURE 4-35: SINGLE-ENDED AND DIFFERENTIAL LEVELS.......................................................... 329
FIGURE 4-36: FULL SWING SIGNALING VOLTAGE PARAMETERS SHOWING -6 DB DE-EMPHASIS 330
FIGURE 4-37: REDUCED SWING TX PARAMETERS ....................................................................... 330
FIGURE 4-38: MINIMUM PULSE WIDTH DEFINITION ................................................................... 331
FIGURE 4-39: FULL SWING TX PARAMETERS SHOWING DE-EMPHASIS ....................................... 332
FIGURE 4-40: MEASURING FULL SWING/DE-EMPHASIZED VOLTAGES FROM EYE DIAGRAM...... 333
FIGURE 4-41: TX EQUALIZATION FIR REPRESENTATION ............................................................ 335
FIGURE 4-42: DEFINITION OF TX VOLTAGE LEVELS AND EQUALIZATION RATIOS ...................... 336
FIGURE 4-43: WAVEFORM MEASUREMENT POINTS FOR PRE-SHOOT AND DE-EMPHASIS ............ 337
FIGURE 4-44: VTX-FS-NO-EQ MEASUREMENT ................................................................................ 340
FIGURE 4-45: TXEQ COEFFICIENT SPACE TRIANGULAR MATRIX EXAMPLE............................... 341
FIGURE 4-46: MEASURING VTX-EIEOS-FS AND VTX-EIEOS-RS ........................................................... 342
FIGURE 4-47: COMPLIANCE PATTERN AND RESULTING PACKAGE LOSS TEST WAVEFORM ........ 343
FIGURE 4-48: TRANSMITTER MARGINING VOLTAGE LEVELS AND CODES .................................. 344
FIGURE 4-49: PLOT OF TRANSMITTER HPF FILTER FUNCTIONS .................................................. 346
FIGURE 4-50: ALGORITHM TO REMOVE DE-EMPHASIS INDUCED JITTER..................................... 347
FIGURE 4-51: EXAMPLE OF DE-EMPHASIS JITTER REMOVAL....................................................... 348
FIGURE 4-52: RELATION BETWEEN DATA EDGE PDFS AND RECOVERED DATA CLOCK............. 350
FIGURE 4-53: DERIVATION OF TTX-UTJ AND TTX-UDJDD ................................................................ 350
FIGURE 4-54: PWJ RELATIVE TO CONSECUTIVE EDGES 1 UI APART .......................................... 351
FIGURE 4-55: DEFINITION OF TTX-UPW-DJDD AND TTX-UPW-TJ ........................................................ 352
FIGURE 4-56: TX, RX DIFFERENTIAL RETURN LOSS MASK......................................................... 352
FIGURE 4-57: TX, RX COMMON MODE RETURN LOSS MASK...................................................... 353
FIGURE 4-58: CALIBRATION CHANNEL VALIDATION .................................................................. 360
FIGURE 4-59: CALIBRATION CHANNEL SHOWING TMIN-PULSE...................................................... 360
FIGURE 4-60: CALIBRATION CHANNEL |S11| PLOT WITH TOLERANCE LIMITS .............................. 361
FIGURE 4-61: SETUP FOR CALIBRATING RECEIVER TEST CIRCUIT INTO A REFERENCE LOAD ..... 362
FIGURE 4-62: SETUP FOR TESTING RECEIVER ............................................................................. 362
FIGURE 4-63: RECEIVER EYE MARGINS ...................................................................................... 365
FIGURE 4-64: SIGNAL AT RECEIVER REFERENCE LOAD SHOWING MIN/MAX SWING.................. 366
FIGURE 4-65: RX TESTBOARD TOPOLOGY................................................................................... 367
FIGURE 4-66: INSERTION LOSS GUIDELINES FOR CALIBRATION/BREAKOUT CHANNELS............. 368
FIGURE 4-67: BEHAVIORAL CDR MODEL FOR RX MEASUREMENT ............................................ 369
FIGURE 4-68: TRANSFER FUNCTION FOR BEHAVIORAL CTLE .................................................... 370
FIGURE 4-69: LOSS CURVES FOR BEHAVIORAL CTLE ................................................................ 370
FIGURE 4-70: EQUATION AND FLOW DIAGRAM FOR 1-TAP DFE ................................................. 371 
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
15
FIGURE 4-71: SETUP FOR CALIBRATING THE STRESSED VOLTAGE EYE ...................................... 372
FIGURE 4-72: LAYOUT FOR STRESSED VOLTAGE TESTING OF RECEIVER .................................... 374
FIGURE 4-73: LAYOUT FOR CALIBRATING THE STRESSED JITTER EYE ........................................ 375
FIGURE 4-74: SWEPT SJ MASK .................................................................................................... 376
FIGURE 4-75: LAYOUT FOR JITTER TESTING COMMON REFCLK RX ............................................ 377
FIGURE 4-76: LAYOUT FOR JITTER TESTING DATA CLOCKED REFCLK RX.................................. 377
FIGURE 4-77: EXIT FROM IDLE VOLTAGE AND TIME MARGINS................................................... 381
FIGURE 4-78: A 30 KHZ BEACON SIGNALING THROUGH A 75 NF CAPACITOR............................ 386
FIGURE 4-79: BEACON, WHICH INCLUDES A 2-NS PULSE THROUGH A 75 NF CAPACITOR........... 386
FIGURE 4-80: SIMULATION ENVIRONMENT FOR CHARACTERIZING CHANNEL............................. 389
FIGURE 4-81: EXTRACTING EYE MARGINS FROM CHANNEL SIMULATION RESULTS ................... 392
FIGURE 4-82: MULTI-SEGMENT CHANNEL EXAMPLE .................................................................. 393
FIGURE 4-83: FLOW DIAGRAM FOR CHANNEL TOLERANCING..................................................... 394
FIGURE 4-84: TX/RX BEHAVIORAL PACKAGE MODELS .............................................................. 395
FIGURE 4-85: BEHAVIORAL TX AND RX S-PARAMETER FILE DETAILS ....................................... 395
FIGURE 4-86: DERIVATION OF JITTER PARAMETERS IN TABLE 4-26............................................ 398
FIGURE 4-87: EH, EW MASK...................................................................................................... 398
FIGURE 4-88: REFCLK TEST SETUP ............................................................................................. 401
FIGURE 4-89: COMMON REFCLK RX ARCHITECTURE.................................................................. 402
FIGURE 4-90: REFCLK TRANSPORT DELAY PATHS FOR A COMMON REFCLK RX ARCHITECTURE 403
FIGURE 4-91: DATA CLOCKED RX ARCHITECTURE..................................................................... 405
FIGURE 4-92: SEPARATE REFCLK ARCHITECTURE ...................................................................... 407
FIGURE 4-93: 8.0 GT/S COMMON REFCLK RX ARCHITECTURE WITH ωN, ζ LIMITS ..................... 409
FIGURE 4-94: 8.0 GT/S DATA CLOCKED RX ARCHITECTURE WITH ωN, ζ LIMITS ........................ 411
FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM ............................................. 417
FIGURE 5-2: ENTRY INTO THE L1 LINK STATE ............................................................................ 425
FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT........................ 428
FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING. 431
FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE MACHINE.................................................. 435
FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED)................ 448
FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE ................................................................ 449
FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION ..................................................... 450
FIGURE 6-1: ERROR CLASSIFICATION.......................................................................................... 465
FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING
OPERATIONS ........................................................................................................................ 479
FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS .................................. 480
FIGURE 6-4: TC FILTERING EXAMPLE......................................................................................... 490
FIGURE 6-5: TC TO VC MAPPING EXAMPLE ............................................................................... 491
FIGURE 6-6: AN EXAMPLE OF TRAFFIC FLOW ILLUSTRATING INGRESS AND EGRESS.................. 492
FIGURE 6-7: AN EXAMPLE OF DIFFERENTIATED TRAFFIC FLOW THROUGH A SWITCH................ 493
FIGURE 6-8: SWITCH ARBITRATION STRUCTURE......................................................................... 494
FIGURE 6-9: VC ID AND PRIORITY ORDER – AN EXAMPLE......................................................... 495
FIGURE 6-10: MULTI-FUNCTION ARBITRATION MODEL.............................................................. 498
FIGURE 6-11: ROOT COMPLEX REPRESENTED AS A SINGLE COMPONENT ................................... 530
FIGURE 6-12: ROOT COMPLEX REPRESENTED AS MULTIPLE COMPONENTS ................................ 531
FIGURE 6-13: EXAMPLE SYSTEM TOPOLOGY WITH ARI DEVICES............................................... 544 
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
16
FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE ......................................... 546
FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES................................................... 564
FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 568
FIGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT.................................................. 569
FIGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS...................................................... 571
FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY
MESSAGES ........................................................................................................................... 572
FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 576
FIGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 576
FIGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT...................................................... 577
FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER............................................................ 588
FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER................................................................ 595
FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER................................................................ 597
FIGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER..................................................... 601
FIGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER.............................................. 602
FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES ..................................................... 603
FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE................................................................. 605
FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 605
FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 606
FIGURE 7-13: DEVICE CAPABILITIES REGISTER .......................................................................... 608
FIGURE 7-14: DEVICE CONTROL REGISTER................................................................................. 613
FIGURE 7-15: DEVICE STATUS REGISTER.................................................................................... 620
FIGURE 7-16: LINK CAPABILITIES REGISTER............................................................................... 622
FIGURE 7-17: LINK CONTROL REGISTER..................................................................................... 627
FIGURE 7-18: LINK STATUS REGISTER........................................................................................ 635
FIGURE 7-19: SLOT CAPABILITIES REGISTER .............................................................................. 638
FIGURE 7-20: SLOT CONTROL REGISTER..................................................................................... 640
FIGURE 7-21: SLOT STATUS REGISTER ....................................................................................... 644
FIGURE 7-22: ROOT CONTROL REGISTER.................................................................................... 646
FIGURE 7-23: ROOT CAPABILITIES REGISTER.............................................................................. 647
FIGURE 7-24: ROOT STATUS REGISTER....................................................................................... 648
FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER........................................................................ 649
FIGURE 7-26: DEVICE CONTROL 2 REGISTER.............................................................................. 654
FIGURE 7-27: LINK CAPABILITIES 2 REGISTER............................................................................ 658
FIGURE 7-28: LINK CONTROL 2 REGISTER .................................................................................. 660
FIGURE 7-29: LINK STATUS 2 REGISTER ..................................................................................... 665
FIGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT.................................. 668
FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER .................................................... 669
FIGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE
............................................................................................................................................. 671
FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER........................ 672
FIGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER........................................................ 673
FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER........................................................... 675
FIGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER..................................................... 677
FIGURE 7-37: CORRECTABLE ERROR STATUS REGISTER............................................................. 679
FIGURE 7-38: CORRECTABLE ERROR MASK REGISTER ............................................................... 680 
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
17
FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 681
FIGURE 7-40: HEADER LOG REGISTER ........................................................................................ 683
FIGURE 7-41: ROOT ERROR COMMAND REGISTER ...................................................................... 683
FIGURE 7-42: ROOT ERROR STATUS REGISTER ........................................................................... 685
FIGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 687
FIGURE 7-44: TLP PREFIX LOG REGISTER .................................................................................. 688
FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 689
FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 690
FIGURE 7-47: PORT VC CAPABILITY REGISTER 1 ....................................................................... 691
FIGURE 7-48: PORT VC CAPABILITY REGISTER 2 ....................................................................... 692
FIGURE 7-49: PORT VC CONTROL REGISTER .............................................................................. 693
FIGURE 7-50: PORT VC STATUS REGISTER ................................................................................. 694
FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER.................................................................. 695
FIGURE 7-52: VC RESOURCE CONTROL REGISTER...................................................................... 697
FIGURE 7-53: VC RESOURCE STATUS REGISTER......................................................................... 699
FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES........................................... 701
FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES
............................................................................................................................................. 702
FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE......................... 703
FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER.................................. 704
FIGURE 7-58: SERIAL NUMBER REGISTER................................................................................... 705
FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 706
FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER............... 707
FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 708
FIGURE 7-62: LINK ENTRY.......................................................................................................... 709
FIGURE 7-63: LINK DESCRIPTION REGISTER ............................................................................... 709
FIGURE 7-64: LINK ADDRESS FOR LINK TYPE 0 .......................................................................... 711
FIGURE 7-65: LINK ADDRESS FOR LINK TYPE 1 .......................................................................... 712
FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY...................................... 713
FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER...................... 713
FIGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 714
FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 717
FIGURE 7-70: ROOT COMPLEX LINK STATUS REGISTER.............................................................. 719
FIGURE 7-71: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE................................. 720
FIGURE 7-72: POWER BUDGETING EXTENDED CAPABILITY HEADER.......................................... 721
FIGURE 7-73: POWER BUDGETING DATA REGISTER.................................................................... 722
FIGURE 7-74: POWER BUDGET CAPABILITY REGISTER ............................................................... 724
FIGURE 7-75: ACS EXTENDED CAPABILITY................................................................................ 725
FIGURE 7-76: ACS EXTENDED CAPABILITY HEADER ................................................................. 725
FIGURE 7-77: ACS CAPABILITY REGISTER ................................................................................. 726
FIGURE 7-78: ACS CONTROL REGISTER ..................................................................................... 727
FIGURE 7-79: EGRESS CONTROL VECTOR REGISTER................................................................... 730
FIGURE 7-80: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY......... 731
FIGURE 7-81: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION EXTENDED
CAPABILITY HEADER........................................................................................................... 731
FIGURE 7-82: PCI EXPRESS MFVC CAPABILITY STRUCTURE..................................................... 733 
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
18
FIGURE 7-83: MFVC EXTENDED CAPABILITY HEADER.............................................................. 733
FIGURE 7-84: PORT VC CAPABILITY REGISTER 1 ....................................................................... 734
FIGURE 7-85: PORT VC CAPABILITY REGISTER 2 ....................................................................... 736
FIGURE 7-86: PORT VC CONTROL REGISTER .............................................................................. 737
FIGURE 7-87: PORT VC STATUS REGISTER ................................................................................. 738
FIGURE 7-88: VC RESOURCE CAPABILITY REGISTER.................................................................. 738
FIGURE 7-89: VC RESOURCE CONTROL REGISTER...................................................................... 740
FIGURE 7-90: VC RESOURCE STATUS REGISTER......................................................................... 742
FIGURE 7-91: PCI EXPRESS VSEC STRUCTURE .......................................................................... 746
FIGURE 7-92: VENDOR-SPECIFIC EXTENDED CAPABILITY HEADER ............................................ 746
FIGURE 7-93: VENDOR-SPECIFIC HEADER .................................................................................. 747
FIGURE 7-94: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE........................................... 748
FIGURE 7-95: RCRB HEADER EXTENDED CAPABILITY HEADER ................................................ 748
FIGURE 7-96: VENDOR ID AND DEVICE ID ................................................................................. 749
FIGURE 7-97: RCRB CAPABILITIES ............................................................................................ 750
FIGURE 7-98: RCRB CONTROL................................................................................................... 750
FIGURE 7-99: MULTICAST EXTENDED CAPABILITY STRUCTURE................................................. 751
FIGURE 7-100: MULTICAST EXTENDED CAPABILITY HEADER .................................................... 751
FIGURE 7-101: MULTICAST CAPABILITY REGISTER .................................................................... 752
FIGURE 7-102: MULTICAST CONTROL REGISTER ........................................................................ 753
FIGURE 7-103: MC_BASE_ADDRESS REGISTER ......................................................................... 754
FIGURE 7-104: MC_RECEIVE REGISTER ..................................................................................... 754
FIGURE 7-105: MC_BLOCK_ALL REGISTER ............................................................................... 755
FIGURE 7-106: MC_BLOCK_UNTRANSLATED REGISTER............................................................ 756
FIGURE 7-107: MC_OVERLAY_BAR.......................................................................................... 757
FIGURE 7-108: RESIZABLE BAR CAPABILITY ............................................................................. 759
FIGURE 7-109: RESIZABLE BAR EXTENDED CAPABILITY HEADER............................................. 759
FIGURE 7-110: RESIZABLE BAR CAPABILITY REGISTER............................................................. 760
FIGURE 7-111: RESIZABLE BAR CONTROL REGISTER ................................................................ 761
FIGURE 7-112: ARI CAPABILITY................................................................................................. 762
FIGURE 7-113: ARI CAPABILITY HEADER .................................................................................. 763
FIGURE 7-114: ARI CAPABILITY REGISTER ................................................................................ 763
FIGURE 7-115: ARI CONTROL REGISTER .................................................................................... 764
FIGURE 7-116: DYNAMIC POWER ALLOCATION CAPABILITY STRUCTURE .................................. 765
FIGURE 7-117: DPA EXTENDED CAPABILITY HEADER ............................................................... 765
FIGURE 7-118: DPA CAPABILITY REGISTER ............................................................................... 766
FIGURE 7-119: DPA LATENCY INDICATOR REGISTER................................................................. 767
FIGURE 7-120: DPA STATUS REGISTER ...................................................................................... 767
FIGURE 7-121: DPA CONTROL REGISTER................................................................................... 768
FIGURE 7-122: DPA POWER ALLOCATION ARRAY ..................................................................... 768
FIGURE 7-123: LTR EXTENDED CAPABILITY STRUCTURE .......................................................... 769
FIGURE 7-124: LTR EXTENDED CAPABILITY HEADER................................................................ 769
FIGURE 7-125: MAX SNOOP LATENCY REGISTER ....................................................................... 770
FIGURE 7-126: MAX NO-SNOOP LATENCY REGISTER................................................................. 770
FIGURE 7-127: TPH EXTENDED CAPABILITY STRUCTURE .......................................................... 771
FIGURE 7-128: TPH REQUESTER EXTENDED CAPABILITY HEADER............................................ 772 
PCI EXPRESS BASE SPECIFICATION, REV. 3.0
19
FIGURE 7-129: TPH REQUESTER CAPABILITY REGISTER............................................................ 772
FIGURE 7-130: TPH REQUESTER CONTROL REGISTER................................................................ 774
FIGURE 7-131: TPH ST TABLE ................................................................................................... 775
FIGURE 7-132: SECONDARY PCI EXPRESS EXTENDED CAPABILITY STRUCTURE ........................ 776
FIGURE 7-133: SECONDARY PCI EXPRESS EXTENDED CAPABILITY HEADER.............................. 776
FIGURE 7-134: LINK CONTROL 3 REGISTER ................................................................................ 777
FIGURE 7-135: LANE ERROR STATUS REGISTER ......................................................................... 778
FIGURE 7-136: LANE EQUALIZATION CONTROL REGISTER ......................................................... 778
FIGURE 7-137: LANE ((MAXIMUM LINK WIDTH – 1):0) EQUALIZATION CONTROL REGISTER .... 779
FIGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER
COMMUNICATION MODELS.................................................................................................. 784
FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND
CONGESTION........................................................................................................................ 785
FIGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS
............................................................................................................................................. 790
FIGURE C-1: SCRAMBLING SPECTRUM AT 2.5 GT/S FOR DATA VALUE OF 0 ............................... 810
FIGURE E-1: REFERENCE TOPOLOGY FOR IDO USE .................................................................... 819
FIGURE G-1: DEVICE AND PROCESSOR CONNECTED USING A PMUX LINK................................ 827
FIGURE G-2: PMUX LINK .......................................................................................................... 828
FIGURE G-3: PMUX PACKET FLOW THROUGH THE LAYERS ...................................................... 829
FIGURE G-4: PMUX PACKET...................................................................................................... 836
FIGURE G-5: TLP AND PMUX PACKET FRAMING (8B10B ENCODING)....................................... 837
FIGURE G-6: TLP AND PMUX PACKET FRAMING (128B/130B ENCODING)................................ 839
FIGURE G-7: PMUX EXTENDED CAPABILITY ............................................................................. 843
FIGURE G-8: PMUX EXTENDED CAPABILITY HEADER............................................................... 843
FIGURE G-9: PMUX CAPABILITY REGISTER............................................................................... 844
FIGURE G-10: PMUX CONTROL REGISTER................................................................................. 846
FIGURE G-11: PMUX STATUS REGISTER.................................................................................... 847
FIGURE G-12: PMUX PROTOCOL ARRAY ENTRY ....................................................................... 850