实时视频流缩放Verilog代码

【实例简介】

允许接入多种分辨率格式，实现输入源图像的放大、跨屏显示的功能

【实例截图】

【核心代码】

`timescale 1ns/100ps

`define READ        4'b0001
`define WRITE       4'b0010

module ddr2_ctrl(
input mclk, 
input rst_n, 

// VID_WR_CMD_FIFO INTERFACE
input vid_rx_cmd_fifo_empty_0,
output reg vid_rx_cmd_fifo_rden_0, 
input [26:0] vid_rx_cmd_fifo_rddata_0,
  
input vid_rx_cmd_fifo_empty_1, 
output reg vid_rx_cmd_fifo_rden_1,
input [26:0] vid_rx_cmd_fifo_rddata_1, 

input vid_rx_cmd_fifo_empty_2,
output reg vid_rx_cmd_fifo_rden_2,
input [26:0] vid_rx_cmd_fifo_rddata_2,
 
input vid_rx_cmd_fifo_empty_3,
output reg vid_rx_cmd_fifo_rden_3,
input [26:0] vid_rx_cmd_fifo_rddata_3,

input vid_rx_cmd_fifo_empty_4,
output reg vid_rx_cmd_fifo_rden_4,
input [26:0] vid_rx_cmd_fifo_rddata_4,

input vid_rx_cmd_fifo_empty_5,
output reg vid_rx_cmd_fifo_rden_5,
input [26:0] vid_rx_cmd_fifo_rddata_5,

// VID_RX_RAM INTERFACE 
input [127:0] vid_rx_ram_rddata_0,
input [127:0] vid_rx_ram_rddata_1,
input [127:0] vid_rx_ram_rddata_2,
input [127:0] vid_rx_ram_rddata_3,
input [127:0] vid_rx_ram_rddata_4,
input [127:0] vid_rx_ram_rddata_5,

output reg [8:0] vid_rx_ram_rdaddr,
 
// VID_RD_CMD_FIFO INTERFACE
input ddr_rd_cmd_fifo_empty,
output reg ddr_rd_cmd_fifo_rden,
input [22:0] ddr_rd_cmd_fifo_rddata,
 
// VID_TX_RAM INTERFACE
output reg [127:0] ram_wrdata,
output reg [8:0] ram_wraddr,

output reg [127:0] ram_wrdata_tmp,
output reg [8:0] ram_wraddr_tmp,

output reg ram_wren_0_0,
output reg ram_wren_0_1,
output reg ram_wren_1_0,
output reg ram_wren_1_1,
output reg ram_wren_2_0,
output reg ram_wren_2_1,
output reg ram_wren_3_0,
output reg ram_wren_3_1,
output reg ram_wren_4_0,
output reg ram_wren_4_1,
output reg ram_wren_5_0,
output reg ram_wren_5_1,

output reg ram_wren_6_0_tmp,
output reg ram_wren_6_1_tmp,
output reg ram_wren_7_0_tmp,
output reg ram_wren_7_1_tmp,
output reg ram_wren_8_0_tmp,
output reg ram_wren_8_1_tmp,
output reg ram_wren_9_0_tmp,
output reg ram_wren_9_1_tmp,
output reg ram_wren_10_0_tmp,
output reg ram_wren_10_1_tmp,
output reg ram_wren_11_0_tmp,
output reg ram_wren_11_1_tmp,

// DDR CORE INTERFACE
output reg [3:0]   cmd,
output reg [24:0] addr,
output reg cmd_valid,
output reg init_start,
output reg [4:0] burst_count,
output reg [127:0] write_data,
     
input cmd_rdy,
input init_done,
input data_rdy,
input read_data_valid,
input [127:0] read_data
);


parameter DELAY_DDR = 20'd40000;

parameter INIT_DELAY = 4'h0,
DDR2_INIT = 4'h1,
DDR2_IDLE = 4'h2,

DDR2_WR_CMD = 4'h3,
DDR2_WR_WAIT = 4'h4,
DDR2_WR_DATA = 4'h5,
DDR2_WR_END = 4'H6,
DDR2_WR_DELAY = 4'H7,

DDR2_RD_CMD = 4'h8,
DDR2_RD_WAIT = 4'h9,
DDR2_RD_DATA = 4'hA,
DDR2_RD_END = 4'hB,
DDR2_RD_DELAY = 4'hC;

// VID_RX_RAM CTRL
parameter CMD_IDLE = 4'd0,
RX_CH_SEL_0 = 4'd1,
RX_CH_SEL_1 = 4'd2,
RX_CH_SEL_2 = 4'd3,
RX_CH_SEL_3 = 4'd4,
RX_CH_SEL_4 = 4'd5,
RX_CH_SEL_5 = 4'd6,

GET_WR_CMD = 4'd9,
WR_CMD_WAIT = 4'd10,
WR_CMD_SEND = 4'd11,
GET_RD_CMD_RDEN = 4'd12,
GET_RD_CMD = 4'd13,
RD_CMD_SEND = 4'd14;


reg ram_wren_6_0;
reg ram_wren_6_1;
reg ram_wren_7_0;
reg ram_wren_7_1;
reg ram_wren_8_0;
reg ram_wren_8_1;
reg ram_wren_9_0;
reg ram_wren_9_1;
reg ram_wren_10_0;
reg ram_wren_10_1;
reg ram_wren_11_0;
reg ram_wren_11_1;

// REG & WIRE
reg [19:0] cnt_init_delay;
reg [3:0] curr_st_ddr;
reg data_rdy_ff1;
reg data_rdy_ff2;
reg [4:0] cnt_ddr_wr_wait;
reg [127:0] write_data_pre;
reg ddr_rden;
reg ddr_wren;
reg get_pre_flag;
reg [3:0] wr_channel;
reg [1:0] wr_block;
reg [10:0] wr_ln;
reg [8:0] wr_col_addr;
reg [1:0] wr_times;
reg [1:0] wr_block_0;
reg [1:0] wr_block_1;
reg [1:0] wr_block_2;
reg [1:0] wr_block_3;
reg [1:0] wr_block_4;
reg [1:0] wr_block_5;
reg [8:0] rd_col_addr;
reg rd_block_chg;
reg [1:0] rd_block;
reg [10:0] rd_ln;
reg [4:0] rd_burst_cnt;
reg [1:0] rd_times;
reg [3:0] rd_channel;
reg [1:0] rd_block_0;
reg [1:0] rd_block_1;
reg [1:0] rd_block_2;
reg [1:0] rd_block_3;
reg [1:0] rd_block_4;
reg [1:0] rd_block_5;
reg [1:0] wr_times_next;
reg [1:0] rd_times_next;
reg [2:0] cnt_wr_times;
reg [2:0] cnt_rd_times;
reg read_data_valid_ff1;
reg [127:0] read_data_ff1;
reg [3:0] cmd_rdy_shift;
reg cmd_rdy_flag;
reg [7:0] ram_wraddr_ff1;
reg [3:0] vi_tx_ch;
reg [3:0] curr_st_cmd;
reg [3:0] cnt_get_wr_cmd;
reg [3:0] rx_ch_sel;
reg [3:0] rx_ram_sel;
reg [26:0] vid_rx_cmd_fifo_rddata;
reg [8:0] ram_rd_staddr;
reg [8:0] ram_rd_staddr_next;

reg [3:0] cnt_get_rd_cmd;
reg [1:0] tx_ram_sel_lsb;
reg rdaddr_add_flag; // OPT TIMING


/*******DDR2 MAIN STATE MATCHION****/
always @(posedge mclk or negedge rst_n)
begin
if(!rst_n)
curr_st_ddr <= INIT_DELAY;
else
begin
case(curr_st_ddr)
INIT_DELAY:
if(cnt_init_delay == DELAY_DDR)
curr_st_ddr <= DDR2_INIT;
else ;

DDR2_INIT:
begin
if(cmd_rdy)
curr_st_ddr <= DDR2_IDLE;
end

DDR2_IDLE:
if((!cmd_valid) && ddr_rden) 
curr_st_ddr <= DDR2_RD_CMD;
else if((!cmd_valid) && ddr_wren)
curr_st_ddr <= DDR2_WR_CMD;
else ;

DDR2_WR_CMD:
if(cmd_valid && cmd_rdy)
curr_st_ddr <= DDR2_WR_WAIT;
else ;

DDR2_WR_WAIT:
if(data_rdy)
curr_st_ddr <= DDR2_WR_DATA;
else ;

DDR2_WR_DATA:
if(!data_rdy)
curr_st_ddr <= DDR2_WR_END ;
else ;

DDR2_WR_END: curr_st_ddr <= DDR2_WR_DELAY;
DDR2_WR_DELAY: curr_st_ddr <= DDR2_IDLE;

DDR2_RD_CMD:
if(cmd_valid && cmd_rdy)
curr_st_ddr <= DDR2_RD_WAIT;
else ;

DDR2_RD_WAIT:
if(read_data_valid)
curr_st_ddr <= DDR2_RD_DATA;
else ;

DDR2_RD_DATA:
if(!read_data_valid )
begin
if(cnt_rd_times == rd_times)
curr_st_ddr <= DDR2_RD_END ;
else
curr_st_ddr <= DDR2_RD_CMD ;
end
else ;

DDR2_RD_END:curr_st_ddr <= DDR2_RD_DELAY;
DDR2_RD_DELAY:curr_st_ddr <= DDR2_IDLE;

default:
curr_st_ddr <= DDR2_IDLE;
endcase
end
end

/**********DDR2 init***********/
always @(posedge mclk or negedge rst_n)
begin
if(!rst_n)
cnt_init_delay <= 0;
else if(curr_st_ddr == INIT_DELAY)
cnt_init_delay <= cnt_init_delay 1'b1;
else
cnt_init_delay <= 0;
end

/**************DDR2 INIT********************/
always @(posedge mclk or negedge rst_n) 
begin
if(!rst_n)
init_start <= 0;
else if((!init_done) && (curr_st_ddr == DDR2_INIT))
init_start <= 1;
else
init_start <= 0;
end

// cmd_rdy_shift
always @(posedge mclk or negedge rst_n) 
begin
if(!rst_n)
cmd_rdy_shift <= 4'd0;
else 
cmd_rdy_shift <= {cmd_rdy_shift[2:0],cmd_rdy};
end

// cmd_rdy_flag
always @(posedge mclk or negedge rst_n) 
begin
if(!rst_n)
cmd_rdy_flag <= 0;
else if(cmd_rdy_shift == 4'b1010)
cmd_rdy_flag <= 1;
else
cmd_rdy_flag <= 0;
end

// cnt_ddr_wr_wait
always @(posedge mclk) 
begin
if(curr_st_ddr == DDR2_WR_WAIT)
cnt_ddr_wr_wait <= cnt_ddr_wr_wait 1;
else
cnt_ddr_wr_wait <= 0;
end

always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
curr_st_cmd <= CMD_IDLE;
else 
case(curr_st_cmd)
CMD_IDLE:
begin
if(vid_rx_cmd_fifo_empty_0 != 1)
curr_st_cmd <= RX_CH_SEL_0;

else if(vid_rx_cmd_fifo_empty_1 != 1)
curr_st_cmd <= RX_CH_SEL_1;
else if(vid_rx_cmd_fifo_empty_2 != 1)
curr_st_cmd <= RX_CH_SEL_2;
else if(vid_rx_cmd_fifo_empty_3 != 1)
curr_st_cmd <= RX_CH_SEL_3;
else if(vid_rx_cmd_fifo_empty_4 != 1)
curr_st_cmd <= RX_CH_SEL_4;
else if(vid_rx_cmd_fifo_empty_5 != 1)
curr_st_cmd <= RX_CH_SEL_5;

else if(ddr_rd_cmd_fifo_empty != 1)
curr_st_cmd <= GET_RD_CMD_RDEN;
else
;
end

RX_CH_SEL_0:curr_st_cmd <= GET_WR_CMD;
RX_CH_SEL_1:curr_st_cmd <= GET_WR_CMD;
RX_CH_SEL_2:curr_st_cmd <= GET_WR_CMD;
RX_CH_SEL_3:curr_st_cmd <= GET_WR_CMD;
RX_CH_SEL_4:curr_st_cmd <= GET_WR_CMD;
RX_CH_SEL_5:curr_st_cmd <= GET_WR_CMD;

GET_WR_CMD:
if(cnt_get_wr_cmd == 4)
curr_st_cmd <= WR_CMD_WAIT;
else ;

WR_CMD_WAIT:
if((curr_st_ddr != DDR2_WR_DATA) && (curr_st_ddr != DDR2_WR_WAIT))
curr_st_cmd <= WR_CMD_SEND;
else ;

WR_CMD_SEND:
if(cnt_wr_times == wr_times)
curr_st_cmd <= CMD_IDLE;
else ;

GET_RD_CMD_RDEN:
curr_st_cmd <= GET_RD_CMD;

GET_RD_CMD:
if(cnt_get_rd_cmd == 3)//(cnt_get_rd_cmd == 2)
curr_st_cmd <= RD_CMD_SEND;
else ;

RD_CMD_SEND:
if(curr_st_ddr == DDR2_RD_END)
curr_st_cmd <= CMD_IDLE;
else ;
endcase
end 

// rx_ch_sel
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rx_ch_sel <= 4'h0;
else 
case(curr_st_cmd)
RX_CH_SEL_0:rx_ch_sel <= 4'h0;
RX_CH_SEL_1:rx_ch_sel <= 4'h1;
RX_CH_SEL_2:rx_ch_sel <= 4'h2;
RX_CH_SEL_3:rx_ch_sel <= 4'h3;
RX_CH_SEL_4:rx_ch_sel <= 4'h4;
RX_CH_SEL_5:rx_ch_sel <= 4'h5;
default:rx_ch_sel <= rx_ch_sel;
endcase
end

// vid_rx_cmd_fifo_rden_0
always@(posedge mclk)
begin
if(curr_st_cmd == RX_CH_SEL_0)
vid_rx_cmd_fifo_rden_0 <= 1;
else
vid_rx_cmd_fifo_rden_0 <= 0;
end

// vid_rx_cmd_fifo_rden_1
always@(posedge mclk)
begin
if(curr_st_cmd == RX_CH_SEL_1)
vid_rx_cmd_fifo_rden_1 <= 1;
else
vid_rx_cmd_fifo_rden_1 <= 0;
end
// vid_rx_cmd_fifo_rden_2
always@(posedge mclk)
begin
if(curr_st_cmd == RX_CH_SEL_2)
vid_rx_cmd_fifo_rden_2 <= 1;
else
vid_rx_cmd_fifo_rden_2 <= 0;
end

// vid_rx_cmd_fifo_rden_3
always@(posedge mclk)
begin
if(curr_st_cmd == RX_CH_SEL_3)
vid_rx_cmd_fifo_rden_3 <= 1;
else
vid_rx_cmd_fifo_rden_3 <= 0;
end

// vid_rx_cmd_fifo_rden_4
always@(posedge mclk)
begin
if(curr_st_cmd == RX_CH_SEL_4)
vid_rx_cmd_fifo_rden_4 <= 1;
else
vid_rx_cmd_fifo_rden_4 <= 0;
end

// vid_rx_cmd_fifo_rden_5
always@(posedge mclk)
begin
if(curr_st_cmd == RX_CH_SEL_5)
vid_rx_cmd_fifo_rden_5 <= 1;
else
vid_rx_cmd_fifo_rden_5 <= 0;
end

// rx_cmd_fifo_rddata
always@(posedge mclk)
begin
case(rx_ch_sel)
4'd0: vid_rx_cmd_fifo_rddata <= vid_rx_cmd_fifo_rddata_0;
4'd1: vid_rx_cmd_fifo_rddata <= vid_rx_cmd_fifo_rddata_1;
4'd2: vid_rx_cmd_fifo_rddata <= vid_rx_cmd_fifo_rddata_2;
4'd3: vid_rx_cmd_fifo_rddata <= vid_rx_cmd_fifo_rddata_3;
4'd4: vid_rx_cmd_fifo_rddata <= vid_rx_cmd_fifo_rddata_4;
4'd5: vid_rx_cmd_fifo_rddata <= vid_rx_cmd_fifo_rddata_5;
default: vid_rx_cmd_fifo_rddata <= 9'h0;
endcase
end

// cnt_get_wr_cmd
always@(posedge mclk)
begin
if(curr_st_cmd == GET_WR_CMD)
cnt_get_wr_cmd <= cnt_get_wr_cmd 1;
else
cnt_get_wr_cmd <= 0;
end

// wr related signal
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
begin
ram_rd_staddr_next <= 0;
wr_times_next <= 0;
wr_block <= 0;
wr_ln <= 0;
wr_channel <= 0;
end
else if(cnt_get_wr_cmd == 4)
begin
ram_rd_staddr_next <= vid_rx_cmd_fifo_rddata[26:18];
wr_times_next <= vid_rx_cmd_fifo_rddata[17:16];
wr_block <=  vid_rx_cmd_fifo_rddata[15:14];
wr_ln <= vid_rx_cmd_fifo_rddata[13:3];
wr_channel <= vid_rx_cmd_fifo_rddata[2:0];
end
else ;
end
// wr_block_0
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
wr_block_0 <= 2'h0;
else if(curr_st_cmd == WR_CMD_WAIT && rx_ch_sel == 0)
wr_block_0 <= wr_block;
else ;
end

// wr_block_1
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
wr_block_1 <= 2'h0;
else if(curr_st_cmd == WR_CMD_WAIT && rx_ch_sel == 1)
wr_block_1 <= wr_block;
else ;
end

// wr_block_2
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
wr_block_2 <= 2'h0;
else if(curr_st_cmd == WR_CMD_WAIT && rx_ch_sel == 2)
wr_block_2 <= wr_block;
else ;
end

// wr_block_3
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
wr_block_3 <= 2'h0;
else if(curr_st_cmd == WR_CMD_WAIT && rx_ch_sel == 3)
wr_block_3 <= wr_block;
else ;
end

// wr_block_4
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
wr_block_4 <= 2'h0;
else if(curr_st_cmd == WR_CMD_WAIT && rx_ch_sel == 4)
wr_block_4 <= wr_block;
else ;
end

// wr_block_5
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
wr_block_5 <= 2'h0;
else if(curr_st_cmd == WR_CMD_WAIT && rx_ch_sel == 5)
wr_block_5 <= wr_block;
else ;
end

// wr_times
always@(posedge mclk or negedge rst_n)
begin 
if(!rst_n)
wr_times <= 2;
else if(curr_st_cmd == WR_CMD_SEND && wr_times_next != 0)
wr_times <= wr_times_next;
else ;
end

// ddr_rd_cmd_fifo_rden
always@(posedge mclk)
begin
if(curr_st_cmd == GET_RD_CMD_RDEN)
ddr_rd_cmd_fifo_rden <= 1;
else
ddr_rd_cmd_fifo_rden <= 0;
end

// cnt_get_rd_cmd
always@(posedge mclk)
begin
if(curr_st_cmd == GET_RD_CMD)
cnt_get_rd_cmd <= cnt_get_rd_cmd 1;
else
cnt_get_rd_cmd <= 0;
end

// rd_ln & rd_channel
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
begin
vi_tx_ch <= 4'h0;
rd_channel <= 3'h0;
rd_ln <= 11'h0;
tx_ram_sel_lsb <= 2'b00;
rd_block_chg <= 1'b0;
end
else if(cnt_get_rd_cmd == 2)//(cnt_get_rd_cmd == 1)
begin
vi_tx_ch <= ddr_rd_cmd_fifo_rddata[21:18];
rd_channel <= ddr_rd_cmd_fifo_rddata[17:15];
rd_ln <= ddr_rd_cmd_fifo_rddata[10:0];
tx_ram_sel_lsb <= ddr_rd_cmd_fifo_rddata[14:13];
rd_block_chg <= ddr_rd_cmd_fifo_rddata[22];
end
else ;
end

// rd_times & rd_burst_cnt
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
begin
rd_times <= 3'h0;
rd_burst_cnt <= 5'h0;
end
else if(cnt_get_rd_cmd == 2)// 1080P: NO 420
begin
rd_times <= 3'h2;
rd_burst_cnt <= 5'd30;
end
else ;
end


// rd_block_0
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rd_block_0 <= 2'b00;
else if(cnt_get_rd_cmd == 3 && rd_block_chg == 1 && rd_channel == 4'h0)
rd_block_0 <= wr_block_0 - 1;
else ;
end

// rd_block_1
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rd_block_1 <= 2'b00;
else if(cnt_get_rd_cmd == 3 && rd_block_chg == 1 && rd_channel == 4'h1)
rd_block_1 <= wr_block_1 - 1;
else ;
end

// rd_block_2
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rd_block_2 <= 2'b00;
else if(cnt_get_rd_cmd == 3 && rd_block_chg == 1 && rd_channel == 4'h2)
rd_block_2 <= wr_block_2 - 1;
else ;
end

// rd_block_3
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rd_block_3 <= 2'b00;
else if(cnt_get_rd_cmd == 3 &&  rd_block_chg == 1 && rd_channel == 4'h3)
rd_block_3 <= wr_block_3 - 1;
else ;
end

// rd_block_4
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rd_block_4 <= 2'b00;
else if(cnt_get_rd_cmd == 3 && rd_block_chg == 1 && rd_channel == 4'h4)
rd_block_4 <= wr_block_4 - 1;
else ;
end

// rd_block_5 
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rd_block_5 <= 2'b00;
else if(cnt_get_rd_cmd == 3 && rd_block_chg == 1 && rd_channel == 4'h5)
rd_block_5 <= wr_block_5 - 1;
else ;
end

// rd_block
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rd_block <= 2'b00;
else if(curr_st_cmd == RD_CMD_SEND)
begin
case(rd_channel) 
3'd0: rd_block <= rd_block_0;
3'd1: rd_block <= rd_block_1;
3'd2: rd_block <= rd_block_2;
3'd3: rd_block <= rd_block_3;
3'd4: rd_block <= rd_block_4;
3'd5: rd_block <= rd_block_5;
default: rd_block <= rd_block_0;
endcase
end
else ;
end

// ddr_wren
always@(posedge mclk)begin
if(curr_st_cmd == WR_CMD_SEND)
ddr_wren <= 1;
else
ddr_wren <= 0;
end
// ddr_rden
always@(posedge mclk)begin
if(curr_st_cmd == RD_CMD_SEND)
ddr_rden <= 1;
else
ddr_rden <= 0;
end


// addr & cmd & burst_count 
always@(posedge mclk or negedge rst_n)
begin 
if(!rst_n)
begin
addr <= 25'h0;
cmd <= 4'h0;
burst_count <= 0;
end
else if(curr_st_cmd == WR_CMD_SEND)
begin
addr <= {wr_ln[10:0],wr_block[1:0],wr_channel[2:0],wr_col_addr[8:0]};
cmd  <= `WRITE;
burst_count <= 5'd30;
end
else if(curr_st_cmd == RD_CMD_SEND)
begin
addr <= {rd_ln[10:0],rd_block[1:0],rd_channel[2:0],rd_col_addr[8:0]};
cmd  <= `READ;
burst_count <= 5'd30;
end
else
begin
addr <= 25'h0;
cmd <= 4'h0;
burst_count <= 0;
end
end

// rx_ram_sel
always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
rx_ram_sel <= 4'd0;
else if(curr_st_cmd == WR_CMD_SEND)
rx_ram_sel <= rx_ch_sel;
else ;
end

// ram_rd_staddr
always@(posedge mclk or negedge rst_n)
begin 
if(!rst_n)
ram_rd_staddr <= 0;
else if(curr_st_cmd == WR_CMD_SEND)
ram_rd_staddr <= ram_rd_staddr_next;
else ;
end

// vid_rx_ram_rdaddr
always@(posedge mclk)
begin
if(cnt_ddr_wr_wait == 5)
rdaddr_add_flag <= 1;
else
rdaddr_add_flag <= 0;
end

always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
vid_rx_ram_rdaddr <= 9'h0;
else if(data_rdy | rdaddr_add_flag)
vid_rx_ram_rdaddr <= vid_rx_ram_rdaddr 1;
else if(curr_st_ddr == DDR2_IDLE)
vid_rx_ram_rdaddr <= ram_rd_staddr;
else ;
end

// data_rdy
always@(posedge mclk) data_rdy_ff1 <= data_rdy;
always@(posedge mclk) data_rdy_ff2 <= data_rdy_ff1;

// write_data

always@(posedge mclk)
begin
if(cnt_ddr_wr_wait == 3)
get_pre_flag <= 1;
else
get_pre_flag <= 0;
end

always@(posedge mclk or negedge rst_n)
begin
if(!rst_n)
write_data_pre <= 0;
else if(get_pre_flag)
write_data_pre <= write_data;
else ;
end

always@(posedge mclk)
begin
if(data_rdy_ff2 == 0 && data_rdy == 1) // FIRST WRITEDATA
write_data <= write_data_pre;
else
case(rx_ram_sel)
4'd0: write_data <= vid_rx_ram_rddata_0;
4'd1: write_data <= vid_rx_ram_rddata_1;
4'd2: write_data <= vid_rx_ram_rddata_2;
4'd3: write_data <= vid_rx_ram_rddata_3;
4'd4: write_data <= vid_rx_ram_rddata_4;
4'd5: write_data <= vid_rx_ram_rddata_5;
default: write_data <= vid_rx_ram_rddata_0;
endcase
end

// cmd_valid
always @(posedge mclk) 
begin
if((curr_st_ddr == DDR2_WR_CMD || curr_st_ddr == DDR2_RD_CMD) && cmd_rdy_flag)
cmd_valid <= 1;
else if(curr_st_ddr == DDR2_WR_DATA && cmd_rdy_flag && cnt_wr_times < wr_times)
cmd_valid <= 1;
else if(curr_st_ddr == DDR2_RD_DATA && cmd_rdy_flag && cnt_rd_times < rd_times)
cmd_valid <= 1;
else
cmd_valid <= 0;
end

//cnt_wr_times
always@(posedge mclk) 
begin
if(curr_st_ddr == DDR2_WR_END || curr_st_ddr == DDR2_IDLE)
cnt_wr_times <= 3'h0 ;
else if(cmd_valid & cmd_rdy & cmd == `WRITE)
cnt_wr_times <= cnt_wr_times 1'b1 ;
else ;
end 

//cnt_rd_times
always@(posedge mclk) 
begin
if(curr_st_ddr == DDR2_IDLE)
cnt_rd_times <= 3'h0 ;
else if(cmd_valid & cmd_rdy & cmd == `READ)
cnt_rd_times <= cnt_rd_times 1'b1 ;
else ;
end

// wr_col_addr
always@(posedge mclk) 
begin
case(cnt_wr_times)
3'h0 : wr_col_addr <= 9'd0;
3'h1 : wr_col_addr <= 9'd240;
3'h2 :   wr_col_addr <= 9'd480;
default : ;
endcase
end

// rd_col_addr
always@(posedge mclk) 
begin
case(cnt_rd_times)
3'h0 : rd_col_addr <= 9'd0 ;
3'h1 : rd_col_addr <= 9'd240 ;
3'h2 :   rd_col_addr <= 9'd480 ;
default : ;
endcase
end

// read_data_valid_ff1;
always@(posedge mclk) read_data_valid_ff1 <= read_data_valid;

// ram_wren_0
always@(posedge mclk) 
if(vi_tx_ch == 4'd0 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_0_0 <= read_data_valid_ff1;
else
ram_wren_0_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd0 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_0_1 <= read_data_valid_ff1;
else
ram_wren_0_1 <= 0;

// ram_wren_1
always@(posedge mclk) 
if(vi_tx_ch == 4'd1 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_1_0 <= read_data_valid_ff1;
else
ram_wren_1_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd1 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_1_1 <= read_data_valid_ff1;
else
ram_wren_1_1 <= 0;

// ram_wren_2
always@(posedge mclk) 
if(vi_tx_ch == 4'd2 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_2_0 <= read_data_valid_ff1;
else
ram_wren_2_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd2 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_2_1 <= read_data_valid_ff1;
else
ram_wren_2_1 <= 0;

// ram_wren_3
always@(posedge mclk) 
if(vi_tx_ch == 4'd3 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_3_0 <= read_data_valid_ff1;
else
ram_wren_3_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd3 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_3_1 <= read_data_valid_ff1;
else
ram_wren_3_1 <= 0;

// ram_wren_4
always@(posedge mclk) 
if(vi_tx_ch == 4'd4 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_4_0 <= read_data_valid_ff1;
else
ram_wren_4_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd4 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_4_1 <= read_data_valid_ff1;
else
ram_wren_4_1 <= 0;

// ram_wren_5
always@(posedge mclk) 
if(vi_tx_ch == 4'd5 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_5_0 <= read_data_valid_ff1;
else
ram_wren_5_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd5 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_5_1 <= read_data_valid_ff1;
else
ram_wren_5_1 <= 0;

// 因为输出口太多，所以分成两次输出
// ram_wren_6
always@(posedge mclk) 
if(vi_tx_ch == 4'd6 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_6_0 <= read_data_valid_ff1;
else
ram_wren_6_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd6 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_6_1 <= read_data_valid_ff1;
else
ram_wren_6_1 <= 0;

// ram_wren_7
always@(posedge mclk) 
if(vi_tx_ch == 4'd7 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_7_0 <= read_data_valid_ff1;
else
ram_wren_7_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd7 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_7_1 <= read_data_valid_ff1;
else
ram_wren_7_1 <= 0;

// ram_wren_8
always@(posedge mclk) 
if(vi_tx_ch == 4'd8 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_8_0 <= read_data_valid_ff1;
else
ram_wren_8_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd8 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_8_1 <= read_data_valid_ff1;
else
ram_wren_8_1 <= 0;

// ram_wren_9
always@(posedge mclk) 
if(vi_tx_ch == 4'd9 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_9_0 <= read_data_valid_ff1;
else
ram_wren_9_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd9 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_9_1 <= read_data_valid_ff1;
else
ram_wren_9_1 <= 0;

// ram_wren_10
always@(posedge mclk) 
if(vi_tx_ch == 4'd10 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_10_0 <= read_data_valid_ff1;
else
ram_wren_10_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd10 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_10_1 <= read_data_valid_ff1;
else
ram_wren_10_1 <= 0;

// ram_wren_11
always@(posedge mclk) 
if(vi_tx_ch == 4'd11 & tx_ram_sel_lsb[1] == 1'b0)
ram_wren_11_0 <= read_data_valid_ff1;
else
ram_wren_11_0 <= 0;

always@(posedge mclk) 
if(vi_tx_ch == 4'd11 & tx_ram_sel_lsb[1] == 1'b1)
ram_wren_11_1 <= read_data_valid_ff1;
else
ram_wren_11_1 <= 0;


always@(posedge mclk)ram_wren_6_0_tmp <= ram_wren_6_0;
always@(posedge mclk)ram_wren_6_1_tmp <= ram_wren_6_1;
always@(posedge mclk)ram_wren_7_0_tmp <= ram_wren_7_0;
always@(posedge mclk)ram_wren_7_1_tmp <= ram_wren_7_1;
always@(posedge mclk)ram_wren_8_0_tmp <= ram_wren_8_0;
always@(posedge mclk)ram_wren_8_1_tmp <= ram_wren_8_1;
always@(posedge mclk)ram_wren_9_0_tmp <= ram_wren_9_0;
always@(posedge mclk)ram_wren_9_1_tmp <= ram_wren_9_1;
always@(posedge mclk)ram_wren_10_0_tmp <= ram_wren_10_0;
always@(posedge mclk)ram_wren_10_1_tmp <= ram_wren_10_1;
always@(posedge mclk)ram_wren_11_0_tmp <= ram_wren_11_0;
always@(posedge mclk)ram_wren_11_1_tmp <= ram_wren_11_1;




// read_data_ff1
always@(posedge mclk) read_data_ff1 <= read_data;
// ram_wrdata
always@(posedge mclk) ram_wrdata <= read_data_ff1;
always@(posedge mclk) ram_wrdata_tmp <= ram_wrdata ;

// ram_wraddr
always @(posedge mclk or negedge rst_n)
begin
if(!rst_n)
ram_wraddr_ff1 <= 0;
else if(!read_data_valid_ff1)
ram_wraddr_ff1 <= 0;
else if(read_data_valid_ff1)
ram_wraddr_ff1 <= ram_wraddr_ff1 1;
else
;
end
always@(posedge mclk) ram_wraddr <= {tx_ram_sel_lsb[0],ram_wraddr_ff1[7:0]};
always@(posedge mclk) ram_wraddr_tmp <= ram_wraddr;


endmodule