s32k 用户指导手册

【实例截图】

【核心代码】

Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 51
1.2 Organization..................................................................................................................................................................51
1.3 Module descriptions......................................................................................................................................................51
1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 52
1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 53
1.4 Register descriptions.....................................................................................................................................................54
1.5 Conventions.................................................................................................................................................................. 55
1.5.1 Notes, Cautions, and Warnings......................................................................................................................55
1.5.2 Numbering systems........................................................................................................................................55
1.5.3 Typographic notation..................................................................................................................................... 56
1.5.4 Special terms.................................................................................................................................................. 56
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................59
2.2 S32K1xx Series introduction........................................................................................................................................ 59
2.2.1 S32K14x.........................................................................................................................................................59
2.2.2 S32K11x ........................................................................................................................................................61
2.3 Feature summary...........................................................................................................................................................62
2.4 Block diagram...............................................................................................................................................................65
2.5 Feature comparison.......................................................................................................................................................66
2.5.1 Differences between S32K14x and S32K11x................................................................................................68
2.6 Applications.................................................................................................................................................................. 69
2.7 Module functional categories........................................................................................................................................70
2.7.1 Arm Cortex-M4F Core Modules....................................................................................................................71
2.7.2 Arm Cortex-M0  Core Modules....................................................................................................................72
2.7.3 System modules............................................................................................................................................. 72
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2.7.4 Memories and memory interfaces..................................................................................................................73
2.7.5 Power Management........................................................................................................................................74
2.7.6 Clocking......................................................................................................................................................... 74
2.7.7 Analog modules............................................................................................................................................. 75
2.7.8 Timer modules............................................................................................................................................... 75
2.7.9 Communication interfaces............................................................................................................................. 76
2.7.10 Debug modules.............................................................................................................................................. 77
Chapter 3
Memory Map
3.1 Introduction...................................................................................................................................................................79
3.2 SRAM memory map.....................................................................................................................................................79
3.2.1 S32K14x: SRAM memory map ....................................................................................................................79
3.2.2 S32K11x: SRAM memory map ....................................................................................................................79
3.3 Flash memory map........................................................................................................................................................80
3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................80
3.4.1 Read-after-write sequence and required serialization of memory operations................................................81
3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................82
3.6 Aliased bit-band regions for CM4 core........................................................................................................................ 83
Chapter 4
Signal Multiplexing and Pin Assignment
4.1 Introduction...................................................................................................................................................................85
4.2 Functional description...................................................................................................................................................85
4.3 Pad description..............................................................................................................................................................86
4.4 Default pad state........................................................................................................................................................... 87
4.5 Signal Multiplexing sheet............................................................................................................................................. 88
4.5.1 IO Signal Table ............................................................................................................................................. 88
4.5.2 Input muxing table......................................................................................................................................... 90
4.6 Pinout diagrams............................................................................................................................................................ 91
Chapter 5
Security Overview
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5.1 Introduction...................................................................................................................................................................93
5.2 Device security..............................................................................................................................................................93
5.2.1 Flash memory security................................................................................................................................... 93
5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................94
5.2.3 Device Boot modes........................................................................................................................................ 95
5.3 Security use case examples...........................................................................................................................................95
5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 95
5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 96
5.3.3 Secure communication...................................................................................................................................97
5.3.4 Component protection....................................................................................................................................98
5.3.5 Message-authentication example................................................................................................................... 99
5.4 Steps required before failure analysis...........................................................................................................................100
5.5 Security programming flow example (Secure Boot).................................................................................................... 101
Chapter 6
Safety Overview
6.1 Introduction...................................................................................................................................................................103
6.2 S32K1xx safety concept............................................................................................................................................... 104
6.2.1 Cortex-M4/M0  Structural Core Self Test (SCST).......................................................................................105
6.2.2 ECC on RAM and flash memory...................................................................................................................106
6.2.3 Power supply monitoring............................................................................................................................... 106
6.2.4 Clock monitoring........................................................................................................................................... 107
6.2.5 Temporal protection.......................................................................................................................................107
6.2.6 Operational interference protection............................................................................................................... 107
6.2.7 CRC................................................................................................................................................................109
6.2.8 Diversity of system resources........................................................................................................................ 109
Chapter 7
CM4 Overview
7.1 Arm Cortex-M4F core configuration............................................................................................................................111
7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 112
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7.1.2 System Tick Timer.........................................................................................................................................112
7.1.3 Debug facilities.............................................................................................................................................. 112
7.1.4 Caches............................................................................................................................................................ 113
7.1.5 Core privilege levels...................................................................................................................................... 113
7.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 114
7.2.1 Interrupt priority levels.................................................................................................................................. 114
7.2.2 Non-maskable interrupt..................................................................................................................................115
7.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 115
7.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................116
7.3.1 Wake-up sources............................................................................................................................................ 116
7.4 FPU configuration.........................................................................................................................................................117
7.5 JTAG controller configuration......................................................................................................................................118
Chapter 8
CM0  Overview
8.1 Arm Cortex-M0  core introduction..............................................................................................................................119
8.1.1 Buses, interconnects, and interfaces.............................................................................................................. 120
8.1.2 System tick timer........................................................................................................................................... 120
8.1.3 Debug facilities.............................................................................................................................................. 120
8.1.4 Core privilege levels...................................................................................................................................... 120
8.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................121
8.2.1 Interrupt priority levels.................................................................................................................................. 121
8.2.2 Non-maskable interrupt..................................................................................................................................121
8.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 121
8.3 AWIC introduction....................................................................................................................................................... 122
8.3.1 Wake-up sources............................................................................................................................................ 122
Chapter 9
Micro Trace Buffer (MTB)
9.1 Introduction...................................................................................................................................................................125
9.1.1 Overview........................................................................................................................................................125
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9.1.2 Features.......................................................................................................................................................... 127
9.1.3 Modes of operation........................................................................................................................................ 128
9.2 Memory map and register definition.............................................................................................................................128
9.2.1 MTB_DWT Memory Map.............................................................................................................................129
Chapter 10
Miscellaneous Control Module (MCM)
10.1 Chip-specific MCM information.................................................................................................................................. 141
10.2 Introduction...................................................................................................................................................................142
10.2.1 Features.......................................................................................................................................................... 142
10.3 Memory map/register descriptions............................................................................................................................... 142
10.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................143
10.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 144
10.3.3 Core Platform Control Register (MCM_CPCR)............................................................................................145
10.3.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 148
10.3.5 Process ID Register (MCM_PID).................................................................................................................. 151
10.3.6 Compute Operation Control Register (MCM_CPO)..................................................................................... 152
10.3.7 Local Memory Descriptor Register (MCM_LMDRn)...................................................................................153
10.3.8 Local Memory Descriptor Register2 (MCM_LMDR2).................................................................................156
10.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR).......................................................................160
10.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)...................................................................... 161
10.3.11 LMEM Fault Address Register (MCM_LMFAR).........................................................................................162
10.3.12 LMEM Fault Attribute Register (MCM_LMFATR)..................................................................................... 163
10.3.13 LMEM Fault Data High Register (MCM_LMFDHR).................................................................................. 164
10.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)....................................................................................164
10.4 Functional description...................................................................................................................................................165
10.4.1 Interrupts........................................................................................................................................................ 165
Chapter 11
System Integration Module (SIM)
11.1 Chip-specific SIM information.....................................................................................................................................167
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11.1.1 SIM register bitfield implementation.............................................................................................................167
11.2 Introduction...................................................................................................................................................................167
11.2.1 Features.......................................................................................................................................................... 167
11.3 Memory map and register definition.............................................................................................................................168
11.3.1 SIM register descriptions............................................................................................................................... 168
Chapter 12
Port Control and Interrupts (PORT)
12.1 Chip-specific PORT information..................................................................................................................................195
12.1.1 Number of PCRs............................................................................................................................................ 195
12.1.2 Finding address for PORTx_PCRn ...............................................................................................................196
12.1.3 I/O configuration sequence ........................................................................................................................... 196
12.1.4 Digital input filter configuration sequence ................................................................................................... 197
12.1.5 Reset pin configuration ................................................................................................................................. 198
12.2 Introduction...................................................................................................................................................................198
12.3 Overview.......................................................................................................................................................................198
12.3.1 Features.......................................................................................................................................................... 198
12.3.2 Modes of operation........................................................................................................................................ 199
12.4 External signal description............................................................................................................................................200
12.5 Detailed signal description............................................................................................................................................200
12.6 Memory map and register definition.............................................................................................................................200
12.6.1 Pin Control Register n (PORT_PCRn).......................................................................................................... 203
12.6.2 Global Pin Control Low Register (PORT_GPCLR)......................................................................................206
12.6.3 Global Pin Control High Register (PORT_GPCHR).....................................................................................206
12.6.4 Global Interrupt Control Low Register (PORT_GICLR).............................................................................. 207
12.6.5 Global Interrupt Control High Register (PORT_GICHR).............................................................................207
12.6.6 Interrupt Status Flag Register (PORT_ISFR)................................................................................................ 208
12.6.7 Digital Filter Enable Register (PORT_DFER).............................................................................................. 209
12.6.8 Digital Filter Clock Register (PORT_DFCR)................................................................................................209
12.6.9 Digital Filter Width Register (PORT_DFWR).............................................................................................. 210
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12.7 Functional description...................................................................................................................................................210
12.7.1 Pin control...................................................................................................................................................... 210
12.7.2 Global pin control.......................................................................................................................................... 211
12.7.3 Global interrupt control..................................................................................................................................212
12.7.4 External interrupts..........................................................................................................................................212
12.7.5 Digital filter....................................................................................................................................................213
Chapter 13
General-Purpose Input/Output (GPIO)
13.1 Chip-specific GPIO information...................................................................................................................................215
13.1.1 Instantiation information................................................................................................................................215
13.1.2 GPIO ports memory map............................................................................................................................... 215
13.1.3 GPIO register reset values .............................................................................................................................216
13.2 Introduction...................................................................................................................................................................216
13.2.1 Features.......................................................................................................................................................... 217
13.2.2 Modes of operation........................................................................................................................................ 217
13.2.3 GPIO signal descriptions............................................................................................................................... 217
13.3 Memory map and register definition.............................................................................................................................218
13.3.1 GPIO register descriptions............................................................................................................................. 218
13.4 Functional description...................................................................................................................................................226
13.4.1 General-purpose input....................................................................................................................................226
13.4.2 General-purpose output..................................................................................................................................226
Chapter 14
Crossbar Switch Lite (AXBS-Lite)
14.1 Chip-specific AXBS-Lite information..........................................................................................................................229
14.1.1 Crossbar Switch master assignments............................................................................................................. 229
14.1.2 Crossbar Switch slave assignments................................................................................................................229
14.2 Introduction...................................................................................................................................................................230
14.2.1 Features.......................................................................................................................................................... 230
14.3 Functional Description..................................................................................................................................................231
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14.3.1 General operation...........................................................................................................................................231
14.3.2 Arbitration......................................................................................................................................................231
14.4 Initialization/application information........................................................................................................................... 233
Chapter 15
Memory Protection Unit (MPU)
15.1 Chip-specific MPU information................................................................................................................................... 235
15.1.1 MPU Slave Port Assignments........................................................................................................................235
15.1.2 MPU Logical Bus Master Assignments.........................................................................................................236
15.1.3 Current PID.................................................................................................................................................... 236
15.1.4 Region descriptors and slave port configuration............................................................................................236
15.2 Introduction...................................................................................................................................................................237
15.3 Overview.......................................................................................................................................................................237
15.3.1 Block diagram................................................................................................................................................ 237
15.3.2 Features.......................................................................................................................................................... 238
15.4 MPU register descriptions.............................................................................................................................................239
15.4.1 MPU Memory map........................................................................................................................................ 239
15.4.2 Control/Error Status Register (CESR)........................................................................................................... 242
15.4.3 Error Address Register, slave port n (EAR0 - EAR4)................................................................................... 244
15.4.4 Error Detail Register, slave port n (EDR0 - EDR4)...................................................................................... 245
15.4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WORD0)...........................................................247
15.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)...........................................................................................248
15.4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)...........................................................................................249
15.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)...........................................................................................252
15.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)...........................................................253
15.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)...........................................................254
15.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)...........................................................257
15.4.12 Region Descriptor Alternate Access Control 0 (RGDAAC0)....................................................................... 259
15.4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)............................................... 262
15.5 Functional description...................................................................................................................................................265
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15.5.1 Access evaluation macro................................................................................................................................265
15.5.2 Putting it all together and error terminations................................................................................................. 267
15.5.3 Power management........................................................................................................................................ 267
15.6 Initialization information.............................................................................................................................................. 268
15.7 Application information................................................................................................................................................268
Chapter 16
Peripheral Bridge (AIPS-Lite)
16.1 Chip-specific AIPS information................................................................................................................................... 271
16.1.1 Instantiation information................................................................................................................................271
16.1.2 Memory maps................................................................................................................................................ 271
16.2 Introduction...................................................................................................................................................................272
16.2.1 Features.......................................................................................................................................................... 273
16.2.2 General operation...........................................................................................................................................273
16.3 Memory map/register definition................................................................................................................................... 273
16.3.1 AIPS register descriptions..............................................................................................................................273
16.4 Functional description...................................................................................................................................................317
16.4.1 Access support............................................................................................................................................... 317
Chapter 17
Direct Memory Access Multiplexer (DMAMUX)
17.1 Chip-specific DMAMUX information......................................................................................................................... 319
17.1.1 Number of channels ...................................................................................................................................... 319
17.1.2 DMA transfers via TRGMUX trigger............................................................................................................319
17.2 Introduction...................................................................................................................................................................320
17.2.1 Overview........................................................................................................................................................320
17.2.2 Features.......................................................................................................................................................... 320
17.2.3 Modes of operation........................................................................................................................................ 321
17.3 Memory map/register definition................................................................................................................................... 321
17.3.1 DMAMUX register descriptions....................................................................................................................321
17.4 Functional description...................................................................................................................................................323
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17.4.1 DMA channels with periodic triggering capability........................................................................................323
17.4.2 DMA channels with no triggering capability.................................................................................................326
17.4.3 Always-enabled DMA sources...................................................................................................................... 326
17.5 Initialization/application information........................................................................................................................... 327
17.5.1 Reset...............................................................................................................................................................327
17.5.2 Enabling and configuring sources..................................................................................................................327
Chapter 18
Enhanced Direct Memory Access (eDMA)
18.1 Chip-specific eDMA information ................................................................................................................................331
18.1.1 Seamless eDMA transfer .............................................................................................................................. 331
18.1.2 Number of channels ...................................................................................................................................... 332
18.2 Introduction...................................................................................................................................................................332
18.2.1 eDMA system block diagram........................................................................................................................ 332
18.2.2 Block parts..................................................................................................................................................... 333
18.2.3 Features.......................................................................................................................................................... 334
18.3 Modes of operation....................................................................................................................................................... 335
18.4 Memory map/register definition................................................................................................................................... 336
18.4.1 TCD memory................................................................................................................................................. 336
18.4.2 TCD initialization.......................................................................................................................................... 336
18.4.3 TCD structure.................................................................................................................................................336
18.4.4 Reserved memory and bit fields.....................................................................................................................337
18.4.5 DMA register descriptions............................................................................................................................. 337
18.5 Functional description...................................................................................................................................................386
18.5.1 eDMA basic data flow................................................................................................................................... 386
18.5.2 Fault reporting and handling.......................................................................................................................... 389
18.5.3 Channel preemption....................................................................................................................................... 392
18.6 Initialization/application information........................................................................................................................... 392
18.6.1 eDMA initialization....................................................................................................................................... 392
18.6.2 Programming errors....................................................................................................................................... 394
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18.6.3 Arbitration mode considerations....................................................................................................................395
18.6.4 Performing DMA transfers............................................................................................................................ 395
18.6.5 Monitoring transfer descriptor status............................................................................................................. 399
18.6.6 Channel Linking.............................................................................................................................................401
18.6.7 Dynamic programming.................................................................................................................................. 402
18.6.8 Suspend/resume a DMA channel with active hardware service requests......................................................406
Chapter 19
Trigger MUX Control (TRGMUX)
19.1 Chip-specific TRGMUX information...........................................................................................................................409
19.1.1 Module interconnectivity............................................................................................................................... 409
19.1.2 TRGMUX register information..................................................................................................................... 413
19.2 Introduction...................................................................................................................................................................413
19.3 Features.........................................................................................................................................................................413
19.4 Memory map and register definition.............................................................................................................................414
19.4.1 TRGMUX register descriptions..................................................................................................................... 414
Chapter 20
External Watchdog Monitor (EWM)
20.1 Chip-specific EWM information ................................................................................................................................. 453
20.1.1 EWM_OUT signal configuration...................................................................................................................453
20.1.2 EWM Memory Map access............................................................................................................................453
20.1.3 EWM low-power modes................................................................................................................................ 453
20.2 Introduction...................................................................................................................................................................453
20.2.1 Features.......................................................................................................................................................... 454
20.2.2 Modes of Operation....................................................................................................................................... 454
20.2.3 Block Diagram............................................................................................................................................... 455
20.3 EWM Signal Descriptions............................................................................................................................................ 456
20.4 Memory Map/Register Definition.................................................................................................................................457
20.4.1 EWM register descriptions.............................................................................................................................457
20.5 Functional Description..................................................................................................................................................462
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20.5.1 The EWM_OUT_b Signal............................................................................................................................. 462
20.5.2 EWM_OUT_b pin state in low power modes................................................................................................463
20.5.3 The EWM_in Signal...................................................................................................................................... 463
20.5.4 EWM Counter................................................................................................................................................ 464
20.5.5 EWM Compare Registers.............................................................................................................................. 464
20.5.6 EWM Refresh Mechanism.............................................................................................................................464
20.5.7 EWM Interrupt...............................................................................................................................................465
20.5.8 Counter clock prescaler..................................................................................................................................465
Chapter 21
Error Injection Module (EIM)
21.1 Chip-specific EIM information.....................................................................................................................................467
21.1.1 EIM channel assignments.............................................................................................................................. 467
21.2 Introduction...................................................................................................................................................................467
21.2.1 Overview........................................................................................................................................................467
21.2.2 Features.......................................................................................................................................................... 469
21.3 EIM register descriptions..............................................................................................................................................469
21.3.1 EIM Memory map..........................................................................................................................................470
21.3.2 Error Injection Module Configuration Register (EIMCR)............................................................................ 470
21.3.3 Error Injection Channel Enable register (EICHEN)...................................................................................... 471
21.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)............................474
21.3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)............................476
21.4 Functional description...................................................................................................................................................477
21.4.1 Error injection scenarios................................................................................................................................ 477
Chapter 22
Error Reporting Module (ERM)
22.1 Chip-specific ERM information................................................................................................................................... 479
22.1.1 Sources of memory error events.................................................................................................................... 479
22.2 Introduction...................................................................................................................................................................479
22.2.1 Overview........................................................................................................................................................479
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22.2.2 Features.......................................................................................................................................................... 480
22.3 ERM register descriptions.............................................................................................................................................480
22.3.1 ERM Memory map........................................................................................................................................ 480
22.3.2 ERM Configuration Register 0 (CR0)........................................................................................................... 481
22.3.3 ERM Status Register 0 (SR0)........................................................................................................................ 483
22.3.4 ERM Memory n Error Address Register (EAR0 - EAR1)............................................................................ 485
22.4 Functional description...................................................................................................................................................486
22.4.1 Single-bit correction events........................................................................................................................... 486
22.4.2 Non-correctable error events..........................................................................................................................487
22.5 Initialization.................................................................................................................................................................. 488
Chapter 23
Watchdog timer (WDOG)
23.1 Chip-specific WDOG information................................................................................................................................489
23.1.1 WDOG clocks................................................................................................................................................ 489
23.1.2 WDOG low-power modes............................................................................................................................. 489
23.1.3 Default watchdog timeout .............................................................................................................................490
23.1.4 Watchdog Timeout Reaction......................................................................................................................... 490
23.2 Introduction...................................................................................................................................................................491
23.2.1 Features.......................................................................................................................................................... 491
23.2.2 Block diagram................................................................................................................................................ 492
23.3 Memory map and register definition.............................................................................................................................492
23.3.1 WDOG register descriptions..........................................................................................................................492
23.4 Functional description...................................................................................................................................................499
23.4.1 Clock source...................................................................................................................................................499
23.4.2 Watchdog refresh mechanism........................................................................................................................500
23.4.3 Configuring the Watchdog.............................................................................................................................502
23.4.4 Using interrupts to delay resets......................................................................................................................503
23.4.5 Backup reset...................................................................................................................................................503
23.4.6 Functionality in debug and low-power modes...............................................................................................504
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23.4.7 Fast testing of the watchdog...........................................................................................................................504
23.5 Application Information................................................................................................................................................506
23.5.1 Disable Watchdog.......................................................................................................................................... 506
23.5.2 Disable Watchdog after Reset........................................................................................................................506
23.5.3 Configure Watchdog...................................................................................................................................... 507
23.5.4 Refreshing the Watchdog...............................................................................................................................507
Chapter 24
Cyclic Redundancy Check (CRC)
24.1 Chip-specific CRC information.................................................................................................................................... 509
24.2 Introduction...................................................................................................................................................................509
24.2.1 Features.......................................................................................................................................................... 509
24.2.2 Block diagram................................................................................................................................................ 510
24.2.3 Modes of operation........................................................................................................................................ 510
24.3 Memory map and register descriptions.........................................................................................................................510
24.3.1 CRC register descriptions.............................................................................................................................. 510
24.4 Functional description...................................................................................................................................................515
24.4.1 CRC initialization/reinitialization.................................................................................................................. 515
24.4.2 CRC calculations............................................................................................................................................515
24.4.3 Transpose feature........................................................................................................................................... 516
24.4.4 CRC result complement................................................................................................................................. 518
Chapter 25
Reset and Boot
25.1 Introduction...................................................................................................................................................................519
25.2 Reset..............................................................................................................................................................................519
25.2.1 Power-on reset (POR).................................................................................................................................... 520
25.2.2 System reset sources...................................................................................................................................... 520
25.2.3 MCU Resets................................................................................................................................................... 524
25.2.4 Reset pin ........................................................................................................................................................524
25.2.5 Debug resets...................................................................................................................................................525
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25.3 Boot...............................................................................................................................................................................526
25.3.1 Boot sources...................................................................................................................................................526
25.3.2 FOPT boot options......................................................................................................................................... 526
25.3.3 Boot sequence................................................................................................................................................ 527
Chapter 26
Reset Control Module (RCM)
26.1 Chip-specific RCM information................................................................................................................................... 529
26.1.1 RCM register information .............................................................................................................................529
26.2 Reset pin filter operation in STOP1/2 modes .............................................................................................................. 530
26.3 Introduction...................................................................................................................................................................530
26.4 Reset memory map and register descriptions............................................................................................................... 530
26.4.1 Version ID Register (RCM_VERID).............................................................................................................531
26.4.2 Parameter Register (RCM_PARAM)............................................................................................................ 532
26.4.3 System Reset Status Register (RCM_SRS)................................................................................................... 534
26.4.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 537
26.4.5 Sticky System Reset Status Register (RCM_SSRS)......................................................................................539
26.4.6 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 541
Chapter 27
Clock Distribution
27.1 Introduction...................................................................................................................................................................545
27.2 High level clocking diagram.........................................................................................................................................545
27.3 Clock definitions...........................................................................................................................................................546
27.4 Internal clocking requirements..................................................................................................................................... 548
27.4.1 Clock divider values after reset......................................................................................................................552
27.4.2 HSRUN mode clocking................................................................................................................................. 552
27.4.3 VLPR mode clocking.....................................................................................................................................552
27.4.4 VLPR/VLPS mode entry............................................................................................................................... 552
27.5 Clock Gating................................................................................................................................................................. 553
27.6 Module clocks...............................................................................................................................................................553
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Chapter 28
System Clock Generator (SCG)
28.1 Chip-specific SCG information.................................................................................................................................... 565
28.1.1 Supported frequency ranges...........................................................................................................................565
28.1.2 Oscillator and SPLL guidelines..................................................................................................................... 565
28.1.3 System clock switching .................................................................................................................................566
28.1.4 System clock and clock monitor requirement ...............................................................................................566
28.2 Introduction...................................................................................................................................................................567
28.2.1 Features.......................................................................................................................................................... 567
28.3 Memory Map/Register Definition.................................................................................................................................568
28.3.1 Version ID Register (SCG_VERID)..............................................................................................................569
28.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 570
28.3.3 Clock Status Register (SCG_CSR)................................................................................................................ 571
28.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................573
28.3.5 VLPR Clock Control Register (SCG_VCCR)............................................................................................... 575
28.3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................577
28.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................579
28.3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................581
28.3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 583
28.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 584
28.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................586
28.3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 587
28.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................588
28.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 589
28.3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................591
28.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 592
28.3.17 System PLL Control Status Register (SCG_SPLLCSR)............................................................................... 593
28.3.18 System PLL Divide Register (SCG_SPLLDIV)............................................................................................595
28.3.19 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 596
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28.4 Functional description...................................................................................................................................................598
28.4.1 SCG Clock Mode Transitions........................................................................................................................ 598
Chapter 29
Peripheral Clock Controller (PCC)
29.1 Chip-specific PCC information.....................................................................................................................................601
29.1.1 PCC register information............................................................................................................................... 601
29.2 Introduction...................................................................................................................................................................604
29.3 Features.........................................................................................................................................................................604
29.4 Functional description...................................................................................................................................................605
29.5 Memory map and register definition.............................................................................................................................606
29.6 PCC register descriptions..............................................................................................................................................606
29.6.1 PCC Memory map......................................................................................................................................... 606
29.6.2 PCC FTFC Register (PCC_FTFC)................................................................................................................ 607
29.6.3 PCC DMAMUX Register (PCC_DMAMUX).............................................................................................. 609
29.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)................................................................................................ 610
29.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)................................................................................................ 612
29.6.6 PCC FTM3 Register (PCC_FTM3)............................................................................................................... 613
29.6.7 PCC ADC1 Register (PCC_ADC1)...............................................................................................................615
29.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)................................................................................................ 616
29.6.9 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................618
29.6.10 PCC LPSPI1 Register (PCC_LPSPI1)...........................................................................................................620
29.6.11 PCC LPSPI2 Register (PCC_LPSPI2)...........................................................................................................621
29.6.12 PCC PDB1 Register (PCC_PDB1)................................................................................................................ 623
29.6.13 PCC CRC Register (PCC_CRC)....................................................................................................................625
29.6.14 PCC PDB0 Register (PCC_PDB0)................................................................................................................ 626
29.6.15 PCC LPIT Register (PCC_LPIT)...................................................................................................................628
29.6.16 PCC FTM0 Register (PCC_FTM0)............................................................................................................... 629
29.6.17 PCC FTM1 Register (PCC_FTM1)............................................................................................................... 631
29.6.18 PCC FTM2 Register (PCC_FTM2)............................................................................................................... 632
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29.6.19 PCC ADC0 Register (PCC_ADC0)...............................................................................................................634
29.6.20 PCC RTC Register (PCC_RTC).................................................................................................................... 636
29.6.21 PCC LPTMR0 Register (PCC_LPTMR0).....................................................................................................637
29.6.22 PCC PORTA Register (PCC_PORTA)......................................................................................................... 639
29.6.23 PCC PORTB Register (PCC_PORTB)..........................................................................................................641
29.6.24 PCC PORTC Register (PCC_PORTC)..........................................................................................................642
29.6.25 PCC PORTD Register (PCC_PORTD)......................................................................................................... 644
29.6.26 PCC PORTE Register (PCC_PORTE).......................................................................................................... 645
29.6.27 PCC SAI0 Register (PCC_SAI0)...................................................................................................................647
29.6.28 PCC SAI1 Register (PCC_SAI1)...................................................................................................................648
29.6.29 PCC FlexIO Register (PCC_FlexIO).............................................................................................................650
29.6.30 PCC EWM Register (PCC_EWM)................................................................................................................ 651
29.6.31 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 653
29.6.32 PCC LPI2C1 Register (PCC_LPI2C1).......................................................................................................... 654
29.6.33 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 656
29.6.34 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 657
29.6.35 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 659
29.6.36 PCC FTM4 Register (PCC_FTM4)............................................................................................................... 661
29.6.37 PCC FTM5 Register (PCC_FTM5)............................................................................................................... 662
29.6.38 PCC FTM6 Register (PCC_FTM6)............................................................................................................... 664
29.6.39 PCC FTM7 Register (PCC_FTM7)............................................................................................................... 666
29.6.40 PCC CMP0 Register (PCC_CMP0)...............................................................................................................667
29.6.41 PCC QSPI Register (PCC_QSPI).................................................................................................................. 669
29.6.42 PCC ENET Register (PCC_ENET)............................................................................................................... 671
Chapter 30
Clock Monitoring Unit (CMU)
30.1 CMU chip-specific information....................................................................................................................................673
30.2 Introduction...................................................................................................................................................................674
30.2.1 Basic operation...............................................................................................................................................675
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30.2.2 Features.......................................................................................................................................................... 676
30.3 CMU_FC register descriptions..................................................................................................................................... 676
30.3.1 CMU_FC Memory map................................................................................................................................. 676
30.3.2 Global Configuration Register (GCR)........................................................................................................... 677
30.3.3 Reference Count Configuration Register (RCCR).........................................................................................678
30.3.4 High Threshold Configuration Register (HTCR).......................................................................................... 679
30.3.5 Low Threshold Configuration Register (LTCR)........................................................................................... 680
30.3.6 Status Register (SR)....................................................................................................................................... 681
30.3.7 Interrupt Enable Register (IER)..................................................................................................................... 682
30.4 Functional description...................................................................................................................................................685
30.4.1 Monitored clock lost...................................................................................................................................... 685
30.5 Programming guidelines............................................................................................................................................... 685
30.5.1 Programming HFREF and LFREF................................................................................................................ 685
30.5.2 Programming RCCR[REF_CNT].................................................................................................................. 686
30.5.3 CMU_FC programming sequence................................................................................................................. 687
Chapter 31
Memories and Memory Interfaces
31.1 Introduction...................................................................................................................................................................689
31.2 Flash Memory Controller and flash memory modules................................................................................................. 689
31.3 SRAM configuration.....................................................................................................................................................690
31.3.1 SRAM sizes....................................................................................................................................................690
31.3.2 SRAM accessibility........................................................................................................................................691
31.3.3 SRAM arbitration and priority control...........................................................................................................692
31.3.4 SRAM retention: power modes and resets.....................................................................................................692
31.3.5 SRAM access: Behavior of device when in accessing a memory with multi-bit ECC error.........................693
Chapter 32
PRAM Controller (PRAMC)
32.1 PRAMC chip-specific information ..............................................................................................................................695
32.2 Introduction...................................................................................................................................................................695
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32.3 Memory map and register definition.............................................................................................................................696
32.4 Functional description...................................................................................................................................................696
32.4.1 Error Correcting Code (ECC)........................................................................................................................ 696
32.4.2 Read/Write introduction.................................................................................................................................697
32.4.3 Reads..............................................................................................................................................................697
32.4.4 Writes............................................................................................................................................................. 698
32.4.5 Late write hits.................................................................................................................................................699
32.5 Initialization / application information......................................................................................................................... 700
Chapter 33
Local Memory Controller (LMEM)
33.1 Chip-specific LMEM information ............................................................................................................................... 701
33.1.1 LMEM region description..............................................................................................................................701
33.1.2 LMEM SRAM sizes.......................................................................................................................................701
33.2 Introduction...................................................................................................................................................................701
33.2.1 Block Diagram............................................................................................................................................... 702
33.2.2 Cache features................................................................................................................................................ 703
33.3 Memory Map/Register Definition.................................................................................................................................705
33.3.1 LMEM register descriptions.......................................................................................................................... 705
33.4 Functional Description..................................................................................................................................................714
33.4.1 LMEM Function............................................................................................................................................ 714
33.4.2 SRAM Function............................................................................................................................................. 715
33.4.3 Cache Function.............................................................................................................................................. 717
33.4.4 Cache Control................................................................................................................................................ 718
Chapter 34
Miscellaneous System Control Module (MSCM)
34.1 Chip-specific MSCM information................................................................................................................................ 723
34.1.1 Chip-specific TMLSZ/TMUSZ information................................................................................................. 723
34.1.2 Chip-specific register information................................................................................................................. 723
34.2 Overview.......................................................................................................................................................................724
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34.3 Chip Configuration and Boot........................................................................................................................................724
34.4 MSCM Memory Map/Register Definition....................................................................................................................725
34.4.1 CPU Configuration Memory Map and Registers...........................................................................................725
34.4.2 MSCM register descriptions.......................................................................................................................... 725
Chapter 35
Flash Memory Controller (FMC)
35.1 Chip-specific FMC information....................................................................................................................................757
35.1.1 FMC masters.................................................................................................................................................. 757
35.1.2 Program flash and Data flash port width....................................................................................................... 758
35.2 Introduction...................................................................................................................................................................758
35.2.1 Overview........................................................................................................................................................758
35.2.2 Features.......................................................................................................................................................... 758
35.3 Modes of operation....................................................................................................................................................... 759
35.4 External signal description............................................................................................................................................759
35.5 Functional description...................................................................................................................................................759
35.5.1 Default configuration..................................................................................................................................... 759
35.5.2 Speculative reads............................................................................................................................................760
35.6 Initialization and application information.....................................................................................................................761
Chapter 36
Flash Memory Module (FTFC)
36.1 Chip-specific FTFC information...................................................................................................................................763
36.1.1 Flash memory types....................................................................................................................................... 763
36.1.2 Flash memory sizes........................................................................................................................................764
36.1.3 Flash memory map.........................................................................................................................................783
36.1.4 Flash memory security................................................................................................................................... 784
36.1.5 Power mode restrictions on flash memory programming..............................................................................784
36.1.6 Flash memory modes..................................................................................................................................... 784
36.1.7 Erase all contents of flash memory................................................................................................................ 784
36.1.8 Customize MCU operations via FTFC_FOPT register..................................................................................785
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36.1.9 Simultaneous operations on PFLASH read partitions .................................................................................. 785
36.2 Introduction...................................................................................................................................................................785
36.2.1 Features.......................................................................................................................................................... 786
36.2.2 Block diagram................................................................................................................................................ 788
36.2.3 Glossary......................................................................................................................................................... 789
36.3 External signal description............................................................................................................................................791
36.4 Memory map and registers............................................................................................................................................792
36.4.1 Flash configuration field description............................................................................................................. 792
36.4.2 Program flash 0 IFR map............................................................................................................................... 792
36.4.3 Data flash 0 IFR map..................................................................................................................................... 793
36.4.4 Register descriptions...................................................................................................................................... 794
36.5 Functional description...................................................................................................................................................812
36.5.1 Flash protection..............................................................................................................................................812
36.5.2 FlexNVM description.................................................................................................................................... 814
36.5.3 Interrupts........................................................................................................................................................ 817
36.5.4 Flash operation in low-power modes............................................................................................................. 818
36.5.5 Functional modes of operation.......................................................................................................................818
36.5.6 Flash memory reads and ignored writes........................................................................................................ 818
36.5.7 Read while write (RWW).............................................................................................................................. 819
36.5.8 Flash program and erase................................................................................................................................ 819
36.5.9 FTFC command operations............................................................................................................................819
36.5.10 Margin read commands..................................................................................................................................826
36.5.11 Flash command descriptions..........................................................................................................................827
36.5.12 Security.......................................................................................................................................................... 853
36.5.13 Cryptographic Services Engine (CSEc).........................................................................................................855
36.5.14 Reset sequence............................................................................................................................................... 893
Chapter 37
Quad Serial Peripheral Interface (QuadSPI)
37.1 Chip-specific QuadSPI information..............................................................................................................................895
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37.1.1 Overview........................................................................................................................................................895
37.1.2 Memory size requirement ............................................................................................................................. 895
37.1.3 QuadSPI register reset values........................................................................................................................ 896
37.1.4 Use case..........................................................................................................................................................896
37.1.5 Supported read modes....................................................................................................................................896
37.1.6 External memory options............................................................................................................................... 897
37.1.7 Recommended software configuration.......................................................................................................... 897
37.1.8 Recommended programming sequence......................................................................................................... 898
37.1.9 Clock ratio between QuadSPI clocks ............................................................................................................898
37.1.10 QuadSPI_MCR[SCLKCFG] implementation ...............................................................................................898
37.1.11 QuadSPI_SOCCR[SOCCFG] implementation .............................................................................................899
37.2 Introduction...................................................................................................................................................................901
37.2.1 Features.......................................................................................................................................................... 901
37.2.2 Block Diagram............................................................................................................................................... 902
37.2.3 QuadSPI Modes of Operation........................................................................................................................ 903
37.2.4 Acronyms and Abbreviations.........................................................................................................................904
37.2.5 Glossary for QuadSPI module....................................................................................................................... 904
37.3 External Signal Description.......................................................................................................................................... 906
37.3.1 Driving External Signals................................................................................................................................907
37.4 Memory Map and Register Definition..........................................................................................................................909
37.4.1 Register Write Access....................................................................................................................................909
37.4.2 Peripheral Bus Register Descriptions............................................................................................................ 910
37.4.3 Serial Flash Address Assignment.................................................................................................................. 954
37.5 Flash memory mapped AMBA bus.............................................................................................................................. 955
37.5.1 AHB Bus Access Considerations...................................................................................................................956
37.5.2 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A.....................................................956
37.5.3 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B..................................................... 957
37.5.4 AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31).......................................................................... 958
37.6 Interrupt Signals............................................................................................................................................................960
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37.7 Functional Description..................................................................................................................................................961
37.7.1 Serial Flash Access Schemes......................................................................................................................... 961
37.7.2 Normal Mode................................................................................................................................................. 961
37.7.3 HyperRAM Support.......................................................................................................................................980
37.8 Initialization/Application Information..........................................................................................................................981
37.8.1 Power Up and Reset.......................................................................................................................................981
37.8.2 Available Status/Flag Information................................................................................................................. 981
37.8.3 Flash Device Selection...................................................................................................................................984
37.8.4 DMA Usage................................................................................................................................................... 984
37.9 Byte Ordering - Endianness..........................................................................................................................................988
37.9.1 Programming Flash Data............................................................................................................................... 989
37.9.2 Reading Flash Data into the RX Buffer......................................................................................................... 989
37.9.3 Reading Flash Data into the AHB Buffer...................................................................................................... 990
37.10 Driving Flash Control Signals in Single and Dual Mode............................................................................................. 991
37.11 Serial Flash Devices......................................................................................................................................................991
37.11.1 Example Sequences........................................................................................................................................991
37.12 Sampling of Serial Flash Input Data.............................................................................................................................997
37.12.1 Basic Description........................................................................................................................................... 997
37.12.2 Supported read modes....................................................................................................................................998
37.12.3 Data Strobe (DQS) sampling method............................................................................................................ 1001
37.13 Data Input Hold Requirement of Flash.........................................................................................................................1004
Chapter 38
Power Management
38.1 Introduction...................................................................................................................................................................1005
38.2 Power modes description.............................................................................................................................................. 1005
38.3 Entering and exiting power modes............................................................................................................................... 1007
38.4 Clocking modes............................................................................................................................................................ 1007
38.4.1 Clock gating................................................................................................................................................... 1007
38.4.2 Stop mode options..........................................................................................................................................1007
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38.4.3 DMA wake-up................................................................................................................................................1008
38.4.4 Compute Operation (CPO).............................................................................................................................1009
38.4.5 Peripheral Doze..............................................................................................................................................1010
38.5 Power mode transitions.................................................................................................................................................1011
38.6 Shutdown sequencing for power modes....................................................................................................................... 1012
38.7 Power mode restrictions on flash memory programming.............................................................................................1012
38.8 Module operation in available power modes................................................................................................................1013
38.9 QuadSPI, Ethernet, and SAI operation ........................................................................................................................ 1017
Chapter 39
System Mode Controller (SMC)
39.1 Introduction...................................................................................................................................................................1019
39.2 Modes of operation....................................................................................................................................................... 1019
39.3 Memory map and register descriptions.........................................................................................................................1021
39.3.1 SMC Version ID Register (SMC_VERID)....................................................................................................1022
39.3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 1023
39.3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................1024
39.3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................1025
39.3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................1027
39.3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 1029
39.4 Functional description...................................................................................................................................................1029
39.4.1 Power mode transitions..................................................................................................................................1030
39.4.2 Power mode entry/exit sequencing................................................................................................................ 1031
39.4.3 Run modes......................................................................................................................................................1034
39.4.4 Stop modes.....................................................................................................................................................1036
39.4.5 Debug in low power modes........................................................................................................................... 1037
Chapter 40
Power Management Controller (PMC)
40.1 Chip-specific PMC information....................................................................................................................................1039
40.1.1 Modes supported............................................................................................................................................ 1039
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40.2 Introduction...................................................................................................................................................................1039
40.3 Features.........................................................................................................................................................................1039
40.4 Modes of Operation...................................................................................................................................................... 1040
40.4.1 Full Performance Mode (FPM)......................................................................................................................1040
40.4.2 Low Power Mode (LPM)...............................................................................................................................1040
40.5 Low Voltage Detect (LVD) System............................................................................................................................. 1040
40.5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 1041
40.5.2 LVD Interrupt Operation............................................................................................................................... 1041
40.5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 1041
40.6 Memory Map and Register Definition..........................................................................................................................1041
40.6.1 PMC register descriptions..............................................................................................................................1041
Chapter 41
ADC Configuration
41.1 Instantiation information...............................................................................................................................................1049
41.1.1 Number of ADC channels..............................................................................................................................1049
41.1.2 ADC Connections/Channel Assignment........................................................................................................1050
41.2 Register implementation............................................................................................................................................... 1051
41.3 DMA Support on ADC................................................................................................................................................. 1051
41.4 ADC Hardware Interleaved Channels.......................................................................................................................... 1052
41.5 ADC internal supply monitoring.................................................................................................................................. 1053
41.6 ADC Reference Options............................................................................................................................................... 1053
41.7 ADC Trigger Sources................................................................................................................................................... 1053
41.7.1 PDB triggering scheme.................................................................................................................................. 1055
41.7.2 TRGMUX trigger scheme..............................................................................................................................1056
41.8 Trigger Selection...........................................................................................................................................................1057
41.9 Trigger Latching and Arbitration..................................................................................................................................1058
41.10 ADC triggering configurations .................................................................................................................................... 1060
41.11 ADC low-power modes................................................................................................................................................ 1067
41.12 ADC Trigger Concept – Use Case................................................................................................................................1067
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41.13 ADC calibration scheme...............................................................................................................................................1069
41.14 S32K11X to S32K14X difference ............................................................................................................................... 1070
Chapter 42
Analog-to-Digital Converter (ADC)
42.1 Chip-specific ADC information....................................................................................................................................1071
42.2 Introduction...................................................................................................................................................................1071
42.2.1 Features.......................................................................................................................................................... 1071
42.2.2 Block diagram................................................................................................................................................ 1072
42.3 ADC signal descriptions............................................................................................................................................... 1073
42.3.1 Analog Power (VDDA)................................................................................................................................. 1073
42.3.2 Analog Ground (VSSA).................................................................................................................................1073
42.3.3 Voltage Reference Select............................................................................................................................... 1073
42.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 1074
42.4 ADC register descriptions.............................................................................................................................................1074
42.4.1 ADC Memory map.........................................................................................................................................1074
42.4.2 ADC Status and Control Register 1 (SC1A - aSC1P)................................................................................... 1076
42.4.3 ADC Configuration Register 1 (CFG1)......................................................................................................... 1079
42.4.4 ADC Configuration Register 2 (CFG2)......................................................................................................... 1081
42.4.5 ADC Data Result Registers (RA - aRP)........................................................................................................ 1082
42.4.6 Compare Value Registers (CV1 - CV2)........................................................................................................ 1084
42.4.7 Status and Control Register 2 (SC2).............................................................................................................. 1085
42.4.8 Status and Control Register 3 (SC3).............................................................................................................. 1088
42.4.9 BASE Offset Register (BASE_OFS).............................................................................................................1089
42.4.10 ADC Offset Correction Register (OFS).........................................................................................................1090
42.4.11 USER Offset Correction Register (USR_OFS)............................................................................................. 1091
42.4.12 ADC X Offset Correction Register (XOFS).................................................................................................. 1092
42.4.13 ADC Y Offset Correction Register (YOFS).................................................................................................. 1093
42.4.14 ADC Gain Register (G)..................................................................................................................................1094
42.4.15 ADC User Gain Register (UG)...................................................................................................................... 1096
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42.4.16 ADC General Calibration Value Register S (CLPS)..................................................................................... 1097
42.4.17 ADC Plus-Side General Calibration Value Register 3 (CLP3)..................................................................... 1098
42.4.18 ADC Plus-Side General Calibration Value Register 2 (CLP2)..................................................................... 1099
42.4.19 ADC Plus-Side General Calibration Value Register 1 (CLP1)..................................................................... 1099
42.4.20 ADC Plus-Side General Calibration Value Register 0 (CLP0)..................................................................... 1100
42.4.21 ADC Plus-Side General Calibration Value Register X (CLPX)....................................................................1101
42.4.22 ADC Plus-Side General Calibration Value Register 9 (CLP9)..................................................................... 1102
42.4.23 ADC General Calibration Offset Value Register S (CLPS_OFS).................................................................1103
42.4.24 ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS)................................................. 1104
42.4.25 ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS)................................................. 1105
42.4.26 ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS)................................................. 1106
42.4.27 ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS)................................................. 1107
42.4.28 ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)............................................... 1108
42.4.29 ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS)................................................. 1109
42.4.30 ADC Status and Control Register 1 (SC1AA - SC1Z).................................................................................. 1110
42.4.31 ADC Data Result Registers (RAA - RZ)....................................................................................................... 1113
42.5 Functional description...................................................................................................................................................1115
42.5.1 Clock select and divide control......................................................................................................................1115
42.5.2 Voltage reference selection............................................................................................................................1116
42.5.3 Hardware trigger and channel selects............................................................................................................ 1116
42.5.4 Conversion control.........................................................................................................................................1117
42.5.5 Automatic compare function..........................................................................................................................1121
42.5.6 Calibration function....................................................................................................................................... 1122
42.5.7 User-defined offset function.......................................................................................................................... 1123
42.5.8 MCU Normal Stop mode operation............................................................................................................... 1124
Chapter 43
Comparator (CMP)
43.1 Chip-specific CMP information....................................................................................................................................1125
43.1.1 Instantiation information................................................................................................................................1125
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43.1.2 CMP input connections..................................................................................................................................1125
43.1.3 CMP external references................................................................................................................................1127
43.1.4 External window/sample input.......................................................................................................................1127
43.1.5 CMP trigger mode..........................................................................................................................................1127
43.1.6 Programming recommendation......................................................................................................................1128
43.1.7 S32K11X to S32K14X difference ................................................................................................................ 1128
43.2 Introduction...................................................................................................................................................................1129
43.3 Features.........................................................................................................................................................................1129
43.3.1 CMP features..................................................................................................................................................1129
43.3.2 8-bit DAC key features.................................................................................................................................. 1130
43.3.3 ANMUX key features.................................................................................................................................... 1130
43.4 CMP, DAC, and ANMUX diagram..............................................................................................................................1131
43.5 CMP block diagram...................................................................................................................................................... 1132
43.6 CMP pin descriptions....................................................................................................................................................1134
43.6.1 External pins.................................................................................................................................................. 1134
43.7 CMP functional modes................................................................................................................................................. 1135
43.7.1 Disabled mode (# 1).......................................................................................................................................1136
43.7.2 Continuous mode (#s 2A & 2B).................................................................................................................... 1137
43.7.3 Sampled, Non-Filtered mode (#s 3A & 3B).................................................................................................. 1137
43.7.4 Sampled, Filtered mode (#s 4A & 4B).......................................................................................................... 1139
43.7.5 Windowed mode (#s 5A & 5B)..................................................................................................................... 1141
43.7.6 Windowed/Resampled mode (# 6).................................................................................................................1143
43.7.7 Windowed/Filtered mode (#7)....................................................................................................................... 1144
43.8 Memory map/register definitions..................................................................................................................................1145
43.8.1 CMP Control Register 0 (CMP_C0)..............................................................................................................1145
43.8.2 CMP Control Register 1 (CMP_C1)..............................................................................................................1149
43.8.3 CMP Control Register 2 (CMP_C2)..............................................................................................................1152
43.9 CMP functional description.......................................................................................................................................... 1154
43.9.1 Initialization................................................................................................................................................... 1154
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43.9.2 Low-pass filter............................................................................................................................................... 1155
43.10 Interrupts.......................................................................................................................................................................1157
43.11 DMA support................................................................................................................................................................ 1157
43.12 DAC functional description.......................................................................................................................................... 1158
43.12.1 Digital-to-analog converter block diagram.................................................................................................... 1158
43.12.2 DAC resets..................................................................................................................................................... 1158
43.12.3 DAC clocks.................................................................................................................................................... 1159
43.12.4 DAC interrupts...............................................................................................................................................1159
43.13 Trigger mode.................................................................................................................................................................1159
Chapter 44
Programmable delay block (PDB)
44.1 Chip-specific PDB information.................................................................................................................................... 1163
44.1.1 Instantiation Information................................................................................................................................1163
44.1.2 PDB trigger interconnections with ADC and TRGMUX.............................................................................. 1164
44.1.3 Back-to-back acknowledgement connections................................................................................................1164
44.1.4 Pulse-Out Enable Register Implementation...................................................................................................1171
44.1.5 S32K11X to S32K14X difference ................................................................................................................ 1171
44.2 Introduction...................................................................................................................................................................1171
44.2.1 Features.......................................................................................................................................................... 1171
44.2.2 Implementation.............................................................................................................................................. 1172
44.2.3 Back-to-back acknowledgment connections..................................................................................................1173
44.2.4 Block diagram................................................................................................................................................ 1173
44.2.5 Modes of operation........................................................................................................................................ 1174
44.3 Memory map and register definition.............................................................................................................................1175
44.3.1 Status and Control register (PDB_SC)...........................................................................................................1177
44.3.2 Modulus register (PDB_MOD)......................................................................................................................1180
44.3.3 Counter register (PDB_CNT)........................................................................................................................ 1181
44.3.4 Interrupt Delay register (PDB_IDLY)........................................................................................................... 1181
44.3.5 Channel n Control register 1 (PDB_CHnC1)................................................................................................ 1182
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44.3.6 Channel n Status register (PDB_CHnS)........................................................................................................ 1183
44.3.7 Channel n Delay 0 register (PDB_CHnDLY0)..............................................................................................1183
44.3.8 Channel n Delay 1 register (PDB_CHnDLY1)..............................................................................................1184
44.3.9 Channel n Delay 2 register (PDB_CHnDLY2)..............................................................................................1185
44.3.10 Channel n Delay 3 register (PDB_CHnDLY3)..............................................................................................1185
44.3.11 Channel n Delay 4 register (PDB_CHnDLY4)..............................................................................................1186
44.3.12 Channel n Delay 5 register (PDB_CHnDLY5)..............................................................................................1187
44.3.13 Channel n Delay 6 register (PDB_CHnDLY6)..............................................................................................1187
44.3.14 Channel n Delay 7 register (PDB_CHnDLY7)..............................................................................................1188
44.3.15 Pulse-Out n Enable register (PDB_POEN)....................................................................................................1188
44.3.16 Pulse-Out n Delay register (PDB_POnDLY)................................................................................................ 1189
44.4 Functional description...................................................................................................................................................1189
44.4.1 PDB pre-trigger and trigger outputs...............................................................................................................1189
44.4.2 PDB trigger input source selection................................................................................................................ 1192
44.4.3 Pulse-Out's..................................................................................................................................................... 1192
44.4.4 Updating the delay registers...........................................................................................................................1193
44.4.5 Interrupts........................................................................................................................................................ 1195
44.4.6 DMA.............................................................................................................................................................. 1195
44.5 Application information................................................................................................................................................1195
44.5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................... 1195
Chapter 45
FlexTimer Module (FTM)
45.1 Chip-specific FTM information....................................................................................................................................1197
45.1.1 Instantiation Information................................................................................................................................1197
45.1.2 FTM Interrupts...............................................................................................................................................1198
45.1.3 FTM Fault Detection Inputs...........................................................................................................................1198
45.1.4 FTM Hardware Triggers and Synchronization.............................................................................................. 1200
45.1.5 FTM Input Capture Options...........................................................................................................................1202
45.1.6 FTM Hall sensor support............................................................................................................................... 1203
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45.1.7 FTM Modulation Implementation................................................................................................................. 1203
45.1.8 FTM Global Time Base................................................................................................................................. 1204
45.1.9 FTM BDM and debug halt mode...................................................................................................................1205
45.1.10 S32K11X to S32K14X difference ................................................................................................................ 1205
45.2 Introduction...................................................................................................................................................................1207
45.2.1 Features.......................................................................................................................................................... 1207
45.2.2 Modes of operation........................................................................................................................................ 1208
45.2.3 Block Diagram............................................................................................................................................... 1209
45.3 FTM signal descriptions............................................................................................................................................... 1211
45.4 Memory map and register definition.............................................................................................................................1211
45.4.1 Memory map.................................................................................................................................................. 1211
45.4.2 Register descriptions...................................................................................................................................... 1212
45.4.3 FTM register descriptions.............................................................................................................................. 1212
45.5 Functional Description..................................................................................................................................................1269
45.5.1 Clock source...................................................................................................................................................1269
45.5.2 Prescaler......................................................................................................................................................... 1269
45.5.3 Counter...........................................................................................................................................................1270
45.5.4 Channel Modes.............................................................................................................................................. 1276
45.5.5 Input Capture Mode....................................................................................................................................... 1278
45.5.6 Output Compare mode................................................................................................................................... 1283
45.5.7 Edge-Aligned PWM (EPWM) mode............................................................................................................. 1284
45.5.8 Center-Aligned PWM (CPWM) mode.......................................................................................................... 1286
45.5.9 Combine mode............................................................................................................................................... 1288
45.5.10 Modified Combine PWM Mode.................................................................................................................... 1296
45.5.11 Complementary Mode....................................................................................................................................1299
45.5.12 Registers updated from write buffers.............................................................................................................1301
45.5.13 PWM synchronization....................................................................................................................................1302
45.5.14 Inverting......................................................................................................................................................... 1318
45.5.15 Software Output Control Mode......................................................................................................................1319
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45.5.16 Deadtime insertion......................................................................................................................................... 1321
45.5.17 Output mask................................................................................................................................................... 1325
45.5.18 Fault Control.................................................................................................................................................. 1326
45.5.19 Polarity Control..............................................................................................................................................1330
45.5.20 Initialization................................................................................................................................................... 1331
45.5.21 Features Priority.............................................................................................................................................1331
45.5.22 External Trigger............................................................................................................................................. 1332
45.5.23 Initialization Trigger...................................................................................................................................... 1333
45.5.24 Capture Test Mode.........................................................................................................................................1335
45.5.25 DMA.............................................................................................................................................................. 1336
45.5.26 Dual Edge Capture Mode...............................................................................................................................1337
45.5.27 Quadrature Decoder Mode.............................................................................................................................1345
45.5.28 Debug mode................................................................................................................................................... 1351
45.5.29 Reload Points................................................................................................................................................. 1352
45.5.30 Global Load....................................................................................................................................................1355
45.5.31 Global time base (GTB).................................................................................................................................1356
45.5.32 Channel trigger output................................................................................................................................... 1357
45.5.33 External Control of Channels Output.............................................................................................................1358
45.5.34 Dithering........................................................................................................................................................ 1358
45.6 Reset Overview.............................................................................................................................................................1369
45.7 FTM Interrupts..............................................................................................................................................................1371
45.7.1 Timer Overflow Interrupt...............................................................................................................................1371
45.7.2 Reload Point Interrupt....................................................................................................................................1371
45.7.3 Channel (n) Interrupt......................................................................................................................................1371
45.7.4 Fault Interrupt................................................................................................................................................ 1371
45.8 Initialization Procedure.................................................................................................................................................1372
Chapter 46
Low Power Interrupt Timer (LPIT)
46.1 Chip-specific LPIT information....................................................................................................................................1375
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46.1.1 Instantiation Information................................................................................................................................1375
46.1.2 LPIT/DMA Periodic Trigger Assignments ...................................................................................................1375
46.1.3 LPIT input triggers ........................................................................................................................................1376
46.1.4 LPIT/ADC Trigger.........................................................................................................................................1376
46.1.5 S32K11X to S32K14X difference ................................................................................................................ 1377
46.2 Introduction...................................................................................................................................................................1378
46.2.1 Overview........................................................................................................................................................1378
46.2.2 Block Diagram............................................................................................................................................... 1379
46.3 Modes of operation....................................................................................................................................................... 1380
46.4 Memory Map and Registers..........................................................................................................................................1381
46.4.1 LPIT register descriptions..............................................................................................................................1381
46.5 Functional description...................................................................................................................................................1397
46.5.1 LPIT programming model............................................................................................................................. 1397
46.5.2 Initialization................................................................................................................................................... 1399
46.5.3 Timer Modes.................................................................................................................................................. 1400
46.5.4 Trigger Control for Timers............................................................................................................................ 1400
46.5.5 Channel Chaining...........................................................................................................................................1401
46.5.6 Detailed timing...............................................................................................................................................1402
Chapter 47
Low Power Timer (LPTMR)
47.1 Chip-specific LPTMR information...............................................................................................................................1415
47.1.1 Instantiation Information................................................................................................................................1415
47.1.2 LPTMR pulse counter input options..............................................................................................................1415
47.1.3 S32K11X to S32K14X difference ................................................................................................................ 1416
47.2 Introduction...................................................................................................................................................................1416
47.2.1 Features.......................................................................................................................................................... 1416
47.2.2 Modes of operation........................................................................................................................................ 1416
47.3 LPTMR signal descriptions.......................................................................................................................................... 1417
47.3.1 Detailed signal descriptions........................................................................................................................... 1417
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47.4 Memory map and register definition.............................................................................................................................1418
47.4.1 LPTMR register descriptions......................................................................................................................... 1418
47.5 Functional description...................................................................................................................................................1423
47.5.1 LPTMR power and reset................................................................................................................................ 1423
47.5.2 LPTMR clocking............................................................................................................................................1424
47.5.3 LPTMR prescaler/glitch filter........................................................................................................................1424
47.5.4 LPTMR counter............................................................................................................................................. 1425
47.5.5 LPTMR compare............................................................................................................................................1426
47.5.6 LPTMR interrupt............................................................................................................................................1426
47.5.7 LPTMR hardware trigger...............................................................................................................................1427
Chapter 48
Real Time Clock (RTC)
48.1 Chip-specific RTC information.................................................................................................................................... 1429
48.1.1 RTC instantiation........................................................................................................................................... 1429
48.1.2 RTC interrupts ...............................................................................................................................................1429
48.1.3 Software recommendation............................................................................................................................. 1429
48.1.4 Multiple trigger ............................................................................................................................................. 1429
48.1.5 S32K11X to S32K14X difference ................................................................................................................ 1430
48.2 Introduction...................................................................................................................................................................1430
48.2.1 Features.......................................................................................................................................................... 1430
48.2.2 Modes of operation........................................................................................................................................ 1430
48.2.3 RTC signal descriptions................................................................................................................................. 1430
48.3 Register definition.........................................................................................................................................................1431
48.3.1 RTC register descriptions...............................................................................................................................1431
48.4 Functional description...................................................................................................................................................1442
48.4.1 Power, clocking, and reset............................................................................................................................. 1442
48.4.2 Time counter.................................................................................................................................................. 1443
48.4.3 Compensation.................................................................................................................................................1443
48.4.4 Time alarm..................................................................................................................................................... 1444
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48.4.5 Update mode.................................................................................................................................................. 1445
48.4.6 Register lock.................................................................................................................................................. 1445
48.4.7 Interrupt..........................................................................................................................................................1445
Chapter 49
Low Power Serial Peripheral Interface (LPSPI)
49.1 Chip-specific LPSPI information..................................................................................................................................1447
49.1.1 Instantiation Information................................................................................................................................1447
49.2 Introduction...................................................................................................................................................................1448
49.2.1 Features.......................................................................................................................................................... 1450
49.2.2 Block Diagram............................................................................................................................................... 1450
49.2.3 Modes of operation........................................................................................................................................ 1451
49.2.4 Signal Descriptions........................................................................................................................................ 1451
49.2.5 Wiring options................................................................................................................................................1452
49.3 Memory Map and Registers..........................................................................................................................................1454
49.3.1 LPSPI register descriptions............................................................................................................................1454
49.4 Functional description...................................................................................................................................................1477
49.4.1 Clocking and resets........................................................................................................................................ 1477
49.4.2 Master Mode.................................................................................................................................................. 1478
49.4.3 Slave Mode.................................................................................................................................................... 1484
49.4.4 Interrupts and DMA Requests........................................................................................................................1486
49.4.5 Peripheral Triggers.........................................................................................................................................1487
Chapter 50
Low Power Inter-Integrated Circuit (LPI2C)
50.1 Chip-specific LPI2C information................................................................................................................................. 1489
50.1.1 Instantiation information................................................................................................................................1489
50.2 Introduction...................................................................................................................................................................1490
50.2.1 Features.......................................................................................................................................................... 1491
50.2.2 Block Diagram............................................................................................................................................... 1493
50.2.3 Modes of operation........................................................................................................................................ 1493
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50.2.4 Signal Descriptions........................................................................................................................................ 1493
50.2.5 Wiring options................................................................................................................................................1494
50.3 Memory Map and Registers..........................................................................................................................................1495
50.3.1 LPI2C register descriptions............................................................................................................................1496
50.4 Functional description...................................................................................................................................................1534
50.4.1 Clocking and Resets.......................................................................................................................................1534
50.4.2 Master Mode.................................................................................................................................................. 1535
50.4.3 Slave Mode.................................................................................................................................................... 1541
50.4.4 Interrupts and DMA Requests........................................................................................................................1543
50.4.5 Peripheral Triggers.........................................................................................................................................1545
Chapter 51
Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
51.1 Chip-specific LPUART information.............................................................................................................................1547
51.1.1 Instantiation Information................................................................................................................................1547
51.2 Introduction...................................................................................................................................................................1548
51.2.1 Features.......................................................................................................................................................... 1548
51.2.2 Modes of operation........................................................................................................................................ 1549
51.2.3 Signal Descriptions........................................................................................................................................ 1549
51.2.4 Block diagram................................................................................................................................................ 1549
51.3 Register definition.........................................................................................................................................................1551
51.3.1 LPUART register descriptions.......................................................................................................................1551
51.4 Functional description...................................................................................................................................................1577
51.4.1 Clocking and Resets.......................................................................................................................................1577
51.4.2 Baud rate generation...................................................................................................................................... 1577
51.4.3 Transmitter functional description................................................................................................................. 1578
51.4.4 Receiver functional description..................................................................................................................... 1582
51.4.5 Additional LPUART functions...................................................................................................................... 1588
51.4.6 Infrared interface............................................................................................................................................1590
51.4.7 Interrupts and status flags.............................................................................................................................. 1591
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51.4.8 Peripheral Triggers.........................................................................................................................................1592
Chapter 52
Flexible I/O (FlexIO)
52.1 Chip-specific FlexIO information.................................................................................................................................1595
52.1.1 FlexIO Configuration.....................................................................................................................................1595
52.2 Introduction...................................................................................................................................................................1595
52.2.1 Overview........................................................................................................................................................1595
52.2.2 Features.......................................................................................................................................................... 1596
52.2.3 Block Diagram............................................................................................................................................... 1596
52.2.4 Modes of operation........................................................................................................................................ 1597
52.2.5 FlexIO Signal Descriptions............................................................................................................................1597
52.3 Memory Map and Registers..........................................................................................................................................1598
52.3.1 FLEXIO register descriptions........................................................................................................................ 1598
52.4 Functional description...................................................................................................................................................1622
52.4.1 Clocking and Resets.......................................................................................................................................1622
52.4.2 Shifter operation.............................................................................................................................................1623
52.4.3 Timer Operation.............................................................................................................................................1625
52.4.4 Pin operation.................................................................................................................................................. 1629
52.4.5 Interrupts and DMA Requests........................................................................................................................1630
52.4.6 Peripheral Triggers.........................................................................................................................................1630
52.5 Application Information................................................................................................................................................1631
52.5.1 UART Transmit............................................................................................................................................. 1631
52.5.2 UART Receive...............................................................................................................................................1632
52.5.3 SPI Master......................................................................................................................................................1634
52.5.4 SPI Slave........................................................................................................................................................ 1636
52.5.5 I2C Master......................................................................................................................................................1637
52.5.6 I2S Master...................................................................................................................................................... 1639
52.5.7 I2S Slave........................................................................................................................................................ 1641
Chapter 53
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FlexCAN
53.1 Chip-specific FlexCAN information.............................................................................................................................1643
53.1.1 Instantiation information................................................................................................................................1643
53.1.2 Reset value of MDIS bit.................................................................................................................................1644
53.1.3 FlexCAN external time tick .......................................................................................................................... 1644
53.1.4 FlexCAN Interrupts........................................................................................................................................1644
53.1.5 FlexCAN Operation in Low Power Modes....................................................................................................1645
53.1.6 FlexCAN oscillator clock...............................................................................................................................1645
53.1.7 Supported baud rate ...................................................................................................................................... 1645
53.1.8 Requirements for entering FlexCAN modes: Freeze, Disable, Stop............................................................. 1645
53.2 Introduction...................................................................................................................................................................1647
53.2.1 Overview........................................................................................................................................................1648
53.2.2 FlexCAN module features............................................................................................................................. 1649
53.2.3 Modes of operation........................................................................................................................................ 1650
53.3 FlexCAN signal descriptions........................................................................................................................................ 1652
53.3.1 CAN Rx .........................................................................................................................................................1652
53.3.2 CAN Tx .........................................................................................................................................................1653
53.4 Memory map/register definition................................................................................................................................... 1653
53.4.1 FlexCAN memory mapping...........................................................................................................................1653
53.4.2 CAN register descriptions..............................................................................................................................1654
53.4.3 Message buffer structure................................................................................................................................1725
53.4.4 FlexCAN memory partition for CAN FD...................................................................................................... 1732
53.4.5 FlexCAN message buffer memory map.........................................................................................................1733
53.4.6 Rx FIFO structure.......................................................................................................................................... 1735
53.5 Functional description...................................................................................................................................................1738
53.5.1 Transmit process............................................................................................................................................ 1738
53.5.2 Arbitration process.........................................................................................................................................1740
53.5.3 Receive process..............................................................................................................................................1743
53.5.4 Matching process........................................................................................................................................... 1745
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53.5.5 Receive process under Pretended Networking mode.....................................................................................1750
53.5.6 Move process................................................................................................................................................. 1754
53.5.7 Data coherence...............................................................................................................................................1756
53.5.8 Rx FIFO......................................................................................................................................................... 1759
53.5.9 CAN protocol related features....................................................................................................................... 1762
53.5.10 Clock domains and restrictions...................................................................................................................... 1782
53.5.11 Modes of operation details.............................................................................................................................1786
53.5.12 Interrupts........................................................................................................................................................ 1789
53.5.13 Bus interface.................................................................................................................................................. 1791
53.6 Initialization/application information........................................................................................................................... 1792
53.6.1 FlexCAN initialization sequence................................................................................................................... 1792
Chapter 54
Synchronous Audio Interface (SAI)
54.1 Chip-specific SAI information .....................................................................................................................................1795
54.1.1 SAI configuration...........................................................................................................................................1795
54.1.2 Chip-specific register information................................................................................................................. 1796
54.2 Introduction...................................................................................................................................................................1797
54.2.1 Features.......................................................................................................................................................... 1797
54.2.2 Block diagram................................................................................................................................................ 1797
54.2.3 Modes of operation........................................................................................................................................ 1798
54.3 External signals.............................................................................................................................................................1799
54.4 Memory map and register definition.............................................................................................................................1799
54.4.1 I2S register descriptions.................................................................................................................................1799
54.5 Functional description...................................................................................................................................................1832
54.5.1 SAI clocking.................................................................................................................................................. 1832
54.5.2 SAI resets....................................................................................................................................................... 1834
54.5.3 Synchronous modes....................................................................................................................................... 1835
54.5.4 Frame sync configuration...............................................................................................................................1836
54.5.5 Data FIFO...................................................................................................................................................... 1836
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54.5.6 Word mask register........................................................................................................................................ 1840
54.5.7 Interrupts and DMA requests.........................................................................................................................1841
Chapter 55
Ethernet MAC (ENET)
55.1 Chip-specific ENET information..................................................................................................................................1845
55.1.1 Software guideline during ENET operation...................................................................................................1845
55.2 Introduction...................................................................................................................................................................1845
55.3 Overview.......................................................................................................................................................................1846
55.3.1 Features.......................................................................................................................................................... 1846
55.3.2 Block diagram................................................................................................................................................ 1849
55.4 External signal description............................................................................................................................................1849
55.5 Memory map/register definition................................................................................................................................... 1851
55.5.1 Interrupt Event Register (ENET_EIR)...........................................................................................................1856
55.5.2 Interrupt Mask Register (ENET_EIMR)........................................................................................................1859
55.5.3 Receive Descriptor Active Register (ENET_RDAR)....................................................................................1862
55.5.4 Transmit Descriptor Active Register (ENET_TDAR)...................................................................................1863
55.5.5 Ethernet Control Register (ENET_ECR).......................................................................................................1864
55.5.6 MII Management Frame Register (ENET_MMFR)...................................................................................... 1866
55.5.7 MII Speed Control Register (ENET_MSCR)................................................................................................ 1866
55.5.8 MIB Control Register (ENET_MIBC).......................................................................................................... 1869
55.5.9 Receive Control Register (ENET_RCR)....................................................................................................... 1870
55.5.10 Transmit Control Register (ENET_TCR)...................................................................................................... 1873
55.5.11 Physical Address Lower Register (ENET_PALR)........................................................................................ 1875
55.5.12 Physical Address Upper Register (ENET_PAUR)........................................................................................ 1875
55.5.13 Opcode/Pause Duration Register (ENET_OPD)........................................................................................... 1876
55.5.14 Descriptor Individual Upper Address Register (ENET_IAUR).................................................................... 1876
55.5.15 Descriptor Individual Lower Address Register (ENET_IALR).................................................................... 1877
55.5.16 Descriptor Group Upper Address Register (ENET_GAUR).........................................................................1877
55.5.17 Descriptor Group Lower Address Register (ENET_GALR).........................................................................1878
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55.5.18 Transmit FIFO Watermark Register (ENET_TFWR)................................................................................... 1878
55.5.19 Receive Descriptor Ring Start Register (ENET_RDSR)...............................................................................1879
55.5.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR).................................................................. 1880
55.5.21 Maximum Receive Buffer Size Register (ENET_MRBR)............................................................................ 1881
55.5.22 Receive FIFO Section Full Threshold (ENET_RSFL).................................................................................. 1882
55.5.23 Receive FIFO Section Empty Threshold (ENET_RSEM)............................................................................ 1882
55.5.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)............................................................................ 1883
55.5.25 Receive FIFO Almost Full Threshold (ENET_RAFL)..................................................................................1883
55.5.26 Transmit FIFO Section Empty Threshold (ENET_TSEM)........................................................................... 1884
55.5.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM)...........................................................................1884
55.5.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)................................................................................ 1885
55.5.29 Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................... 1885
55.5.30 Frame Truncation Length (ENET_FTRL).....................................................................................................1886
55.5.31 Transmit Accelerator Function Configuration (ENET_TACC).................................................................... 1886
55.5.32 Receive Accelerator Function Configuration (ENET_RACC)......................................................................1887
55.5.33 Reserved Statistic Register (ENET_RMON_T_DROP)................................................................................1888
55.5.34 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS)............................................................ 1889
55.5.35 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)........................................................1889
55.5.36 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)........................................................1890
55.5.37 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN)............................ 1890
55.5.38 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)............1890
55.5.39 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)..........1891
55.5.40 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG).....................1891
55.5.41 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)........ 1892
55.5.42 Tx Collision Count Statistic Register (ENET_RMON_T_COL).................................................................. 1892
55.5.43 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................... 1892
55.5.44 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127)............................................ 1893
55.5.45 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)........................................ 1893
55.5.46 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)........................................ 1894
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55.5.47 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................... 1894
55.5.48 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047)................................ 1895
55.5.49 Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048).......................... 1895
55.5.50 Tx Octets Statistic Register (ENET_RMON_T_OCTETS).......................................................................... 1895
55.5.51 Reserved Statistic Register (ENET_IEEE_T_DROP)...................................................................................1896
55.5.52 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK)................................................ 1896
55.5.53 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................... 1897
55.5.54 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).........................1897
55.5.55 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)....................................1897
55.5.56 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL).................................. 1898
55.5.57 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL).....................1898
55.5.58 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR)....................1899
55.5.59 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)....................... 1899
55.5.60 Reserved Statistic Register (ENET_IEEE_T_SQE)...................................................................................... 1899
55.5.61 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC)...............................1900
55.5.62 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK)...........1900
55.5.63 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS)............................................................ 1901
55.5.64 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)....................................................... 1901
55.5.65 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)....................................................... 1901
55.5.66 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)............................1902
55.5.67 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENET_RMON_R_UNDERSIZE)................................................................................................................1902
55.5.68 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE)...1903
55.5.69 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................... 1903
55.5.70 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)....... 1903
55.5.71 Reserved Statistic Register (ENET_RMON_R_RESVD_0).........................................................................1904
55.5.72 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64)...................................................................1904
55.5.73 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)........................................... 1905
55.5.74 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)....................................... 1905
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55.5.75 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)....................................... 1905
55.5.76 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................... 1906
55.5.77 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................... 1906
55.5.78 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)........................... 1907
55.5.79 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)..........................................................................1907
55.5.80 Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP)................................................. 1907
55.5.81 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................... 1908
55.5.82 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC).............................................. 1908
55.5.83 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN)................................ 1909
55.5.84 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)..........................................1909
55.5.85 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC)...................................1909
55.5.86 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK).........1910
55.5.87 Adjustable Timer Control Register (ENET_ATCR)..................................................................................... 1910
55.5.88 Timer Value Register (ENET_ATVR).......................................................................................................... 1912
55.5.89 Timer Offset Register (ENET_ATOFF)........................................................................................................ 1913
55.5.90 Timer Period Register (ENET_ATPER)........................................................................................................1913
55.5.91 Timer Correction Register (ENET_ATCOR)................................................................................................ 1914
55.5.92 Time-Stamping Clock Period Register (ENET_ATINC).............................................................................. 1914
55.5.93 Timestamp of Last Transmitted Frame (ENET_ATSTMP).......................................................................... 1915
55.5.94 Timer Global Status Register (ENET_TGSR)...............................................................................................1915
55.5.95 Timer Control Status Register (ENET_TCSRn)............................................................................................1916
55.5.96 Timer Compare Capture Register (ENET_TCCRn)......................................................................................1917
55.6 Functional description...................................................................................................................................................1918
55.6.1 Ethernet MAC frame formats........................................................................................................................ 1918
55.6.2 IP and higher layers frame format..................................................................................................................1921
55.6.3 IEEE 1588 message formats.......................................................................................................................... 1925
55.6.4 MAC receive.................................................................................................................................................. 1929
55.6.5 MAC transmit................................................................................................................................................ 1935
55.6.6 Full-duplex flow control operation................................................................................................................ 1939
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55.6.7 Magic packet detection.................................................................................................................................. 1941
55.6.8 IP accelerator functions..................................................................................................................................1942
55.6.9 Resets and stop controls.................................................................................................................................1946
55.6.10 IEEE 1588 functions...................................................................................................................................... 1949
55.6.11 FIFO thresholds..............................................................................................................................................1953
55.6.12 Loopback options...........................................................................................................................................1956
55.6.13 Legacy buffer descriptors...............................................................................................................................1957
55.6.14 Enhanced buffer descriptors...........................................................................................................................1958
55.6.15 Client FIFO application interface.................................................................................................................. 1964
55.6.16 FIFO protection..............................................................................................................................................1967
55.6.17 Reference clock..............................................................................................................................................1969
55.6.18 PHY management interface........................................................................................................................... 1970
55.6.19 Ethernet interfaces..........................................................................................................................................1973
Chapter 56
Debug
56.1 Introduction...................................................................................................................................................................1979
56.2 CM4 and CM0  ROM table......................................................................................................................................... 1982
56.3 Debug port.................................................................................................................................................................... 1983
56.3.1 JTAG-to-SWD change sequence................................................................................................................... 1984
56.4 Debug port pin descriptions..........................................................................................................................................1985
56.5 System TAP connection................................................................................................................................................1985
56.5.1 IR codes..........................................................................................................................................................1985
56.6 MDM-AP status and control registers.......................................................................................................................... 1986
56.6.1 MDM-AP Control Register............................................................................................................................1987
56.6.2 MDM-AP Status Register.............................................................................................................................. 1988
56.7 Debug resets..................................................................................................................................................................1989
56.8 AHB-AP........................................................................................................................................................................1990
56.9 ITM............................................................................................................................................................................... 1990
56.10 Core trace connectivity................................................................................................................................................. 1991
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56.11 TPIU..............................................................................................................................................................................1991
56.12 DWT............................................................................................................................................................................. 1992
56.13 MTB .............................................................................................................................................................................1992
56.14 Debug in low-power modes..........................................................................................................................................1993
56.14.1 Debug module state in low-power modes......................................................................................................1993
56.15 Debug and security....................................................................................................................................................... 1994
Chapter 57
JTAG Controller (JTAGC)
57.1 Chip-specific JTAGC information................................................................................................................................1995
57.2 Introduction...................................................................................................................................................................1995
57.2.1 Block diagram................................................................................................................................................ 1995
57.2.2 Features.......................................................................................................................................................... 1996
57.2.3 Modes of operation........................................................................................................................................ 1996
57.3 External signal description............................................................................................................................................1998
57.3.1 Test clock input (TCK).................................................................................................................................. 1998
57.3.2 Test data input (TDI)......................................................................................................................................1998
57.3.3 Test data output (TDO).................................................................................................................................. 1998
57.3.4 Test mode select (TMS).................................................................................................................................1999
57.4 Register description...................................................................................................................................................... 1999
57.4.1 Instruction register......................................................................................................................................... 1999
57.4.2 Bypass register............................................................................................................................................... 1999
57.4.3 Device identification register......................................................................................................................... 2000
57.4.4 Boundary scan register...................................................................................................................................2000
57.5 Functional description...................................................................................................................................................2001
57.5.1 JTAGC reset configuration............................................................................................................................ 2001
57.5.2 IEEE 1149.1-2001 (JTAG) TAP....................................................................................................................2001
57.5.3 TAP controller state machine.........................................................................................................................2001
57.5.4 JTAGC block instructions..............................................................................................................................2004
57.5.5 Boundary scan................................................................................................................................................2007
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57.6 Initialization/application information........................................................................................................................... 2007