DDR4 SDRAM Registered DIMM Design Specification.pdf

DDR4 SDRAM Registered DIMM Design Specification 

【实例截图】

【核心代码】

Table of Contents
1 Product Description .............................................................................................. 5
2 Environmental Requirements .............................................................................. 6
3 Connector Pinout and Signal Description .......................................................... 7
4 Power Details....................................................................................................... 12
4.1 DIMM Voltage Requirements.................................................................................. 12
4.2 VDDSPD .................................................................................................................. 12
4.3 Recommended Power Sequence........................................................................... 12
4.4 Feed Through Voltage (VFT).................................................................................. 14
4.5 12 V Power............................................................................................................... 14
5 Component Details.............................................................................................. 15
5.1 Component Types and Placement ........................................................................ 18
5.2 Decoupling Guidelines ........................................................................................... 18
6 DIMM Design Details ........................................................................................... 19
6.1 Signal Groups.......................................................................................................... 19
6.2 General Net Structure Routing Rules.................................................................... 19
6.2.1 Clock, Control, and Address/Command Groups ...........................................................21
6.2.2 PreRegister ADD/CMD and CTRL ................................................................................21
6.2.3 PreRegister CK .............................................................................................................21
6.2.4 PostRegister ADD/CMD ................................................................................................22
6.2.5 PostRegister CTRL Group ............................................................................................23
6.2.6 DQ Group ......................................................................................................................23
6.3 Modified Rules for RDIMM Designs at 2666 Mbps and Higher and 16 Gb......... 24
6.4 Plane Referencing................................................................................................... 25
6.5 Address Mirroring................................................................................................... 25
6.6 DQ Mapping to Support CRC................................................................................. 27
6.7 DIMM Routing Space Constraints ......................................................................... 31
6.8 DIMM Physical Requirements................................................................................ 32
6.8.1 Via Size .........................................................................................................................32
6.8.2 Component Pad Sizes and Geometry...........................................................................32
6.8.3 SDRAM Package Size ..................................................................................................32
6.8.4 Clock Termination .........................................................................................................32
6.8.5 DQ Resistor...................................................................................................................33
6.9 RDIMM Configuration ............................................................................................. 33
6.9.1 Control Wiring................................................................................................................33
6.9.2 AVDD Filter Circuit, Placement and Wiring ...................................................................35
6.9.3 ZQ Calibration Wiring ....................................................................................................35
6.9.4 ALERT_n Circuit Wiring ................................................................................................35
6.9.5 TEN Pin Wiring..............................................................................................................36
6.10 SPD-TSE Selection, Wiring and Placement.......................................................... 36
7 Serial Presence Detect (Pending Separate Ballot)........................................... 37
7.1 Serial Presence Detect Definition.......................................................................... 37
8 Product Label ...................................................................................................... 40
9 JEDEC Process ................................................................................................... 45
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DDR4 SDRAM Registered DIMM Design Specification JEDEC Standard No. 21C, Release 29
Revision 1.50 Page 4.20.28-3
List of Tables
Table 1 — DDR4 Product Family Attributes .................................................................... 5
Table 2 — Environmental Parameters ............................................................................. 6
Table 3 — Pin Definition.................................................................................................... 7
Table 4 — Input/Output Functional Description ............................................................. 8
Table 5 — DDR4 288 Pin RDIMM Pin Wiring Assignments.......................................... 10
Table 6 — DDR4 RDIMM DC Operating Voltage1,2,3 - 1.2 V operation....................... 12
Table 7 — DDR4 x4 SDRAM DIMM Pad Array ............................................................... 16
Table 8 — DDR4 x8 SDRAM DIMM Pad Array ............................................................... 17
Table 9 — RDIMM Decoupling Capacitor Guidelines ................................................... 18
Table 10 — Simulation Conditions................................................................................. 20
Table 11 — Example PreRegister ADD/CMD and CTRL Definition ............................. 21
Table 12 — Example PreRegister CK Length................................................................ 22
Table 13 — Example PostRegister ADD/CMD Definition ............................................. 23
Table 14 — Example DQ Definition ................................................................................ 24
Table 15 — Plane Referencing........................................................................................ 25
Table 16 — DIMM Wiring Definition for Address Mirroring.......................................... 26
Table 17 — SPD DQ Nibble Map for CRC ...................................................................... 27
Table 18 — Nibble/Byte DQ Map Patterns for CRC....................................................... 28
Table 19 — Example of DQ Mapping for CRC............................................................... 30
Table 20 — Routing Space Constraints......................................................................... 31
Table 21 — SPD Address Map........................................................................................ 37
Table 22 — Block 0: Base Configuration and SDRAM Parameters............................. 37
Table 23 — Preproduction Registration Definition....................................................... 42
Downloaded by James Zhang (pat12155@gmail.com) on Feb 11, 2020, 7:48 pm PST
Wistron
JEDEC Standard No. 21C, Release 29 DDR4 SDRAM Registered DIMM Design Specification
Page 4.20.28-4 Revision 1.50
List of Figures
Figure 1 — Graphical View of Recommended Power Up Sequence...........................13
Figure 2 — Graphical View of Recommended Power Down Sequence......................13
Figure 3 — DIMM Ball Patterns for DDR4 SDRAM Components .................................15
Figure 4 — Example RDIMM Topologies .......................................................................19
Figure 5 — Example PreRegister ADD/CMD and CTRL Diagram ................................21
Figure 6 — Example PreRegister CK Diagram..............................................................22
Figure 7 — Example PostRegister ADD/CMD Diagram ................................................23
Figure 8 — Example DQ Net Structure ..........................................................................24
Figure 9 — Example of DQ Wiring with Mapping for CRC ...........................................29
Figure 10 — DDR4 SRx8 Control Wiring........................................................................33
Figure 11 — DDR4 SRx4 Control Wiring........................................................................33
Figure 12 — DDR4 DRx8 Control Wiring .......................................................................34
Figure 13 — DDR4 2R/4R/8R/16R (planar/3DS) Control Wiring ...................................34
Figure 14 — DDR4 2R VLP (DDP) Control Wiring .........................................................34
Figure 15 — AVDD Filter Circuit Wiring.........................................................................35
Figure 16 — Example Wiring of the ALERT_n Function ..............................................36
Figure 17 — Block Diagram: SPD-TSE and DDR4RCD01 ............................................36