IEEE Standard for Verilog.pdf

【实例截图】

【核心代码】

Contents
1. Overview.................................................................................................................................................. 1
1.1 Scope.............................................................................................................................................. 1
1.2 Conventions used in this standard ................................................................................................. 1
1.3 Syntactic description...................................................................................................................... 2
1.4 Use of color in this standard .......................................................................................................... 3
1.5 Contents of this standard................................................................................................................ 3
1.6 Deprecated clauses......................................................................................................................... 5
1.7 Header file listings ......................................................................................................................... 5
1.8 Examples........................................................................................................................................ 5
1.9 Prerequisites................................................................................................................................... 5
2. Normative references............................................................................................................................... 6
3. Lexical conventions ................................................................................................................................. 8
3.1 Lexical tokens ................................................................................................................................ 8
3.2 White space.................................................................................................................................... 8
3.3 Comments ...................................................................................................................................... 8
3.4 Operators........................................................................................................................................ 8
3.5 Numbers......................................................................................................................................... 9
3.5.1 Integer constants ............................................................................................................ 10
3.5.2 Real constants ................................................................................................................ 12
3.5.3 Conversion ..................................................................................................................... 12
3.6 Strings .......................................................................................................................................... 12
3.6.1 String variable declaration ............................................................................................. 13
3.6.2 String manipulation........................................................................................................ 13
3.6.3 Special characters in strings........................................................................................... 13
3.7 Identifiers, keywords, and system names .................................................................................... 14
3.7.1 Escaped identifiers......................................................................................................... 14
3.7.2 Keywords ....................................................................................................................... 15
3.7.3 System tasks and functions ............................................................................................ 15
3.7.4 Compiler directives........................................................................................................ 15
3.8 Attributes ..................................................................................................................................... 16
3.8.1 Examples........................................................................................................................ 16
3.8.2 Syntax ............................................................................................................................ 18
4. Data types .............................................................................................................................................. 21
4.1 Value set ...................................................................................................................................... 21
4.2 Nets and variables........................................................................................................................ 21
4.2.1 Net declarations ............................................................................................................. 21
4.2.2 Variable declarations ..................................................................................................... 23
4.3 Vectors ......................................................................................................................................... 24
4.3.1 Specifying vectors.......................................................................................................... 24
4.3.2 Vector net accessibility.................................................................................................. 24
4.4 Strengths ...................................................................................................................................... 25
4.4.1 Charge strength .............................................................................................................. 25
4.4.2 Drive strength ................................................................................................................ 25
4.5 Implicit declarations .................................................................................................................... 25
4.6 Net types ...................................................................................................................................... 26
4.6.1 Wire and tri nets............................................................................................................. 26
4.6.2 Wired nets ...................................................................................................................... 27
4.6.3 Trireg net........................................................................................................................ 28
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
viii Copyright © 2006 IEEE. All rights reserved.
4.6.4 Tri0 and tri1 nets............................................................................................................ 31
4.6.5 Unresolved nets.............................................................................................................. 31
4.6.6 Supply nets..................................................................................................................... 32
4.7 Regs ............................................................................................................................................. 32
4.8 Integers, reals, times, and realtimes............................................................................................. 32
4.8.1 Operators and real numbers ........................................................................................... 33
4.8.2 Conversion ..................................................................................................................... 33
4.9 Arrays........................................................................................................................................... 34
4.9.1 Net arrays....................................................................................................................... 34
4.9.2 reg and variable arrays................................................................................................... 34
4.9.3 Memories ....................................................................................................................... 35
4.10 Parameters.................................................................................................................................... 35
4.10.1 Module parameters ........................................................................................................ 36
4.10.2 Local parameters (localparam) ...................................................................................... 37
4.10.3 Specify parameters......................................................................................................... 38
4.11 Name spaces ................................................................................................................................ 39
5. Expressions ............................................................................................................................................ 41
5.1 Operators...................................................................................................................................... 41
5.1.1 Operators with real operands ......................................................................................... 42
5.1.2 Operator precedence ...................................................................................................... 43
5.1.3 Using integer numbers in expressions ........................................................................... 44
5.1.4 Expression evaluation order........................................................................................... 45
5.1.5 Arithmetic operators ...................................................................................................... 45
5.1.6 Arithmetic expressions with regs and integers .............................................................. 47
5.1.7 Relational operators ....................................................................................................... 48
5.1.8 Equality operators .......................................................................................................... 49
5.1.9 Logical operators ........................................................................................................... 49
5.1.10 Bitwise operators ........................................................................................................... 50
5.1.11 Reduction operators ....................................................................................................... 51
5.1.12 Shift operators................................................................................................................ 53
5.1.13 Conditional operator ...................................................................................................... 53
5.1.14 Concatenations............................................................................................................... 54
5.2 Operands ...................................................................................................................................... 55
5.2.1 Vector bit-select and part-select addressing .................................................................. 56
5.2.2 Array and memory addressing....................................................................................... 57
5.2.3 Strings ............................................................................................................................ 58
5.3 Minimum, typical, and maximum delay expressions .................................................................. 61
5.4 Expression bit lengths.................................................................................................................. 62
5.4.1 Rules for expression bit lengths..................................................................................... 62
5.4.2 Example of expression bit-length problem.................................................................... 63
5.4.3 Example of self-determined expressions ....................................................................... 64
5.5 Signed expressions....................................................................................................................... 64
5.5.1 Rules for expression types ............................................................................................. 65
5.5.2 Steps for evaluating an expression................................................................................. 65
5.5.3 Steps for evaluating an assignment................................................................................ 66
5.5.4 Handling X and Z in signed expressions ....................................................................... 66
5.6 Assignments and truncation......................................................................................................... 66
6. Assignments........................................................................................................................................... 68
6.1 Continuous assignments .............................................................................................................. 68
6.1.1 The net declaration assignment...................................................................................... 69
6.1.2 The continuous assignment statement ........................................................................... 69
6.1.3 Delays ............................................................................................................................ 71
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
Copyright © 2006 IEEE. All rights reserved. ix
6.1.4 Strength.......................................................................................................................... 71
6.2 Procedural assignments................................................................................................................ 72
6.2.1 Variable declaration assignment.................................................................................... 72
6.2.2 Variable declaration syntax ........................................................................................... 73
7. Gate- and switch-level modeling ........................................................................................................... 74
7.1 Gate and switch declaration syntax ............................................................................................. 74
7.1.1 The gate type specification ............................................................................................ 76
7.1.2 The drive strength specification..................................................................................... 76
7.1.3 The delay specification .................................................................................................. 77
7.1.4 The primitive instance identifier.................................................................................... 77
7.1.5 The range specification.................................................................................................. 77
7.1.6 Primitive instance connection list .................................................................................. 78
7.2 and, nand, nor, or, xor, and xnor gates......................................................................................... 80
7.3 buf and not gates .......................................................................................................................... 81
7.4 bufif1, bufif0, notif1, and notif0 gates......................................................................................... 82
7.5 MOS switches .............................................................................................................................. 83
7.6 Bidirectional pass switches.......................................................................................................... 84
7.7 CMOS switches ........................................................................................................................... 85
7.8 pullup and pulldown sources ....................................................................................................... 86
7.9 Logic strength modeling .............................................................................................................. 86
7.10 Strengths and values of combined signals ................................................................................... 88
7.10.1 Combined signals of unambiguous strength.................................................................. 88
7.10.2 Ambiguous strengths: sources and combinations.......................................................... 89
7.10.3 Ambiguous strength signals and unambiguous signals ................................................. 94
7.10.4 Wired logic net types ..................................................................................................... 98
7.11 Strength reduction by nonresistive devices ............................................................................... 100
7.12 Strength reduction by resistive devices ..................................................................................... 100
7.13 Strengths of net types................................................................................................................. 100
7.13.1 tri0 and tri1 net strengths ............................................................................................. 100
7.13.2 trireg strength............................................................................................................... 100
7.13.3 supply0 and supply1 net strengths ............................................................................... 101
7.14 Gate and net delays .................................................................................................................... 101
7.14.1 min:typ:max delays...................................................................................................... 102
7.14.2 trireg net charge decay................................................................................................. 103
8. User-defined primitives (UDPs) .......................................................................................................... 105
8.1 UDP definition........................................................................................................................... 105
8.1.1 UDP header.................................................................................................................. 107
8.1.2 UDP port declarations.................................................................................................. 107
8.1.3 Sequential UDP initial statement................................................................................. 107
8.1.4 UDP state table ............................................................................................................ 107
8.1.5 Z values in UDP........................................................................................................... 108
8.1.6 Summary of symbols ................................................................................................... 108
8.2 Combinational UDPs ................................................................................................................. 109
8.3 Level-sensitive sequential UDPs ............................................................................................... 110
8.4 Edge-sensitive sequential UDPs ................................................................................................ 110
8.5 Sequential UDP initialization .................................................................................................... 111
8.6 UDP instances............................................................................................................................ 113
8.7 Mixing level-sensitive and edge-sensitive descriptions............................................................. 114
8.8 Level-sensitive dominance ........................................................................................................ 115
9. Behavioral modeling............................................................................................................................ 116
9.1 Behavioral model overview ....................................................................................................... 116
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
x Copyright © 2006 IEEE. All rights reserved.
9.2 Procedural assignments.............................................................................................................. 117
9.2.1 Blocking procedural assignments ................................................................................ 117
9.2.2 The nonblocking procedural assignment ..................................................................... 118
9.3 Procedural continuous assignments........................................................................................... 122
9.3.1 The assign and deassign procedural statements........................................................... 123
9.3.2 The force and release procedural statements............................................................... 124
9.4 Conditional statement ................................................................................................................ 125
9.4.1 If-else-if construct........................................................................................................ 126
9.5 Case statement ........................................................................................................................... 127
9.5.1 Case statement with do-not-cares ................................................................................ 128
9.5.2 Constant expression in case statement......................................................................... 129
9.6 Looping statements .................................................................................................................... 130
9.7 Procedural timing controls......................................................................................................... 131
9.7.1 Delay control................................................................................................................ 132
9.7.2 Event control................................................................................................................ 132
9.7.3 Named events............................................................................................................... 133
9.7.4 Event or operator ......................................................................................................... 134
9.7.5 Implicit event_expression list ...................................................................................... 134
9.7.6 Level-sensitive event control ....................................................................................... 136
9.7.7 Intra-assignment timing controls ................................................................................. 136
9.8 Block statements ........................................................................................................................ 139
9.8.1 Sequential blocks ......................................................................................................... 140
9.8.2 Parallel blocks.............................................................................................................. 141
9.8.3 Block names................................................................................................................. 141
9.8.4 Start and finish times ................................................................................................... 142
9.9 Structured procedures ................................................................................................................ 143
9.9.1 Initial construct ............................................................................................................ 143
9.9.2 Always construct.......................................................................................................... 144
10. Tasks and functions ............................................................................................................................. 145
10.1 Distinctions between tasks and functions .................................................................................. 145
10.2 Tasks and task enabling ............................................................................................................. 145
10.2.1 Task declarations ......................................................................................................... 146
10.2.2 Task enabling and argument passing ........................................................................... 147
10.2.3 Task memory usage and concurrent activation............................................................ 149
10.3 Disabling of named blocks and tasks......................................................................................... 150
10.4 Functions and function calling................................................................................................... 152
10.4.1 Function declarations................................................................................................... 152
10.4.2 Returning a value from a function ............................................................................... 154
10.4.3 Calling a function......................................................................................................... 155
10.4.4 Function rules .............................................................................................................. 155
10.4.5 Use of constant functions............................................................................................. 156
11. Scheduling semantics........................................................................................................................... 158
11.1 Execution of a model ................................................................................................................. 158
11.2 Event simulation ........................................................................................................................ 158
11.3 The stratified event queue.......................................................................................................... 158
11.4 Verilog simulation reference model .......................................................................................... 159
11.4.1 Determinism................................................................................................................. 160
11.4.2 Nondeterminism........................................................................................................... 160
11.5 Race conditions.......................................................................................................................... 160
11.6 Scheduling implication of assignments ..................................................................................... 161
11.6.1 Continuous assignment ................................................................................................ 161
11.6.2 Procedural continuous assignment............................................................................... 161
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
Copyright © 2006 IEEE. All rights reserved. xi
11.6.3 Blocking assignment.................................................................................................... 161
11.6.4 Nonblocking assignment.............................................................................................. 161
11.6.5 Switch (transistor) processing...................................................................................... 161
11.6.6 Port connections........................................................................................................... 162
11.6.7 Functions and tasks...................................................................................................... 162
12. Hierarchical structures......................................................................................................................... 163
12.1 Modules ..................................................................................................................................... 163
12.1.1 Top-level modules ....................................................................................................... 165
12.1.2 Module instantiation .................................................................................................... 165
12.2 Overriding module parameter values......................................................................................... 167
12.2.1 defparam statement ...................................................................................................... 168
12.2.2 Module instance parameter value assignment ............................................................. 170
12.2.3 Parameter dependence ................................................................................................. 173
12.3 Ports ........................................................................................................................................... 173
12.3.1 Port definition .............................................................................................................. 173
12.3.2 List of ports.................................................................................................................. 174
12.3.3 Port declarations .......................................................................................................... 174
12.3.4 List of ports declarations.............................................................................................. 176
12.3.5 Connecting module instance ports by ordered list....................................................... 176
12.3.6 Connecting module instance ports by name ................................................................ 177
12.3.7 Real numbers in port connections................................................................................ 178
12.3.8 Connecting dissimilar ports ......................................................................................... 178
12.3.9 Port connection rules ................................................................................................... 179
12.3.10 Net types resulting from dissimilar port connections .................................................. 179
12.3.11 Connecting signed values via ports ............................................................................. 181
12.4 Generate constructs.................................................................................................................... 181
12.4.1 Loop generate constructs ............................................................................................. 183
12.4.2 Conditional generate constructs................................................................................... 186
12.4.3 External names for unnamed generate blocks ............................................................. 190
12.5 Hierarchical names ................................................................................................................... 191
12.6 Upwards name referencing ........................................................................................................ 193
12.7 Scope rules ................................................................................................................................ 195
12.8 Elaboration................................................................................................................................. 197
12.8.1 Order of elaboration..................................................................................................... 197
12.8.2 Early resolution of hierarchical names ........................................................................ 197
13. Configuring the contents of a design ................................................................................................... 199
13.1 Introduction................................................................................................................................ 199
13.1.1 Library notation ........................................................................................................... 199
13.1.2 Basic configuration elements....................................................................................... 200
13.2 Libraries ..................................................................................................................................... 200
13.2.1 Specifying libraries—the library map file ................................................................... 200
13.2.2 Using multiple library map files .................................................................................. 202
13.2.3 Mapping source files to libraries ................................................................................. 202
13.3 Configurations ........................................................................................................................... 202
13.3.1 Basic configuration syntax........................................................................................... 202
13.3.2 Hierarchical configurations.......................................................................................... 205
13.4 Using libraries and configs ........................................................................................................ 205
13.4.1 Precompiling in a single-pass use model..................................................................... 205
13.4.2 Elaboration-time compiling in a single-pass use model .............................................. 206
13.4.3 Precompiling using a separate compilation tool .......................................................... 206
13.4.4 Command line considerations...................................................................................... 206
13.5 Configuration examples............................................................................................................. 206
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
xii Copyright © 2006 IEEE. All rights reserved.
13.5.1 Default configuration from library map file ................................................................ 207
13.5.2 Using default clause..................................................................................................... 207
13.5.3 Using cell clause .......................................................................................................... 207
13.5.4 Using instance clause................................................................................................... 208
13.5.5 Using hierarchical config............................................................................................. 208
13.6 Displaying library binding information ..................................................................................... 208
13.7 Library mapping examples ........................................................................................................ 209
13.7.1 Using the command line to control library searching.................................................. 209
13.7.2 File path specification examples.................................................................................. 209
13.7.3 Resolving multiple path specifications ........................................................................ 209
14. Specify blocks...................................................................................................................................... 211
14.1 Specify block declaration........................................................................................................... 211
14.2 Module path declarations........................................................................................................... 212
14.2.1 Module path restrictions .............................................................................................. 212
14.2.2 Simple module paths.................................................................................................... 213
14.2.3 Edge-sensitive paths .................................................................................................... 214
14.2.4 State-dependent paths .................................................................................................. 215
14.2.5 Full connection and parallel connection paths............................................................. 219
14.2.6 Declaring multiple module paths in a single statement ............................................... 220
14.2.7 Module path polarity.................................................................................................... 220
14.3 Assigning delays to module paths ............................................................................................. 222
14.3.1 Specifying transition delays on module paths ............................................................. 222
14.3.2 Specifying x transition delays...................................................................................... 224
14.3.3 Delay selection............................................................................................................. 225
14.4 Mixing module path delays and distributed delays ................................................................... 225
14.5 Driving wired logic.................................................................................................................... 226
14.6 Detailed control of pulse filtering behavior............................................................................... 228
14.6.1 Specify block control of pulse limit values ................................................................. 229
14.6.2 Global control of pulse limit values............................................................................. 230
14.6.3 SDF annotation of pulse limit values........................................................................... 230
14.6.4 Detailed pulse control capabilities............................................................................... 230
15. Timing checks...................................................................................................................................... 237
15.1 Overview.................................................................................................................................... 237
15.2 Timing checks using a stability window.................................................................................... 240
15.2.1 $setup ........................................................................................................................... 241
15.2.2 $hold ............................................................................................................................ 242
15.2.3 $setuphold.................................................................................................................... 243
15.2.4 $removal ...................................................................................................................... 245
15.2.5 $recovery ..................................................................................................................... 246
15.2.6 $recrem ........................................................................................................................ 247
15.3 Timing checks for clock and control signals ............................................................................. 248
15.3.1 $skew ........................................................................................................................... 249
15.3.2 $timeskew .................................................................................................................... 250
15.3.3 $fullskew...................................................................................................................... 252
15.3.4 $width .......................................................................................................................... 255
15.3.5 $period ......................................................................................................................... 256
15.3.6 $nochange .................................................................................................................... 257
15.4 Edge-control specifiers .............................................................................................................. 258
15.5 Notifiers: user-defined responses to timing violations .............................................................. 259
15.5.1 Requirements for accurate simulation ......................................................................... 261
15.5.2 Conditions in negative timing checks.......................................................................... 263
15.5.3 Notifiers in negative timing checks ............................................................................. 264
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
Copyright © 2006 IEEE. All rights reserved. xiii
15.5.4 Option behavior ........................................................................................................... 264
15.6 Enabling timing checks with conditioned events ...................................................................... 265
15.7 Vector signals in timing checks ................................................................................................. 266
15.8 Negative timing checks.............................................................................................................. 266
16. Backannotation using the standard delay format (SDF)...................................................................... 269
16.1 The SDF annotator..................................................................................................................... 269
16.2 Mapping of SDF constructs to Verilog...................................................................................... 269
16.2.1 Mapping of SDF delay constructs to Verilog declarations.......................................... 269
16.2.2 Mapping of SDF timing check constructs to Verilog .................................................. 271
16.2.3 SDF annotation of specparams .................................................................................... 272
16.2.4 SDF annotation of interconnect delays........................................................................ 273
16.3 Multiple annotations .................................................................................................................. 274
16.4 Multiple SDF files ..................................................................................................................... 275
16.5 Pulse limit annotation ................................................................................................................ 275
16.6 SDF to Verilog delay value mapping ........................................................................................ 276
17. System tasks and functions .................................................................................................................. 277
17.1 Display system tasks.................................................................................................................. 278
17.1.1 The display and write tasks.......................................................................................... 278
17.1.2 Strobed monitoring ...................................................................................................... 285
17.1.3 Continuous monitoring ................................................................................................ 286
17.2 File input-output system tasks and functions............................................................................. 286
17.2.1 Opening and closing files ............................................................................................ 287
17.2.2 File output system tasks............................................................................................... 288
17.2.3 Formatting data to a string ........................................................................................... 289
17.2.4 Reading data from a file............................................................................................... 290
17.2.5 File positioning ............................................................................................................ 294
17.2.6 Flushing output ............................................................................................................ 295
17.2.7 I/O error status ............................................................................................................. 295
17.2.8 Detecting EOF ............................................................................................................. 295
17.2.9 Loading memory data from a file ................................................................................ 296
17.2.10 Loading timing data from an SDF file......................................................................... 297
17.3 Timescale system tasks.............................................................................................................. 298
17.3.1 $printtimescale............................................................................................................. 299
17.3.2 $timeformat.................................................................................................................. 300
17.4 Simulation control system tasks ................................................................................................ 302
17.4.1 $finish .......................................................................................................................... 302
17.4.2 $stop............................................................................................................................. 302
17.5 Programmable logic array (PLA) modeling system tasks ......................................................... 303
17.5.1 Array types................................................................................................................... 303
17.5.2 Array logic types.......................................................................................................... 304
17.5.3 Logic array personality declaration and loading.......................................................... 304
17.5.4 Logic array personality formats................................................................................... 304
17.6 Stochastic analysis tasks ............................................................................................................ 307
17.6.1 $q_initialize ................................................................................................................. 307
17.6.2 $q_add.......................................................................................................................... 307
17.6.3 $q_remove ................................................................................................................... 307
17.6.4 $q_full.......................................................................................................................... 308
17.6.5 $q_exam....................................................................................................................... 308
17.6.6 Status codes.................................................................................................................. 308
17.7 Simulation time system functions.............................................................................................. 309
17.7.1 $time ............................................................................................................................ 309
17.7.2 $stime........................................................................................................................... 309
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
xiv Copyright © 2006 IEEE. All rights reserved.
17.7.3 $realtime ...................................................................................................................... 310
17.8 Conversion functions ................................................................................................................. 310
17.9 Probabilistic distribution functions............................................................................................ 311
17.9.1 $random function......................................................................................................... 311
17.9.2 $dist_ functions............................................................................................................ 312
17.9.3 Algorithm for probabilistic distribution functions....................................................... 313
17.10 Command line input................................................................................................................... 320
17.10.1 $test$plusargs (string).................................................................................................. 320
17.10.2 $value$plusargs (user_string, variable) ....................................................................... 321
17.11 Math functions ........................................................................................................................... 323
17.11.1 Integer math functions ................................................................................................. 323
17.11.2 Real math functions ..................................................................................................... 323
18. Value change dump (VCD) files ......................................................................................................... 325
18.1 Creating four-state VCD file...................................................................................................... 325
18.1.1 Specifying name of dump file ($dumpfile).................................................................. 325
18.1.2 Specifying variables to be dumped ($dumpvars) ........................................................ 326
18.1.3 Stopping and resuming the dump ($dumpoff/$dumpon)............................................. 327
18.1.4 Generating a checkpoint ($dumpall)............................................................................ 328
18.1.5 Limiting size of dump file ($dumplimit) ..................................................................... 328
18.1.6 Reading dump file during simulation ($dumpflush).................................................... 328
18.2 Format of four-state VCD file ................................................................................................... 329
18.2.1 Syntax of four-state VCD file...................................................................................... 330
18.2.2 Formats of variable values........................................................................................... 331
18.2.3 Description of keyword commands ............................................................................. 332
18.2.4 Four-state VCD file format example ........................................................................... 337
18.3 Creating extended VCD file ...................................................................................................... 338
18.3.1 Specifying dump file name and ports to be dumped ($dumpports)............................. 338
18.3.2 Stopping and resuming the dump ($dumpportsoff/$dumpportson)............................. 339
18.3.3 Generating a checkpoint ($dumpportsall).................................................................... 340
18.3.4 Limiting size of dump file ($dumpportslimit)............................................................. 340
18.3.5 Reading dump file during simulation ($dumpportsflush)............................................ 341
18.3.6 Description of keyword commands ............................................................................. 341
18.3.7 General rules for extended VCD system tasks ............................................................ 341
18.4 Format of extended VCD file .................................................................................................... 342
18.4.1 Syntax of extended VCD file....................................................................................... 342
18.4.2 Extended VCD node information ................................................................................ 344
18.4.3 Value changes .............................................................................................................. 346
18.4.4 Extended VCD file format example ............................................................................ 347
19. Compiler directives.............................................................................................................................. 349
19.1 `celldefine and `endcelldefine.................................................................................................... 349
19.2 `default_nettype ......................................................................................................................... 349
19.3 `define and `undef...................................................................................................................... 350
19.3.1 `define .......................................................................................................................... 350
19.3.2 `undef ........................................................................................................................... 352
19.4 `ifdef, `else, `elsif, `endif, `ifndef .............................................................................................. 352
19.5 `include ...................................................................................................................................... 356
19.6 `resetall....................................................................................................................................... 356
19.7 `line ............................................................................................................................................ 357
19.8 `timescale ................................................................................................................................... 358
19.9 `unconnected_drive and `nounconnected_drive ........................................................................ 360
19.10 `pragma ...................................................................................................................................... 360
19.10.1 Standard pragmas......................................................................................................... 361
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
Copyright © 2006 IEEE. All rights reserved. xv
19.11 `begin_keywords, `end_keywords ............................................................................................. 361
20. Programming language interface (PLI) overview ............................................................................... 366
20.1 PLI purpose and history............................................................................................................. 366
20.2 User-defined system task/function names ................................................................................. 367
20.3 User-defined system task/function types ................................................................................... 367
20.4 Overriding built-in system task/function names........................................................................ 367
20.5 User-supplied PLI applications.................................................................................................. 367
20.6 PLI mechanism .......................................................................................................................... 368
20.7 User-defined system task/function arguments........................................................................... 368
20.8 PLI include files......................................................................................................................... 368
21. PLI TF and ACC interface mechanism (deprecated)........................................................................... 369
22. Using ACC routines (deprecated)........................................................................................................ 370
23. ACC routine definitions (deprecated).................................................................................................. 371
24. Using TF routines (deprecated) ........................................................................................................... 372
25. TF routine definitions (deprecated) ..................................................................................................... 373
26. Using Verilog procedural interface (VPI) routines.............................................................................. 374
26.1 VPI system tasks and functions ................................................................................................. 374
26.1.1 sizetf VPI application routine ...................................................................................... 374
26.1.2 compiletf VPI application routine................................................................................ 374
26.1.3 calltf VPI application routine....................................................................................... 375
26.1.4 Arguments to sizetf, compiletf, and calltf application routines................................... 375
26.2 VPI mechanism.......................................................................................................................... 375
26.2.1 VPI callbacks ............................................................................................................... 375
26.2.2 VPI access to Verilog HDL objects and simulation objects........................................ 376
26.2.3 Error handling .............................................................................................................. 376
26.2.4 Function availability .................................................................................................... 376
26.2.5 Traversing expressions ................................................................................................ 377
26.3 VPI object classifications........................................................................................................... 377
26.3.1 Accessing object relationships and properties............................................................. 378
26.3.2 Object type properties.................................................................................................. 379
26.3.3 Object file and line properties...................................................................................... 380
26.3.4 Delays and values ........................................................................................................ 380
26.3.5 Object protection properties......................................................................................... 381
26.4 List of VPI routines by functional category............................................................................... 381
26.5 Key to data model diagrams ...................................................................................................... 383
26.5.1 Diagram key for objects and classes ........................................................................... 384
26.5.2 Diagram key for accessing properties.......................................................................... 384
26.5.3 Diagram key for traversing relationships .................................................................... 385
26.6 Object data model diagrams ...................................................................................................... 386
26.6.1 Module ......................................................................................................................... 387
26.6.2 Instance arrays ............................................................................................................. 388
26.6.3 Scope............................................................................................................................ 389
26.6.4 IO declaration .............................................................................................................. 389
26.6.5 Ports ............................................................................................................................. 390
26.6.6 Nets and net arrays....................................................................................................... 391
26.6.7 Regs and reg arrays...................................................................................................... 393
26.6.8 Variables ...................................................................................................................... 395
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
xvi Copyright © 2006 IEEE. All rights reserved.
26.6.9 Memory........................................................................................................................ 396
26.6.10 Object range................................................................................................................. 396
26.6.11 Named event ................................................................................................................ 397
26.6.12 Parameter, specparam .................................................................................................. 398
26.6.13 Primitive, prim term..................................................................................................... 399
26.6.14 UDP ............................................................................................................................. 400
26.6.15 Module path, path term................................................................................................ 401
26.6.16 Intermodule path .......................................................................................................... 401
26.6.17 Timing check ............................................................................................................... 402
26.6.18 Task, function declaration............................................................................................ 402
26.6.19 Task/function call ........................................................................................................ 403
26.6.20 Frames.......................................................................................................................... 404
26.6.21 Delay terminals ............................................................................................................ 405
26.6.22 Net drivers and loads ................................................................................................... 405
26.6.23 Reg drivers and loads................................................................................................... 406
26.6.24 Continuous assignment ................................................................................................ 406
26.6.25 Simple expressions ...................................................................................................... 407
26.6.26 Expressions .................................................................................................................. 408
26.6.27 Process, block, statement, event statement ................................................................. 409
26.6.28 Assignment .................................................................................................................. 410
26.6.29 Delay control................................................................................................................ 410
26.6.30 Event control................................................................................................................ 410
26.6.31 Repeat control .............................................................................................................. 411
26.6.32 While, repeat, wait ....................................................................................................... 411
26.6.33 For................................................................................................................................ 411
26.6.34 Forever ......................................................................................................................... 411
26.6.35 If, if-else....................................................................................................................... 412
26.6.36 Case.............................................................................................................................. 412
26.6.37 Assign statement, deassign, force, release .................................................................. 413
26.6.38 Disable ......................................................................................................................... 413
26.6.39 Callback ....................................................................................................................... 414
26.6.40 Time queue .................................................................................................................. 414
26.6.41 Active time format ....................................................................................................... 414
26.6.42 Attributes ..................................................................................................................... 415
26.6.43 Iterator.......................................................................................................................... 416
26.6.44 Generates ..................................................................................................................... 417
27. VPI routine definitions......................................................................................................................... 418
27.1 vpi_chk_error() .......................................................................................................................... 418
27.2 vpi_compare_objects()............................................................................................................... 420
27.3 vpi_control() .............................................................................................................................. 420
27.4 vpi_flush().................................................................................................................................. 421
27.5 vpi_free_object()........................................................................................................................ 421
27.6 vpi_get()..................................................................................................................................... 422
27.7 vpi_get_cb_info()....................................................................................................................... 422
27.8 vpi_get_data() ............................................................................................................................ 423
27.9 vpi_get_delays()......................................................................................................................... 424
27.10 vpi_get_str()............................................................................................................................... 426
27.11 vpi_get_systf_info()................................................................................................................... 427
27.12 vpi_get_time()............................................................................................................................ 428
27.13 vpi_get_userdata() ..................................................................................................................... 429
27.14 vpi_get_value() .......................................................................................................................... 429
27.15 vpi_get_vlog_info() ................................................................................................................... 435
27.16 vpi_handle() ............................................................................................................................... 436
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
Copyright © 2006 IEEE. All rights reserved. xvii
27.17 vpi_handle_by_index() .............................................................................................................. 437
27.18 vpi_handle_by_multi_index().................................................................................................... 438
27.19 vpi_handle_by_name() .............................................................................................................. 438
27.20 vpi_handle_multi()..................................................................................................................... 439
27.21 vpi_iterate()................................................................................................................................ 439
27.22 vpi_mcd_close()......................................................................................................................... 440
27.23 vpi_mcd_flush()......................................................................................................................... 441
27.24 vpi_mcd_name() ........................................................................................................................ 441
27.25 vpi_mcd_open() ......................................................................................................................... 442
27.26 vpi_mcd_printf()........................................................................................................................ 443
27.27 vpi_mcd_vprintf()...................................................................................................................... 444
27.28 vpi_printf()................................................................................................................................. 444
27.29 vpi_put_data()............................................................................................................................ 445
27.30 vpi_put_delays() ........................................................................................................................ 447
27.31 vpi_put_userdata() ..................................................................................................................... 450
27.32 vpi_put_value().......................................................................................................................... 450
27.33 vpi_register_cb()........................................................................................................................ 453
27.33.1 Simulation event callbacks .......................................................................................... 454
27.33.2 Simulation time callbacks............................................................................................ 458
27.33.3 Simulator action or feature callbacks........................................................................... 460
27.34 vpi_register_systf() .................................................................................................................... 461
27.34.1 System task/function callbacks.................................................................................... 462
27.34.2 Initializing VPI system task/function callbacks........................................................... 463
27.34.3 Registering multiple system tasks and functions......................................................... 464
27.35 vpi_remove_cb()........................................................................................................................ 465
27.36 vpi_scan()................................................................................................................................... 465
27.37 vpi_vprintf()............................................................................................................................... 466
28. Protected envelopes ............................................................................................................................. 467
28.1 General....................................................................................................................................... 467
28.2 Processing protected envelopes ................................................................................................. 467
28.2.1 Encryption.................................................................................................................... 468
28.2.2 Decryption ................................................................................................................... 469
28.3 Protect pragma directives........................................................................................................... 469
28.4 Protect pragma keywords........................................................................................................... 471
28.4.1 begin............................................................................................................................. 471
28.4.2 end................................................................................................................................ 471
28.4.3 begin_protected............................................................................................................ 471
28.4.4 end_protected............................................................................................................... 472
28.4.5 author ........................................................................................................................... 472
28.4.6 author_info................................................................................................................... 473
28.4.7 encrypt_agent............................................................................................................... 473
28.4.8 encrypt_agent_info ...................................................................................................... 473
28.4.9 encoding....................................................................................................................... 474
28.4.10 data_keyowner ............................................................................................................. 475
28.4.11 data_method................................................................................................................. 475
28.4.12 data_keyname .............................................................................................................. 476
28.4.13 data_public_key ........................................................................................................... 477
28.4.14 data_decrypt_key ......................................................................................................... 477
28.4.15 data_block.................................................................................................................... 478
28.4.16 digest_keyowner .......................................................................................................... 478
28.4.17 digest_key_method ...................................................................................................... 478
28.4.18 digest_keyname ........................................................................................................... 479
28.4.19 digest_public_key ........................................................................................................ 479
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
xviii Copyright © 2006 IEEE. All rights reserved.
28.4.20 digest_decrypt_key ...................................................................................................... 480
28.4.21 digest_method.............................................................................................................. 480
28.4.22 digest_block ................................................................................................................. 481
28.4.23 key_keyowner.............................................................................................................. 482
28.4.24 key_method.................................................................................................................. 482
28.4.25 key_keyname ............................................................................................................... 482
28.4.26 key_public_key............................................................................................................ 483
28.4.27 key_block..................................................................................................................... 483
28.4.28 decrypt_license ............................................................................................................ 484
28.4.29 runtime_license............................................................................................................ 484
28.4.30 comment....................................................................................................................... 485
28.4.31 reset.............................................................................................................................. 485
28.4.32 viewport ....................................................................................................................... 486
Annex A (normative) Formal syntax definition .......................................................................................... 487
A.1 Source text ....................................................................................................................... 487
A.1.1 Library source text ............................................................................................. 487
A.1.2 Verilog source text ............................................................................................. 487
A.1.3 Module parameters and ports ............................................................................. 487
A.1.4 Module items...................................................................................................... 488
A.1.5 Configuration source text ................................................................................... 489
A.2 Declarations ..................................................................................................................... 489
A.2.1 Declaration types................................................................................................ 489
A.2.2 Declaration data types ........................................................................................ 490
A.2.3 Declaration lists.................................................................................................. 491
A.2.4 Declaration assignments..................................................................................... 491
A.2.5 Declaration ranges.............................................................................................. 492
A.2.6 Function declarations ......................................................................................... 492
A.2.7 Task declarations................................................................................................ 492
A.2.8 Block item declarations...................................................................................... 493
A.3 Primitive instances........................................................................................................... 493
A.3.1 Primitive instantiation and instances.................................................................. 493
A.3.2 Primitive strengths.............................................................................................. 494
A.3.3 Primitive terminals ............................................................................................. 494
A.3.4 Primitive gate and switch types.......................................................................... 494
A.4 Module instantiation and generate construct ................................................................... 495
A.4.1 Module instantiation........................................................................................... 495
A.4.2 Generate construct.............................................................................................. 495
A.5 UDP declaration and instantiation ................................................................................... 496
A.5.1 UDP declaration ................................................................................................. 496
A.5.2 UDP ports........................................................................................................... 496
A.5.3 UDP body........................................................................................................... 496
A.5.4 UDP instantiation ............................................................................................... 497
A.6 Behavioral statements ...................................................................................................... 497
A.6.1 Continuous assignment statements..................................................................... 497
A.6.2 Procedural blocks and assignments.................................................................... 497
A.6.3 Parallel and sequential blocks ............................................................................ 497
A.6.4 Statements .......................................................................................................... 498
A.6.5 Timing control statements.................................................................................. 498
A.6.6 Conditional statements ....................................................................................... 499
A.6.7 Case statements .................................................................................................. 499
A.6.8 Looping statements ............................................................................................ 499
A.6.9 Task enable statements....................................................................................... 499
A.7 Specify section................................................................................................................. 500
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
Copyright © 2006 IEEE. All rights reserved. xix
A.7.1 Specify block declaration ................................................................................... 500
A.7.2 Specify path declarations ................................................................................... 500
A.7.3 Specify block terminals...................................................................................... 500
A.7.4 Specify path delays............................................................................................. 500
A.7.5 System timing checks......................................................................................... 502
A.8 Expressions ...................................................................................................................... 504
A.8.1 Concatenations ................................................................................................... 504
A.8.2 Function calls ..................................................................................................... 504
A.8.3 Expressions......................................................................................................... 504
A.8.4 Primaries............................................................................................................. 505
A.8.5 Expression left-side values................................................................................. 506
A.8.6 Operators ............................................................................................................ 506
A.8.7 Numbers ............................................................................................................. 506
A.8.8 Strings................................................................................................................. 507
A.9 General............................................................................................................................. 507
A.9.1 Attributes............................................................................................................ 507
A.9.2 Comments........................................................................................................... 508
A.9.3 Identifiers ........................................................................................................... 508
A.9.4 White space ........................................................................................................ 509
Annex B (normative) List of keywords ....................................................................................................... 510
Annex C (informative) System tasks and functions .................................................................................... 511
C.1 $countdrivers ................................................................................................................... 511
C.2 $getpattern ....................................................................................................................... 512
C.3 $input ............................................................................................................................... 513
C.4 $key and $nokey .............................................................................................................. 513
C.5 $list................................................................................................................................... 513
C.6 $log and $nolog ............................................................................................................... 514
C.7 $reset, $reset_count, and $reset_value ............................................................................ 514
C.8 $save, $restart, and $incsave............................................................................................ 515
C.9 $scale ............................................................................................................................... 516
C.10 $scope .............................................................................................................................. 516
C.11 $showscopes .................................................................................................................... 516
C.12 $showvars ........................................................................................................................ 516
C.13 $sreadmemb and $sreadmemh......................................................................................... 517
Annex D (informative) Compiler directives................................................................................................ 518
D.1 `default_decay_time......................................................................................................... 518
D.2 `default_trireg_strength ................................................................................................... 518
D.3 `delay_mode_distributed ................................................................................................. 519
D.4 `delay_mode_path............................................................................................................ 519
D.5 `delay_mode_unit ............................................................................................................ 519
D.6 `delay_mode_zero............................................................................................................ 519
Annex E (normative) acc_user.h (deprecated)............................................................................................. 520
Annex F (normative) veriuser.h (deprecated).............................................................................................. 521
Annex G (normative) vpi_user.h ................................................................................................................. 522
Annex H (informative) Encryption/decryption flow ................................................................................... 537
H.1 Tool vendor secret key encryption system ...................................................................... 537
H.1.1 Encryption input................................................................................................. 537
Authorized licensed use limited to: University of Science and Technology of China. Downloaded on September 20,2012 at 02:33:32 UTC from IEEE Xplore. Restrictions apply. 
xx Copyright © 2006 IEEE. All rights reserved.
H.1.2 Encryption output............................................................................................... 538
H.2 IP author secret key encryption system ........................................................................... 538
H.2.1 Encryption input................................................................................................. 538
H.2.2 Encryption output............................................................................................... 539
H.3 Digital envelopes ............................................................................................................. 539
H.3.1 Encryption input................................................................................................. 540
H.3.2 Encryption output............................................................................................... 541
Annex I (informative) Bibliography ............................................................................................................ 542
Index ............................................................................................................................................................ 543