JESD84-B451.pdf

【实例截图】

【核心代码】

EMBEDDED MULTIMEDIA CARD (e•MMC), ELECTRICAL STANDARD 4.51
Contents
Page
1 Scope .........................................................................................................................................1
2 Normative reference..................................................................................................................1
3 Terms and definitions................................................................................................................1
4 System Features.........................................................................................................................5
5 e•MMC Device and System ......................................................................................................7
5.1 e•MMC System Overview.........................................................................................................7
5.2 Memory Addressing..................................................................................................................7
5.3 e•MMC Device Overview.........................................................................................................8
5.3.1 Bus Protocol .............................................................................................................................. 9
5.4 Bus Speed Modes....................................................................................................................15
5.4.1 HS200 Bus Speed Mode.......................................................................................................... 15
5.4.2 HS200 System Block Diagram................................................................................................ 15
5.4.3 Adjustable Sampling Host....................................................................................................... 16
6 e•MMC functional description ................................................................................................17
6.1 e•MMC Overview ...................................................................................................................17
6.2 Partition Management .............................................................................................................18
6.2.1 General .................................................................................................................................... 18
6.2.2 Command restrictions.............................................................................................................. 20
6.2.3 Extended Partitions Attribute .................................................................................................. 20
6.2.4 Configure partitions................................................................................................................. 20
6.2.5 Access partitions...................................................................................................................... 23
6.3 Boot operation mode ...............................................................................................................24
6.3.1 Device reset to Pre-idle state ................................................................................................... 24
6.3.2 Boot partition........................................................................................................................... 25
6.3.3 Boot operation ......................................................................................................................... 26
6.3.4 Alternative boot operation....................................................................................................... 28
6.3.5 Access to boot partition........................................................................................................... 31
6.3.6 Boot bus width and data access configuration ........................................................................ 32
6.3.7 Boot Partition Write Protection............................................................................................... 32
6.4 Device identification mode .....................................................................................................34
JEDEC Standard No. 84-B451
6.4.1 Device reset............................................................................................................................. 34
6.4.2 Access mode validation (higher than 2GB of densities) ......................................................... 35
6.4.3 From busy to ready.................................................................................................................. 36
6.4.4 Device identification process .................................................................................................. 36
6.5 Interrupt mode .........................................................................................................................37
6.6 Data transfer mode ..................................................................................................................39
6.6.1 Command sets and extended settings...................................................................................... 41
6.6.2 High-speed modes selection.................................................................................................... 42
6.6.3 “High-speed” mode selection.................................................................................................. 42
6.6.4 “HS200” timing mode selection.............................................................................................. 42
6.6.5 Power class selection............................................................................................................... 44
6.6.6 Bus testing procedure .............................................................................................................. 44
6.6.7 Bus Sampling Tuning Concept................................................................................................ 46
6.6.7.1 Sampling Tuning Sequence for HS200 ................................................................................... 47
6.6.8 Bus width selection ................................................................................................................. 49
6.6.9 Data read ................................................................................................................................. 49
6.6.9.1 Block read ............................................................................................................................... 49
6.6.10 Data write ................................................................................................................................ 51
6.6.10.1 Block write ............................................................................................................................ 51
6.6.11 Erase........................................................................................................................................ 53
6.6.12 TRIM....................................................................................................................................... 55
6.6.13 Sanitize .................................................................................................................................... 56
6.6.14 Discard .................................................................................................................................... 57
6.6.15 Secure Erase ............................................................................................................................ 58
6.6.16 Secure Trim............................................................................................................................. 59
6.6.17 Write protect management ...................................................................................................... 60
6.6.18 Extended Security Protocols Pass Through Commands.......................................................... 62
6.6.18.1 PROTOCOL_RD - CMD53 .................................................................................................. 62
6.6.18.2 PROTOCOL_WR - CMD54 ................................................................................................. 62
6.6.18.3 Security Protocol Type .......................................................................................................... 62
6.6.18.4 Security Protocol Information ............................................................................................... 63
6.6.18.5 Error handling........................................................................................................................ 63
6.6.19 Device lock/unlock operation.................................................................................................. 63
6.6.20 Application-specific commands.............................................................................................. 67
6.6.21 Sleep (CMD5) ......................................................................................................................... 67
6.6.22 Replay Protected Memory Block ............................................................................................ 68
JEDEC Standard No. 84-B451
-iii6.6.22.1 The Data Frame for Replay Protected Memory Block Access ............................................... 68
6.6.22.2 Memory Map of the Replay Protected Memory Block ........................................................... 71
6.6.22.3 Message Authentication Code Calculation ............................................................................. 71
6.6.22.4 Accesses to the Replay Protected Memory Block................................................................... 72
6.6.22.4.1 Programming of the Authentication Key ................................................................................73
6.6.22.4.2 Reading of the Counter Value .................................................................................................74
6.6.22.4.3 Authenticated Data Write........................................................................................................75
6.6.22.4.4 Authenticated Data Read.........................................................................................................77
6.6.23 Dual Data Rate mode selection ............................................................................................... 78
6.6.24 Dual Data Rate mode operation .............................................................................................. 78
6.6.25 Background Operations........................................................................................................... 79
6.6.26 High Priority Interrupt (HPI)................................................................................................... 79
6.6.27 Context Management .............................................................................................................. 81
6.6.27.1 Context configuration.............................................................................................................. 81
6.6.27.2 Context direction ..................................................................................................................... 82
6.6.27.3 Large-Unit ............................................................................................................................... 82
6.6.27.4 Context Writing Interruption................................................................................................... 82
6.6.27.5 Large-Unit Multipliers ............................................................................................................ 83
6.6.28 Data Tag Mechanism............................................................................................................... 84
6.6.29 Packed Commands.................................................................................................................. 84
6.6.29.1 Packed Command Header ....................................................................................................... 85
6.6.29.2 Packed Commands Error Handling......................................................................................... 86
6.6.30 Exception Events..................................................................................................................... 87
6.6.31 Cache....................................................................................................................................... 87
6.6.32 Features cross matrix............................................................................................................... 89
6.6.33 Dynamic Capacity Management ............................................................................................. 91
6.6.34 Large sector size...................................................................................................................... 92
6.6.34.1 Disabling emulation mode....................................................................................................... 94
6.6.34.2 Native 4KB sector behavior .................................................................................................... 95
6.6.35 Real Time Clock Information.................................................................................................. 96
6.6.35.1 Periodic Wake-up.................................................................................................................... 97
6.6.36 Power Off Notification............................................................................................................ 97
6.7 Clock control...........................................................................................................................97
6.8 Error conditions.......................................................................................................................98
JEDEC Standard No. 84-B451
6.8.1 CRC and illegal command ...................................................................................................... 98
6.8.2 Time-out conditions ................................................................................................................ 98
6.8.3 Read ahead in multiple block read operation ......................................................................... 99
6.9 Minimum performance............................................................................................................99
6.9.1 Speed class definition.............................................................................................................. 99
6.9.2 Measurement of the performance.......................................................................................... 100
6.10 Commands.............................................................................................................................101
6.10.1 Command types..................................................................................................................... 101
6.10.2 Command format................................................................................................................... 101
6.10.3 Command classes.................................................................................................................. 101
6.10.4 Detailed command description.............................................................................................. 102
6.11 Device state transition table ..................................................................................................109
6.12 Responses..............................................................................................................................111
6.13 Device status..........................................................................................................................112
6.14 Memory array partitioning ....................................................................................................116
6.15 Timings..................................................................................................................................118
6.15.1 Command and response......................................................................................................... 118
6.15.2 Data read ............................................................................................................................... 120
6.15.3 Data write .............................................................................................................................. 121
6.15.4 Bus test procedure timing...................................................................................................... 124
6.15.5 Boot operation ....................................................................................................................... 125
6.15.6 Alternative boot operation..................................................................................................... 126
6.15.7 Timing Values....................................................................................................................... 127
6.15.8 Timing changes in HS200 mode ........................................................................................... 128
6.15.8.1 Timing values........................................................................................................................ 128
6.15.8.2 Read Block Gap..................................................................................................................... 128
6.15.8.3 CMD12 Timing Modification in Write Operation ................................................................ 129
6.15.8.4 CMD12 Timing Modification in Read Operation................................................................. 130
6.15.8.5 R1B Timing ........................................................................................................................... 130
6.15.8.6 Reselecting a Busy Device .................................................................................................... 130
6.15.9 H/W Reset Operation ............................................................................................................ 131
6.15.10 Noise filtering timing for H/W Reset.................................................................................... 131
7 Device Registers....................................................................................................................132
7.1 OCR register..........................................................................................................................132
7.2 CID register...........................................................................................................................132
7.2.1 MID [127:120] ...................................................................................................................... 133
JEDEC Standard No. 84-B451
-v7.2.2 CBX [113:112]...................................................................................................................... 133
7.2.3 OID [111:104]....................................................................................................................... 133
7.2.4 PNM [103:56]........................................................................................................................ 133
7.2.5 PRV [55:48] .......................................................................................................................... 133
7.2.6 PSN [47:16]........................................................................................................................... 133
7.2.7 MDT [15:8] ........................................................................................................................... 134
7.2.8 CRC [7:1].............................................................................................................................. 134
7.3 CSD register..........................................................................................................................135
7.3.1 CSD_STRUCTURE [127:126]............................................................................................. 137
7.3.2 SPEC_VERS [125:122] ........................................................................................................ 137
7.3.3 TAAC [119:112] ................................................................................................................... 137
7.3.4 NSAC [111:104].................................................................................................................... 137
7.3.5 TRAN_SPEED [103:96]....................................................................................................... 138
7.3.6 CCC [95:84].......................................................................................................................... 138
7.3.7 READ_BL_LEN [83:80] ...................................................................................................... 138
7.3.8 READ_BL_PARTIAL [79] .................................................................................................. 139
7.3.9 DSR_IMP [76] ...................................................................................................................... 139
7.3.10 C_SIZE [73:62]..................................................................................................................... 140
7.3.11 VDD_R_CURR_MIN [61:59] and VDD_W_CURR_MIN [55:53].................................... 140
7.3.12 VDD_R_CURR_MAX [58:56] and VDD_W_CURR_MAX [52:50].................................. 140
7.3.13 C_SIZE_MULT [49:47]........................................................................................................ 141
7.3.14 ERASE_GRP_SIZE [46:42] ................................................................................................. 141
7.3.15 ERASE_GRP_MULT [41:37] .............................................................................................. 141
7.3.16 WP_GRP_SIZE [36:32]........................................................................................................ 141
7.3.17 WP_GRP_ENABLE [31]...................................................................................................... 141
7.3.18 DEFAULT_ECC [30:29] ...................................................................................................... 141
7.3.19 R2W_FACTOR [28:26]........................................................................................................ 141
7.3.20 WRITE_BL_LEN [25:22]..................................................................................................... 142
7.3.21 WRITE_BL_PARTIAL[21].................................................................................................. 142
7.3.22 CONTENT_PROT_APP [16]............................................................................................... 142
7.3.23 FILE_FORMAT_GRP [15] .................................................................................................. 142
7.3.24 COPY [14]............................................................................................................................. 142
7.3.25 PERM_WRITE_PROTECT [13].......................................................................................... 143
7.3.26 TMP_WRITE_PROTECT [12]............................................................................................. 143
7.3.27 FILE_FORMAT [11:10]....................................................................................................... 143
JEDEC Standard No. 84-B451
7.3.28 ECC [9:8] .............................................................................................................................. 143
7.3.29 CRC [7:1].............................................................................................................................. 143
7.4 Extended CSD register..........................................................................................................145
7.4.1 EXT_SECURITY_ERR [505] .............................................................................................. 150
7.4.2 S_CMD_SET [504]............................................................................................................... 150
7.4.3 HPI_FEATURES [503]......................................................................................................... 150
7.4.4 BKOPS_SUPPORT [502]..................................................................................................... 151
7.4.5 MAX_PACKED_READS [501]........................................................................................... 151
7.4.6 MAX_PACKED_WRITES [500]......................................................................................... 151
7.4.7 DATA_TAG_SUPPORT [499] ............................................................................................ 151
7.4.8 TAG_UNIT_SIZE [498]....................................................................................................... 151
7.4.9 TAG_RES_SIZE [497] ......................................................................................................... 152
7.4.10 CONTEXT_CAPABILITIES [496]...................................................................................... 152
7.4.11 LARGE_UNIT_SIZE_M1 [495] .......................................................................................... 152
7.4.12 EXT_SUPPORT [494].......................................................................................................... 152
7.4.13 CACHE_SIZE [252:249] ...................................................................................................... 152
7.4.14 GENERIC_CMD6_TIME [248]........................................................................................... 153
7.4.15 POWER_OFF_LONG_TIME [247]..................................................................................... 153
7.4.16 BKOPS_STATUS [246] ....................................................................................................... 154
7.4.17 CORRECTLY_PRG_SECTORS_NUM [245:242].............................................................. 154
7.4.18 INI_TIMEOUT_PA [241]..................................................................................................... 154
7.4.19 TRIM_MULT [232].............................................................................................................. 155
7.4.20 SEC_FEATURE_SUPPORT [231]....................................................................................... 155
7.4.21 SEC_ERASE_MULT [230].................................................................................................. 156
7.4.22 SEC_TRIM_MULT [229]..................................................................................................... 156
7.4.23 BOOT_INFO [228]............................................................................................................... 156
7.4.24 BOOT_SIZE_MULT [226]................................................................................................... 157
7.4.25 ACC_SIZE [225]................................................................................................................... 157
7.4.26 HC_ERASE_GRP_SIZE [224]............................................................................................. 158
7.4.27 ERASE_TIMEOUT_MULT [223] ....................................................................................... 158
7.4.28 REL_WR_SEC_C [222] ....................................................................................................... 158
7.4.29 HC_WP_GRP_SIZE [221].................................................................................................... 159
7.4.30 S_C_VCC[220] and S_C_VCCQ[219]................................................................................. 159
7.4.31 S_A_TIMEOUT [217] .......................................................................................................... 159
7.4.32 SEC_COUNT [215:212]....................................................................................................... 160
7.4.33 MIN_PERF_a_b_ff [210/:205] and MIN_PERF_DDR_a_b_ff [235:234]........................... 160
JEDEC Standard No. 84-B451
-vii7.4.34 PWR_CL_ff_vvv [203:200] and PWR_CL_DDR_ff_vvv [239:238]................................... 161
7.4.35 PARTITION_SWITCH_TIME [199] ................................................................................... 162
7.4.36 OUT_OF_INTERRUPT_TIME [198] .................................................................................. 162
7.4.37 DRIVER_STRENGTH [197]................................................................................................ 163
7.4.38 DEVICE_TYPE [196]........................................................................................................... 163
7.4.39 CSD_STRUCTURE [194] .................................................................................................... 163
7.4.40 EXT_CSD_REV [192].......................................................................................................... 163
7.4.41 CMD_SET [191]................................................................................................................... 164
7.4.42 CMD_SET_REV [189]......................................................................................................... 164
7.4.43 POWER_CLASS [187]......................................................................................................... 164
7.4.44 HS_TIMING [185]................................................................................................................ 165
7.4.45 BUS_WIDTH [183] .............................................................................................................. 165
7.4.46 ERASED_MEM_CONT [181] ............................................................................................. 166
7.4.47 PARTITION_CONFIG (before BOOT_CONFIG) [179]..................................................... 166
7.4.48 BOOT_CONFIG_PROT[178] .............................................................................................. 167
7.4.49 BOOT_BUS_CONDITIONS [177] ...................................................................................... 167
7.4.50 ERASE_GROUP_DEF [175]................................................................................................ 169
7.4.51 BOOT_WP_STATUS [174] ................................................................................................. 169
7.4.52 BOOT_WP [173] .................................................................................................................. 169
7.4.53 USER_WP [171]................................................................................................................... 171
7.4.54 FW_CONFIG [169] .............................................................................................................. 172
7.4.55 RPMB_SIZE_MULT [168] .................................................................................................. 172
7.4.56 WR_REL_SET [167]............................................................................................................ 173
7.4.57 WR_REL_PARAM [166]..................................................................................................... 174
7.4.58 SANITIZE_START[165]...................................................................................................... 174
7.4.59 BKOPS_START [164].......................................................................................................... 174
7.4.60 BKOPS_EN [163]................................................................................................................. 174
7.4.61 RST_n_FUNCTION [162].................................................................................................... 175
7.4.62 HPI_MGMT [161] ................................................................................................................ 175
7.4.63 PARTITIONING_SUPPORT [160]...................................................................................... 176
7.4.64 MAX_ENH_SIZE_MULT [159:157]................................................................................... 176
7.4.65 PARTITIONS_ATTRIBUTE [156]...................................................................................... 177
7.4.66 PARTITION_SETTING_COMPLETED [155].................................................................... 177
7.4.67 GP_SIZE_MULT_GP0 - GP_SIZE_MULT_GP3 [154:143]............................................... 178
7.4.68 ENH_SIZE_MULT [142:140] .............................................................................................. 179
JEDEC Standard No. 84-B451
7.4.69 ENH_START_ADDR [139:136].......................................................................................... 179
7.4.70 SEC_BAD_BLK_MGMNT [134] ........................................................................................ 179
7.4.71 TCASE_SUPPORT [132]..................................................................................................... 180
7.4.72 PERIODIC_WAKEUP [131]................................................................................................ 180
7.4.73 PROGRAM_CID_CSD_DDR_SUPPORT [130]................................................................. 180
7.4.74 NATIVE_SECTOR_SIZE [63]............................................................................................. 181
7.4.75 USE_NATIVE_SECTOR [62].............................................................................................. 181
7.4.76 DATA_SECTOR_SIZE [61] ................................................................................................ 181
7.4.77 INI_TIMEOUT_EMU [60]................................................................................................... 181
7.4.78 CLASS_6_CTRL[59]............................................................................................................ 182
7.4.79 DYNCAP_NEEDED [58]..................................................................................................... 182
7.4.80 EXCEPTION_EVENTS_CTRL [57:56]............................................................................... 182
7.4.81 EXCEPTION_EVENTS_STATUS [55:54].......................................................................... 182
7.4.82 EXT_PARTITIONS_ATTRIBUTE [53:52]......................................................................... 183
7.4.83 CONTEXT_CONF [51:37]................................................................................................... 184
7.4.84 PACKED_COMMAND_STATUS [36]............................................................................... 184
7.4.85 PACKED_FAILURE_INDEX [35]...................................................................................... 185
7.4.86 POWER_OFF_NOTIFICATION [34].................................................................................. 185
7.4.87 CACHE_CTRL [33].............................................................................................................. 185
7.4.88 FLUSH_CACHE [32]........................................................................................................... 185
7.4.89 VENDOR_SPECIFIC_FIELD [127:64] ............................................................................... 186
7.5 RCA register..........................................................................................................................186
7.6 DSR register..........................................................................................................................186
8 Error protection .....................................................................................................................186
8.1 Error correction codes (ECC)................................................................................................186
8.2 Cyclic redundancy codes (CRC)...........................................................................................187
8.2.1 CRC7..................................................................................................................................... 187
8.2.2 CRC16................................................................................................................................... 187
9 e•MMC mechanical standard ................................................................................................188
10 The e•MMC bus....................................................................................................................189
10.1 Power-up ...............................................................................................................................190
10.1.1 e•MMC power-up.................................................................................................................. 192
10.1.2 e•MMC power-up guidelines................................................................................................ 192
10.1.3 e•MMC power cycling .......................................................................................................... 193
10.2 Programmable Device output driver .....................................................................................194
10.3 Bus operating conditions.......................................................................................................196
JEDEC Standard No. 84-B451
-ix10.3.1 Power supply: e•MMC.......................................................................................................... 196
10.3.2 Power supply: e
2
•MMC......................................................................................................... 197
10.3.3 Power supply Voltages.......................................................................................................... 198
10.3.4 Bus signal line load ............................................................................................................... 199
10.4 Bus signal levels....................................................................................................................200
10.4.1 Open-drain mode bus signal level......................................................................................... 200
10.4.2 Push-pull mode bus signal level— e•MMC.......................................................................... 200
10.4.3 Bus Operating Conditions for HS200.................................................................................... 201
10.4.4 Device Output Driver Requirements for HS200 ................................................................... 201
10.4.4.1 Driver Types Definition ........................................................................................................ 201
10.4.4.2 Driver Type-0 AC Characteristics........................................................................................ 202
10.4.4.3 Driver Type-0 Test Circuit.................................................................................................... 203
10.4.4.4 Driver Type Selection ........................................................................................................... 203
10.5 Bus timing .............................................................................................................................203
10.5.1 Device interface timings........................................................................................................ 204
10.6 Bus timing for DAT signals during 2x data rate operation ...................................................206
10.6.1 Dual data rate interface timings............................................................................................. 207
10.7 Bus Timing Specification in HS200 mode............................................................................207
10.7.1 HS200 Clock Timing............................................................................................................. 207
10.7.2 HS200 Device Input Timing ................................................................................................. 208
10.7.3 HS200 Device Output Timing............................................................................................... 209
10.8 Temperature Conditions........................................................................................................210
11 e•MMC standard compliance ................................................................................................211
Annex A Application Notes..................................................................................................................214
A.1 Device Payload block length and ECC types handling.........................................................214
A.2 Description of method for storing passwords on the Device.................................................215
A.3 e•MMC macro commands.....................................................................................................216
A.4 Host interface timing.............................................................................................................227
A.5 Handling of passwords..........................................................................................................227
A.5.1 Changing the password .........................................................................................................227
A.5.2 Removal of the password ......................................................................................................228
A.6 High-speed e•MMC bus functions........................................................................................228
A.6.1 Bus initialization....................................................................................................................228
A.6.2 Switching to high-speed mode ..............................................................................................229
A.6.3 Changing the data bus width .................................................................................................229
JEDEC Standard No. 84-B451
A.7 Erase-unit size selection flow................................................................................................232
A.8 HPI background and one of possible solutions .....................................................................233
A.8.1 Background - issues with HPI............................................................................................... 233
A.8.2 One of possible solutions ...................................................................................................... 233
A.9 Stop transmission timing.......................................................................................................233
A.10 Temperature Conditions per Power Classes (Tcase controlled)............................................235
A.11 Handling write protection for each boot area individually....................................................236
Annex B Changes between system specification versions...................................................................238
B.1. Version 4.1, the first version of this standard........................................................................238
B.2. Changes from version 4.1 to 4.2............................................................................................238
B.3. Changes from version 4.2 to 4.3............................................................................................238
B.4. Changes from version 4.3 to 4.4............................................................................................239
B.5. Changes from version 4.4 to 4.41..........................................................................................239
B.6. Changes from version 4.41 to 4.5..........................................................................................240
B.7. Changes from version 4.5 to 4.51..........................................................................................240