RTL8198数据手册

【实例简介】
RTL8198的数据手册，适合改磊科的285g路由参考！
Cus REALTEK RTL819 Datasheet Table of contents 1. GENERAL DESCRIPTION 2. FEATURES 3. BLOCK DIAGRAM 4. PIN ASSIGNMENTS wepe要 ,6 4.1. PACKAGE IDENTIFICATION 5. PIN DESCRIPTIONS 5.1. CONFIGURATION UPON POWER ON STRAPPING 6. 2. GMAC PIN MODE DESCRIPTION 77455 5.2.1. MAC Interface MI/GMIIIRGMI Mode Pin Sharing Mappings 5.2.2. GMIIIRGMII Inter/uce Pin Descriptions 15 5.2. 3. MlI MAC Mode Inler/ace Pin descriptions 5.2. 4. MI PHy Mode interface Pin descripti Ions 16 SHARED IO PIN MAPPING MEMORY MAP 18 6. MEMORY CONTROLLER.m.. 21 6.1. SDR DRAM CONTROL INTERFACE 21 6.1.2. Bank2 and Bank3 21 6.2. DDR DRAM CONTROLLER 6.2.1.Feat 22 6.3 SPI FLASH CONTROLLER 22 63. Features 22 6.3.2. Pin Mode and Definition of Serial and Dual I/O 6.4 SOFTWARE REGISTER DEFINITIONS 23 6.4.1. Memory Control Register (MCR\(OxB800 1000) 3 6.4.2. DRAM Configuration Register (DCR)(OxB800_1004) 24 6.4.3. DRAM Timing Register(DTRr0xB800_1008) 6.4.4. DDR DRAM Calibration Register(DDCR(0x B800 10.50 6.4.5. SPI Flash Configuration Register (SFCR)(0xB800_1200) 6.4.6. SPI Flash Configuration Register 2(SFCR2)(0x B800_ 1204) 6.4.7. SPI Flash Control, Status Register(SFCSR)(0xB800_1208) 6.4.8. SPIFlashData Register(SFDR)(0xB800_120C) 29 6.4.9. SP! Flash Data Register 2(SFDR2)(OxB800_ 1210) 7.PERIPHERAL AND 30 JNTERRUPT CONTROI 1.、 nterrupt Control register Address Mapping…… 1.2.) NGlobal Interrupt Mask Register 30 Regis 7. 1.4. Interrupt Routing Register O 32 7.1.5. Interrupt Routing Register1…… 7.1.6. Interrupt Routing Register 2. 32 7.1.7. Interrupt Routing Register 3 7. 2. TIMER CONTROL 34 7.2.1. Timer Control Register Address Mapping 7.2.2. Timer Counter o Data register ··· 34 IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Track D:JATR-2265-1/ Rev, 0.91 Cus REALTEK RTL819 Datasheet 7.2.3. Timer Counter I Dala register 34 7.2.4. Timer/ Counter 0 Counter registe 7. 2.6. Timer/Counter Control Register si 7. 5. Timer/Co er registe 35 7.2.7. Timer Counter interrupt Register 235 7. 2.8. Clock Division Base regisler 7.2.9. Watchdog Control Register 7. 3. GPIO CONTROL .37 7.3.1. GP1O Register Set(0xB800 3500) 37 7.3.2. GP1O Port A, B, C, D Control Register(PABCD CNR)(OxB800 3500) 7.3.3. GP1O Port A, B, C, D Direction Register(PABCD DIR)(OxB800-3508 7.3.4. Port A, B, C, D Data Register(PABCD DAT(OrB800 350C 38 7.3.5. Port A, B, C, D Interrupt Status Register(PABCD ISR)(OxB800 3510 39 7.3.6. Port A, B Interrupt Mask Register (PAB IMR)(OxB800 3.514 39 3. 7. Port C, D Interrupt Mask register(PCD/MR)(OxB800 3578) 40 7.3. 8. GPIO Port E, F, G, H Control Register (PEFGH CNR)(OxB800 3510 40 3.9. GPIO Port F, F, G, H Direction Register(PEFGH DIR)(OxB800 3.524) 41 7.3. 10. Port F, F, G, H Data Register(PEFGH DAT)(OxB800 3528) 41 Port E, F,G, H Interrupt Status Register(PEFGH ISR)(OxB800-352C) 42 7.3.12 Port E, F Interrupt Mask Register(PEF IMR)(OxB800 3530 2 7.3.13. Port G, H Interrupt Mask register(PGH MMR)(OxB800 3534 42 74. GPIO SIIARED PIN CONFIGURED MAPPING LIST 44 74, Shared pin register( PIN MUX SEL0xB8000040-0xB800043形)………… 7. 42. Shared Pin Register(PIN_ MUX SEL 2, 0xB8000044-0xB80Q0047h 8. GREEN ETHERNET CABLE LENGTII POWER SAVING 8. 2. LINK DOWN POWER SAVING 666 ENERGY EFFICIENT ETIIERNET (EEE) 9. ETHERNET SWITCH CORE ,48 9.1. GLOBAL PORT CONTROL REGISTER 9. 1. MAC Configuration register 9.1.1.1 Description ,48 9.1.2. Port mirror Control register 9.1.2.1 Port Mirroring Control register 49 9.1.3. Frame Filtering Control register...... 9.1.3. 1 Broadcast Storm Control register 9.1.3.2 Checksum Control registe 9.2 PER-PORT CONFIGURATION REGISTER 9.2.1. Port Interface Type Configuration Register 9,2.2. Port Configuration Register 9.2.3.Port Status Register 9.3./SWITCH MSIC CONTROL REGISTER 58 93如形0m1 D Register……… ··中 9.4.1/ Aging Timer Control Register 9.4.2 Module Switch Control regisler USB 2.0 HOST INTERFACE 64 0. 1. OPEN HOST CONTROLLER INTERFACE(OHCI)OPERATIONAL REGISTERS 10.1.1. Open Host Controller Interface(OHCI) Operational Registers l0.l.2. Control and status partition 10.1.3. Memory Pointer Partition........... IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Track D:JATR-2265-1/ Rev, 0.91 Cus REALTEK RTL819 Datasheet 10.1.4 frame counter partition 10.1.5. Root Hub partition 10.2. EHCI CAPABILITY AND OPERATIONAL REGISTERS 80 l0.2.l Capabilily regisler 10.2.2. Operational Registers UART 92 11. 1. FEATURES 92 112. INTERFACE PINS ··4·· 11.3. UART CONTROL REGISTER…… 11.3.1. UART Control Regisler Address Mapping 11.3.2. UART Receiver Buller Register (DLAB-o) 11.3.3. UART Trunsmiller Holding Regisler DLAB-0 11.3.4. UART Divisor Latch LSB (DLaB=1 11.3.5. UART Divisor Latch MSB (DLaB=1) 11.3.6. UART Interrupt Enable register DLAB=0) 11.3.7. UART Interrupt ldentification Register……… 94 113.8. UARTFIFO Control Register 11.3.9. UART Line control Register 11.3.10. UARTModem Control Register /1.3. 11. UART Line Status Register ++ 17.3.12. ART Modem status register 96 114 BAUD RATE NON-FLASII BOOTING INTERFACE (NFBI)............. 8 12.1. BLOCK DIAGRAM 98 122. NFBI FRAME FORMAT 123. NFBI REGISTER ADDRESS MAPPING 12 4 PHY IDENTIFIER REGISTERS 12.5. COMMAND REGISTER 100 126. ADDRESS REGISTERS .10 12.7. DATA REGISTER 102 12.7. Command and status Register ++++ 02 12.8. SYSTEM STATUS REGISTER . 103 12.8.1. Interrupt Mask Register *·::···· 103 12.8.2. Interrupt Status Register 12.9. RTL8198 INTERNAL CPU NFBI CONTROL REGISTER 105 12.9.1. Receive Command and send status Register 12.9.2. Interrupt Mask and Interrupt Status Register On NFBI PCI EXPRESS BUS INTERFACE……… 107 3. 1. PCI EXPRESS TRANSMITTER .107 13.2. PCH EXPRESS RECEIVER 107 13.3 CI EXPRESS ADDRESS MAPPING 107 13.4. PCT EXPRESS HOST MODE... 108 13.4 PCIE Host Mode Extended Register Address Mapping 13.4.2 PCIE MDIO Register.……… K3.4.3, PCIE Interrupt status Register 13.44 PCIE Power Control Register …109 3. 4.5. PCIE IP Configuration Register 10 13. 4.6. PCIE SRAM BlST Check register 1l0 DC SPECIFICATIONS 111 14.1. OPERATING CONDITIONS∴……. 111 14.2. TOTAL POWER CONSUMPTION 111 IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Track D:JATR-2265-1/ Rev, 0.91 Cus REALTEK RTL819 Datasheet 14.3. SDR DRAM BUS DC PARAMETERS …112 14.4. DDR DRAM BUS DC PARAMETERS l12 14.5. FLASH BUS DC PARAMETERS 12 14.6. USB V1. 1 DC PARAMETERS 14.7. USB V2.0 DC PARAMETERS 113 14. 8. UART DC PARAMETERS l13 14.9. GPIO DC PARAMETERS 114 14.10. JTAG DC PARAMETERS l14 14.11 MII DC PARAMETERS… 14.12. GMII DC PARAMETERS 14.13 RGMII DC PARAMETERS l15 14.14 RESET DC PARAMETERS 115 14.15. LED DC PARAMETERS 15 AC SPECIFICATIONS .117 151. CLOCK SIGNAL TIMING 117 15.7.. SDR DRAM Clock Timing…… 15.1.2. Mll Clock Timing 119 15.13. GMII Clock Timing 120 15.1.4. RGMI/ CLock Timing /2 152. BUS SIGNAL TIMING 122 15.2. SDR DRAM BuS 122 1.5.2.2 DDR DRAM BuS 124 15.2.3 Serial Flash Interface Output Timing 25 1.5.2.4. Serial Flash Inter face intput Timing.. 126 15.2..5. INTerface 26 15.2.6. GMII Timing characteristics 128 15.2.7. RGMII Timing Characteristics 129 15.2.8 J丿 TAG Boundary Scan 130 15.2.9. Power sequence 13l 15.2.10. Power Configuration limin 13l 15.3. PCI EXPRESS BUS PARAMETERS 132 15.3.1. Differential Transmitter parameters 132 15.3. 2. Differential Receiver parameters. 33 15.33. REFCLK Parameter's 133 THERMAL CHARACTERISTICS 138 16. 1. THERMAL OPERATING RANGE 139 16.2. THERMAL PARAMETERS 139 17. MECHANICAL DIMENSIONS. 17. 1. MECHANICAL DIMENSIONS NOTES 10 18. ORDERING INFORMATION 141 IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Track D:JATR-2265-1/ Rev, 0.91 Cus REALTEK RTL819 Datasheet List of tables TABLE 1. PIN DESCRIPTIONS TABLE 2. CONFIGURATION UPON POWER ON STRAPPING TABLE 3. MAC INTERFACE MI RGMII MODE PIN SIIARING MAPPINGS 7461 TABLE 4. GMIVRGMIL INTERFACE PIN DESCRIPTIONS TABLE 5. MII MAC MODE INTERFACE PIN DESCRIPTIONS…….......… TABLE 6. MII PHY MODE INTERFACE PIN DESCRIPTIONS TABLE 7. SHAREDIO PIN MAPPING 17 table 8 MEMORY MAP,……… TABLE 9. MEMORY CONTROL REGISTER(MCR)(OXB800 1000) TABLE 10. DRAM CONFIGURATION REGISTER (DCR)(OXB800 1004) 24 TABLE.DRAMTMNGRFGISTER(DTR)(0XB8001003…0 TABLE 12. DDR DRAM CALIBRATION REGISTER(DDCR)(OXB800 1050)......../. 26 TABLE 13. SPI FLASH CONFIGURATION REGISTER(SFCR)(OXB800_1200). TABLE 14. SPI FLASH CONFIGURATION REGISTER 2(SPCR2)(OXB800 1204 TABLE 15. SPI FLASH CONTROL STATUS REGISTER(SFCSR)(0XB800 1208).... TABLE 16. SPI FLASH DATA REGISTER(SFDR)(OXB800 120c)..... TABLE 17. SPI FLASH DATA REGISTER 2(SFDR2)(OXB800 1210 29 TABLE 18. INTERRUPT CONTROL REGISTER ADDRESS MAPPING(OXB80023000) 30 TABLE 19. GLOBAL INTERRUPT MASK REGISTER (GIMR)(OXB800_3000) TABLE 20. GLOBAL INTERRUPT STATUS REGISTER (GISR)(OXB800 3004) TABLE 21. INTERRUPT ROUTING REGISTER O (IRRO) (OXB800 3008) TABLE 22. INTERRUPT ROUTING REGISTER 1(IRRI)(0XB800 300C) TABLE 23. INTERRUPT ROUTING REGISTER 2(IRR2)(0XB800 3010) 2223 TABLE 24. INTERRUPT ROUTING REGISTER 3 (IRR3)(0XB800_3014) TABLE 25. TIMER CONTROL REGISTER ADDRESS MAPPING (BASE: OXB800 3 100) TABLE 26. TIMER/ COUNTER O DATA REGISTER (OXB800 3100)> TABLE 27. TIMER/ COUNTER I DATA REGISTER (OXB800 3104) TABLE28. TIMER COUNTER O COUNTER REGISTER(0xB8003108)………………… TABLE 29. TIMER/ COUNTER I COUNTER REGISTER (OXB800_310C). TABLE30. TIMER/COUNTER CONTROF REGISTER(OXB800_3110) TABLE 3 TIMER/ COUNTER INTERRUPT REGISTER(OXB800_3114 TABLE 32. CLOCK DIVISION BASE REGISTER (OXB800 3118 TADLE 33. WATCIIDOG CONTROL REGISTER(OXB800 311C TABLE 34. GPIO REGISTER SET(OXB800 3500 TADLE 35. GPIO PORT A, B, C, DCONTROL REGISTER(PABCD_CNR)(OXB800_3500 38 TABLE 36. GPIO PORTA, B, C, D DIRECTION REGISTER(PABCD DIR)(OXB800_ 3508) TABLE 37. PORT A, B, C, DDATA REGISTER(PABCD_DAT)(OXB800_350C) 38 TABLE 38. PORT A/B, C, DINTERRUPT STATUS REGISTER(PABCD_ISR)(OXB800_3510) TABLE 39. PORTA, B INTERRUPT MASK REGISTER(PAB IMR)(0XB800_3514) TABL40. PORTO, D INTERRUPT MASK REGISTER( PCD IMR)(0XB8003518)……,……… 10 TABDE41. GPIO PORTE, F, G, H CONTROL REGISTER(PEFGH_CNR)(0XB800_351C) 0 TABLE 42. GPIO PORTE, F, G, H DIRECTION REGISTER(PEFGH DIR)(0XB800 3524)..... TABLE43. PORT E, F, G, H DATA REGISTER(PEFGH DAT)(OXB800 3528) TABLE 44. PORT E, F, G, H INTERRUPT STATUS REGISTER(PEFGH ISR)(0XB800 352C 42 O TABLE 45. PORT E, F INTERRUPT MASK REGISTER(PEF IMR)(OXB800 3530) 42 TABLE 46. PORT G H INTERRUPT MASK REGISTER(PGH IMR)(0XB800 3534)...................42 TABLE 47. SHARED PIN REGISTER(PIN MUX SEL, OXB800 0040-0X B800 0043H) 44 TABLE 48. SHARED PIN REGISTER(PIN MUX SEL 2, 0XB800 0044-0XB800 0047H) 45 TABLE 49. MAC CONFIGURATION REGISTER(OXBB80-4000) 48 TABLE 50. PORT MIRROR CONTROL REGISTER (OXBB80-400C) 50 TABLE 51. BROADCAST STORM CONTROL REGISTER (0XBB80-4044) TABLE 52. CHECKSUM CONTROL REGISTER (0XBB80-4048)..............................51 IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Track D:JATR-2265-1/ Rev, 0.91 Cus REALTEK RTL819 Datasheet TABLE 53. PORT INTERFACE TYPE CONTROL REGISTER(OXBB804100) TABLE 54. PORT CONFIGURATION REGISTER OF PORTN N-0-41 TABLE 55. PORT STATUS REGISTER OF PORTN(N-0-4 57 TABLE 56. CHIP VERSION ID REGISTER (OXBB80-4200) 58 TABLE 57. SWITCH SYSTEM INITIAL REGISTER (OXBB80-4204) 58 TABLE 58. CHIP REVISION MANAGEMENT REGISTER O(OX BB80-4208 TABLE 59. COUNTER VALUE AND TIMING MEANING TRANSLATION 61 TABLE 60. TABLE ENTRY AGING CONTROL REGISTER (OX BB80-4400) TABLE 61. MODULE SWITCH CONTROL REGISTER (OX BB80-4410) TABLE 6 OHCI OPERATIONAL REGISTER SET(OXB802 0000) 4 TABLE 63. HCREVISION REGISTER (OXB802 0000 TABLE 64. HCCONTROL REGISTER (OXB802 0004 TABLE 65. IICCOMMANDSTATUS REGISTER (OXB802 0008) 67 TABLE 66 HCINTERRUPTSTATUS REGISTER(OXB802 000C) 68 TABLE 67. HCINTERRUPTENABLE REGISTER(OX B802 0010 TABLE 68. HCINTERRUPTDISABLE REGISTER (OXB802 0014 TABLE 69. HCHCCA REGISTER(OXB802 0018) 70 TABLE 70. HCPERIODCURRENTED REGISTER(OX B802 001C) 70 TABLE 71. HCCONTROL HEADED REGISTER (OXB802 0020) TABLE 72. HCCONTROLCURRENTED REGISTER (OXB802 0024) 71 TADLE 73. HCBULKHEADED REGISTER (OXB802 0028) TADLE 74. HCBULKCURRENTED REGISTER (OXB802 002C) 71 TABLE 75. HCDONEHEAD REGISTER(OXB 802 0030) TADLE 76. HCFMINTERVAL REGISTER(OXB802 0034) 72 TABLE 77. HCFMREMAINING REGISTER (OXB802 0038) TABLE 78. HCFMNUMBER REGISTER(OXB802 003C 73 TABLE 79. HCPERIODICSTART REGISTER(OXB802 0040) TABLE 80. HCLSTHRESHOLD REGISTER(OXB802 0044).... 74 TABLE 81. HCRHDESCRIPTORA REGISTER(OXB802_0048). TABLE 82. HCRHDESCRIPTORB REGISTER(OXB802 004C) TABLE 83. HCRHSTATUS REGISTER (OXB802 0050).......... 76 TABLE 84. HCRHSTATUS REGISTER (OXB802 0054, 0058) TABLE 85. EHCI CAPABILITY REGISTER SET(OXB802 1000 TABLE 86. CAPLENGTH REGISTER (OXB802 1000) 80 TABLE87.HCIⅤ ERSION REGISTE取(0xB8021002) TABLE 88. HCSPARAMS REGISTER(OXB802 1004) TABLE 89. HCCP ARAMS REGISTER(OXB802 1008) TABLE 90. HCSP-PORTROSTE REGISTER(OXB802 100C)..... LE 91. EHCI OPERATIONAL REGISTER SET(BASE: OXB802 1010 8888 TABLE 92. USBCMD REGISTER (OXB802 1010 TABLE 93. USBSTS REGISTER (OXB802 1014 TABLE 94. USBINTR REGISTER(OXB802 1018) TABLE9. FRINDEX reGISter(0xB802101C)…… TABLE 96//CTRLDSSEGMENT REGISTER(0XB802 1020) TABLE97 PERIODICLISTBASE REGISTER(OXB802 1024 TABLE 98. ASYNCLISTBASE REGISTER(0XB802 1024) TABLE 99. CONFIGFLAG REGISTER(OXB802-_1050) TABLE10O/PORTSC REGISTER(0XB802 1054 87 TABL LOL UART CONTROL INTERFACE PINS \TABLE 102. UART CONTROL REGISTER ADDRESS MAPPING(BASE: OXB800 2000)..... 92 ABLE 103. UART RECEIVER BUFFER REGISTER DLAB=0)(OXB800 2100, 0XB800 2000) TARLE 104. UART TRANSMITTER HOL DING REGISTER(DLAB=0)(0XB800 2100,0XB800 2000) TABLE 105. UART DIVISOR LATCH LSB (DLAB=D)(OXB800 2100,,0X B800 2000) TADLE 106. UART DIVISOR LATCII MSB (DLAB=1)(0XB800 2104, 0XB800 2004) TADLE 107. UART INTERRUPT ENADLE REGISTER (DLAB=O)(OXB800 2104,0XB800 2004) IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Ill Track D:JATR-2265-1/ Rev, 0.91 Cus REALTEK RTL819 Datasheet TABLE 108. UART INTERRUPT IDENTIFICATION REGISTER(OXB800 2108, 0XB800 2008).............. 94 TABLE 109. UART FIFO CONTROL REGISTER(OXB800 2108, 0XB800 2008) TABLE 110. UART LINE CONTROL REGISTER(OXB800 210C, 0XB800 200C TABLE 111. UART MODEM CONTROL REGISTER(OXB800-2110,0XB800-2010) TABLE 112. UART LINE STATUS REGISTER(OXB800 2114,0XB800 2014) TABLE 113. UART MODEM STATUS REGISTER (OXB800-2110,0XB800-2018) TABLE 114. DIVISOR LATCH VALUE EXAMPLES TABLE115. NFBI FRAME FORMAT…… .9 TABLE 116. NFBI REGISTER ADDRESS MAPPING 99 TABLE 117. PHY IDENTIFIER REGISTER 1 (REGAD OXO2) 100 TABLE 118. PHY IDENTIFIER REGISTER 2 (REGAD OXO3) 100 TABLE 119. COMMAND REGISTER(REGAD OX1O) 100 TABLE 120. ADDRESS REGISTER (IIIGH)(REGAD OXIl) TABLE 121. ADDRESS REGISTER LOW)(REGAD OX 12) 101 TABLE 122. DATA REGISTER (HIGH)(REGAD 13) 102 TABLE 123. DATA REGISTER LOW)(REGAD OX 14) .102 TABLE 124. SEND COMMAND REGISTER (REGAD OX I5) 102 TABLE 125. RECEIVE STATUS REGISTER(REGAD OX16 .102 TABL E 126. SYSTEM STATUS REGISTER(REGAD I7 103 TABLE 127. INTERRUPT MASK REGISTER(REGAD OX19) 103 TADLE 128. INTERRUPT STATUS REGISTER (REGAD OXIA) TADLE 129. CPU INTERNAL REGISTER TABLE(OXB801 9000 105 TABLE 130. RTL8198 CPU RECEIVE COMMAND REGISTER(OXB801 900 105 TABLE 131. rtl8 198 CPU SEND STATUS REGISTER (OXB801 9004 105 TABLE 132. RTL8198 NFBI INTERRUPT MASK REGISTER(OXB8019010).............106 TABLE 133. RTL8198 NFBI INTERRUPT STATUS REGISTER(OXB801 9014). / 106 TABLE 134. PCI EXPRESS ADDRESS MAPPING...... 107 TABLE 135. PCI-E HOST MODE EXTENDED REGISTER ADDRESS MAPPING(BASE: OXB8B0 1000/0XB8B2 1000).........108 TABLE 136. PCI-E MDIO REGISTER(OXB8B0 1000/ 0XB8B21000) TABLE 137. PCIE INTERRUPT STATUS REGISTER(OXB&B0 1004/0XB8B2 1004) TABLE 138. PCIE POWER CONTROL REGISTER(0XB8B0_1008/0XB8B2_1008). 109 TABLE 139. PCIE IP CONFIGURATION REGISTER(OXB8BO 100C/0XB8B2 100C) 110 TABLE 140. PCIE SRAM BIST CHECK REGISTER(OXB8B0_1010/0XB8B2_1010) 1110 TABLE 141. OPERATING CONDITIONS l11 TABLE 143. SDR DRAM BUS DC PARAMETERS.. TABLE 144. DDR DRAM BUS DC PARAMETERS 112 TABLE 145. FLASH BUS DC PARAMETERS 112 TABLE146.USBV1 DCPARAMETERS…… 113 TABLE 147 SBV2 DC PARAMETERS……… 113 TABLE 148. UARTDC PARAMETERS TABLE 149. GPIO DC PARAMETERS 1l4 TABLE 150. JTAG DC PARAMETERS l14 TABLE151//MII DC PARAMETERS 114 TABLE 152, GMII DC PARAMETERS 115 TABLE 153. RGMIIDC PARAMETERS 115 TABI1154. RESET DC PARAMETERS…… 155/ LED DC PARAMETERS 116 TABI. E 56. CLOCK SIGNAL, TIMING 117 \TABLE 157. SDR DRAM CLOCK TIMING l18 able 158. MII CLOCK TImING TABLE 159 GMII CLOCK TIMING l20 TABLE 160. RGMII CLOCK TIMING TABLE 161. SDR DRAM INPUT TIMING TABLE 162. SDR DRAM OUTPUT TIMING IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Track D:JATR-2265-1/ Rev, 0.91 Cus REALTEK RTL819 Datasheet TABLE 163. SDR DRAM ACCESS CONTROL TIMING 123 TABLE 164. DDR DRAM INPUT TIMING 124 TABLE165. DDR DRAM OUTPUT TIMING…… …124 TABLE 166. DDR DRAM ACCESS CONTROL TIMINO 124 TABLE 167. SERIAL FLASH INTERFACE OUTPUT TIMING 125 TABLE 168. SERIAL FLASH INTERFACE INTPUT TIMINO 126 TABLE 169. MII MAC MODE OUTPUT TIMING TABLE 170. MII PHY MODE OUTPUT TIMING 126 TABLE 171. MII MAC MODE INPUT TIMING VALUES 127 TABLE 172. MII PHY MODE INPUT TIMING VALUES 127 TABLE 173. GMII TIMING CHARACTERISTICS 128 TABLE 174. RGMII TIMING CHARACTERISTICS .129 TABLE 175. JTAG BOUNDARY SCAN INTERFACE TIMING VALUES 130 TABLE 176. POWER-UP TIMING PARAMETERS 13 TABLE 177. IFFERENTIAL TRANSMITTER PARAMETERS 132 TABLE 178. IFFERENTIAL RECEIVER PARAMETERS 133 TABLE 179. REFCLK PARAMETERS 133 TABLE 80. THERMAL OPERATING raNGE 139 table I &L THERMAL PARAMETERS 1.39 TABLE 82. ORDERING INFORMATION 141 IEEE 802. 1In Gigabit Ethernet AP/Router Network Processor Track D:JATR-2265-1/ Rev, 0.91 【实例截图】
【核心代码】