Multicore DSP_From Algorithms to Real-time Implementation

【实例简介】
This unique book provides readers with an understanding of the TMS320C66xx SoC as well as its constraints. It offers critical analysis of each element, which not only broadens their knowledge of the subject, but aids them in gaining a better understanding of how these elements work so well together.
This edition first published 2018 o 2018 John Wiley Sons Ltd All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by law. Advice onhowtoobtainpermissiontoreusematerialfromthistitleisavailableathttp://www.wiley.com/go/permissions The right of Naim Dahnoun to be identified as the author of this work has been asserted in accordance with law Registered ofic John Wiley Sons, Inc, 1ll River Street, Hoboken, N)07030, USA John Wiley Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, UK Editorial office The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, UK For details of our global editorial offices, customer services, and more information about Wiley products visit us at www.wlley.com Wiley also publishes its books in a variety of electronic formats and by print-on-demand. Some content that appears in standard print versions of this book may not be available in other formats Limit of liability disclaimer of warrant While the publisher and authors have used their best efforts in preparing this work, they make no representations or warranties with respect to the accuracy or completeness of the contents of this work and specifically disclaim all warranties, including without limitation any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives, written sales materials or promotional statements for this work. The fact that an organization, website, or product is referred to in this work as a citation and/or potential source of further information does not mean that the publisher and authors endorse the information or services the organization, website, or product may provide or recommendations it may make. This work is sold with the understanding that the publisher is not engaged in rendering professional services. The advice and strategies contained herein may not be suitable for your situation. You should consult with a specialist where appropriate Further, readers should be aware that websites listed in this work may have changed or disappeared between when this work was written and when it is read Neither the publisher nor authors shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages Library of Congress Cataloging-in-Publication data applied for ISBN:9781119003823 Cover design by wile Cover image: matejmo/ Gettyimages Set in 10/12pt Warnock by SPi Global, Pondicherry, India 10987654321 i dedicate this book to my children Zahra, Yasmin and riyad and in memory of my parents Contents Preface xviii Acknowledgements xxi Foreword xxii About the Companion Website xxiii Introduction to dsp 1 1.1 Introduction 1 1.2 Multicore processors 3 1. 2. 1 Can any algorithm benefit from a multicore processor? 3 1.2.2 How many cores do i need for my application? 5 1.3 Key applications of high-performance multicore devices 6 1.4 FPGAS, Multicore dsps, gpus and multicore cpus 8 1.5 Challenges faced for programming a multicore processor 9 1.6 Texas Instruments DSP roadmap 10 1.7 Conclusion 11 References 12 2 The tms320C66x architecture overview 14 2.1 Overview 14 2.2 The CPu 15 2.2. 1 Cross paths 16 2.2. 1 1 Data cross paths 17 2.2.1.2 Address cross paths 18 2.2.2 Register file a and file b 20 2.2.2.1 Operands 20 2.2.3 Functional units 21 2.2.3.1 Condition registers 21 2.2.3.2. L units22 2.2.3.3 Units22 2.2.3.4 S units23 2.2.3.5 D units23 2.3 Single instruction, multiple data(SIMD) instructions 24 2.3. 1 Control registers 24 2.4 The Keystone memory 24 2.4.1 USing the internal memory 27 2.4.2 Memory protection and extension 29 2.4.3 Memory throughput 29 viiContents 2.5 Peripherals 30 2.5.1 Navigator 32 2.5.2 Enhanced Direct Memory Access(EDMA) Controller 32 2.5.3 Universal Asynchronous Receiver/Transmitter (UART) 32 2.5.4 General purpose input-output(GPIO) 32 2.5.5 Internal timers 32 2.6 Conclusion 33 References 33 3 Software development tools and the tMS320C6678 EVM 35 3.1 Introduction 35 3.2 Software development tools 37 3. 2.1 Compiler 38 3.2.2 Assembler 39 3.2.3 Linker 40 3.2.3. 1 Linker command file 40 3.2.4 Compile, assemble and link 42 3. 2.5 USing the Real-Time Software Components(rTsC) tools 42 3.2.5.1 Platform update using the XDCtools 42 3.2.6 Keystone Multicore Software Development Kit 47 3.3 Hardware development tools 47 3.3.1 EVM features 47 3.4 Laboratory experiments based on the C6678 EVM: introduction to Code Composer Studio(CCS) 51 3.4.1 Software and hardware requirements 51 3.4.1.1 Key features 52 3.4. 1.2 Download sites 53 3.4.2 Laboratory experiments with the CCS6 53 3.4.2.1 Introduction to CCs 55 3.4.2.2 Implementation of a dotp algorithm 63 3.4.3 Profiling using the clock 65 3.4.4 Considerations when measuring time 67 3.5 Loading different applications to different cores 67 3.6 Conclusion 72 References 72 4 Numerical issues 74 4.1 Introduction 74 4. 2 Fixed- and floating-point representations 75 4.2.1 Fixed-point arithmetic 76 4.2.1. 1 Unsigned integer 76 4.2.1.2 Signed integer 77 4.2.1.3 Fractional numbers 77 4. 2.2 Floating-point arithmetic 78 4. 2.2.1 Special numbers for the 32-bit and 64-bit floating-point formats 8 4.3 Dynamic range and accuracy 82 4.4 Laboratory exercise 83 4.5 Conclusion 85 References 85 Contentsⅸx Software optimisation 86 5.1 Introduction 86 5.2 Hindrance to software scalability for a multicore processor 88 5.3 Single-core code optimisation procedure 88 5.3.1 The C compiler options 90 5.4 Interfacing C with intrinsics, linear assembly and assembly 9 5.4.1 Intrinsics 91 5.4.2 Interfacing C and assembly 92 5.5 Assembly optimisation 97 5.5.1 Parallel instructions 98 5.5.2 Removing the Nops 99 5.5.3 Loop unrolling 99 5.5.4 Double- Word access 100 5.5.5 Optimisation summary 100 5.6 Software pipelining 101 5.6.1 Software-pipelining procedure 105 5.6.1. 1 Writing linear assembly code 105 5.6.1. 2 Creating a dependency graph 105 5.6.1.3 Resource allocation 108 5.6.1.4 Scheduling table 108 5.6. 1.5 Generating assembly code 109 57 Linear assembly 111 5.7. 1 Hand optimisation of the dotp function using linear assembly 112 5.8 Avoiding memory banks 118 59 Optimisation using the tools 118 5.10 Laboratory experiments 123 5.11 Conclusion 126 References 126 The tMs320C66x interrupts 127 6.1 Introduction 127 6.1.1 Chip-level interrupt controller 129 6.2 The interrupt controller 135 63 Laboratory experiment 140 6.3.1 Experiment 1: USing the GIPIOs to trigger some functions 140 6.3.2 Experiment 2: Using the console to trigger an interrupt 140 64 Conclusion 143 References 144 7 Real-time g system: Tl-RTOS 145 7.1 Introduction 146 7.2 TI-RTOS 146 7.3 Real-time scheduling 148 7.3.1 Hardware interrupts(Hwis) 148 7.3.1.1 Setting an Hwi 149 7.3.1.2 Hwi hook functions 149 7.3.2 Software interrupts( Swis), including clock, periodic or single-shot functions 155 7.3.3 Tasks 155 7.3.3.1 Task hook functions 157 x Contents 7.3.4 Idle functions 158 7.3.5 Clock functions 158 7.3.6 Timer functions 158 7.3.7 Synchronisation 158 7.3.7.1 Semaphores 159 7.3.7.2 Semaphore pend 159 7.3.7.3 Semaphore_post 159 7.3.7.4 How to configure the semaphores 159 7. 8 Events 159 7.3.9 Summary 163 74 Dynamic memory management 163 7.4.1 Stack allocation 165 7.4.2 Heap allocation 165 7.4.3 Heap implementation 165 7.4.3.1 HeapMin implementation 165 7.4.3.2 HeapMem implementation 165 7.4.3.3 Heap Buf implementation 167 7.4.3.4 HeapMultiBuf implementation 171 7.5 Laboratory experiments 172 7.5.1 Lab 1 Manual setup of the clock (part 1)172 7.5.2 Lab 2: Manual setup of the clock (part 2)172 7.5.3 Lab 3: USing Hwis, Swis, tasks and clocks 174 7.5.4 Lab 4: Using events 187 7.5.5 Lab 5: Using the heaps 189 7.6 Conclusion 190 References 19 References(further reading) 191 8 Enhanced Direct Memory Access(EDMA3)controller 192 8.1 Introduction 192 8.2 Type of dmas available 193 83 EDMA controllers architecture 194 8.3. 1 The EDMA3 Channel Controller (EDMA3CC) 194 8.3.2 The eDmA3 transfer controller (EDMA3TC) 201 8.3.3 EDMA prioritisation 201 8.3.3. 1 Trigger source priority 202 8.3.3.2 Channel priority 203 8.3.3. 3 Dequeue priority 203 8.3.3.4 System(transfer controller) priority 203 8.4 Parameter RAM (PaRAM) 203 8.4.1 Channel options parameter(OPT)203 8.5 Transfer synchronisation dimensions 203 8.5.1 A- Synchronisation 204 8.5.2 AB- Synchronisation 204 8.6 Simple EDMA transfer 204 8.7 Chaining edma transfers 208 8.8 Linked admas 208 8.9 Laboratory experiments 210 Contents xi 8.9.1 Laboratory 1: Simple edma transfer 211 8.9.2 Laboratory 2: EDMA chaining transfer 211 89.3 Laboratory 3 EDMA link transfer 213 8.10 Conclusion 213 References 213 Inter-Processor Communication (PC) 214 9.1 Introduction 215 9.2 Texas Instruments ipc 217 9.3 Notify module 219 9.3.1 Laboratory experiment 222 94 Message 222 9.4.1 MessageQ protocol 224 9.4.2 Message priority 229 9.4.3 Thread synchronisation 229 9.5 Listmp module 233 9.6 Gatemp module 234 9.6.1 Initialising a GateMP parameter structure 234 9.6. 1.1 Types of gate protection 235 9.6.2 Creating a GateMP instance 236 9.6.3 Entering a GateMP 236 9.6.4 Leaving a gate 236 9.6.5 The list of functions that can be used by gateMP 237 97 Multi-processor Memory Allocation: Heap BufMP, HeapMemMP and HeapMultiBufMP 237 9.7.1 Heap Buf_Params 238 9.7.2 HeapMem_ Params 239 9.7.3 HeapMultiBuf_Params 239 9.7.4 Configuration example for HeapMultiBuf 239 9.8 Transport mechanisms for the IPC 241 9.9 Laboratory experiments with KeyStone I 241 9.9.1 Laboratory 1: Using MessageQ with multiple cores 241 9.9.1.1 Overview 242 9.9.2 Laboratory 2: USing ListMP, ShareRegion and GateMP 243 9.10 Laboratory experiments with Key Stone Ii 249 9.10.1 Laboratory experiment 1: Transferring a block of data 249 9.10. 1.1 Set the connection between the host(pc) and the Keystone 249 9.10. 1.2 Explore the arm code 250 9.10.1.3 Explore the dsp code 259 9.10.1.4 Compile and run the program 263 9.10.2 Laboratory experiment 2: Transferring a pointer 267 9. 10.2. 1 Explore the ARM code 267 9.10.2. 2 Explore the Dsp code 271 9. 10.2.3 Compile and run the program 278 9.11 Conclusion 278 References 278 xii Contents 10 Single and multicore debugging 280 10.1 Introduction 281 10.2 Software and hardware debugging 282 10.3 Debug architecture 282 103.1 Trace282 10.3. 1.1 Standard trace 282 10.3. 1.2 Event trace 283 10.3.1. 3 System trace 285 10.4 Advanced Event Triggering 286 10.4.1 Advanced Event Triggering logic 289 10.4.2 Unified Breakpoint manager 294 10.5 Unified Instrumentation architecture 295 10.5.1 Host-side tooling 295 10.5.2 Target-side tooling 295 10.5.2.1 Software instrumentation APis 297 10.5.2.2 Predefined software events and metadata 297 10.5.2. 3 Event loggers 297 10.5.2. Transports 297 10.5.2.5 SYS/BIOS event capture and transport 297 10.5.2.6 Multicore support 297 10.6 Debugging with the System Analyzer tools 298 10.6.1 Target-side coding with UIA APIs and the XDCtools 299 10.6.2 Logging events with Log_write functions 300 10.6. 3 Advance debugging using the diagnostic feature 301 10.6.4 Log Snapshot APIs for logging state information 302 107 Instrumentation with TI-RTOS and CCs 302 10.7.1 Using RTOS Object Viewer 302 10.7.2 Using the rtoS Analyzer and the System analyzer 303 10.7. 2.1 RTOS Analyzer 303 10.7.2.2 System analyzer 303 10.8 Laboratory sessions 305 10.8.1 Laboratory experiment 1 Using the Rtos rov 305 10.8. 2 Laboratory experiment 2: Using the RtoS Analyzer 305 10.8.3 Laboratory experiment 3: Using the System Analyzer 312 10.8.4 Laboratory experiment 4 Using diagnosis features 314 10.8.5 Laboratory experiment 5: Using a diagnostic feature with filtering 317 10.9 Conclusion 321 References 322 Further reading 323 11 Bootloader for Key Stone I and Keystone ll 324 11.1 Introduction 324 11.2 How to start the boot process 325 11.3 The boot process 325 11.4 ROM Bootloader(RBL)328 11.4. 1 The boot configuration format 336 11.4.1.1 Creating the boot parameter table 336 11.4.1.2 Creating the boot table 338 【实例截图】
【核心代码】